board/gateworks/gw_ventana/gw_ventana.c

   1 /*
   2  * Copyright (C) 2013 Gateworks Corporation
   3  *
   4  * Author: Tim Harvey <tharvey@gateworks.com>
   5  *
   6  * SPDX-License-Identifier: GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/mxc_hdmi.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/gpio.h>
  19 #include <asm/imx-common/iomux-v3.h>
  20 #include <asm/imx-common/mxc_i2c.h>
  21 #include <asm/imx-common/boot_mode.h>
  22 #include <asm/imx-common/sata.h>
  23 #include <asm/imx-common/video.h>
  24 #include <jffs2/load_kernel.h>
  25 #include <hwconfig.h>
  26 #include <i2c.h>
  27 #include <linux/ctype.h>
  28 #include <fdt_support.h>
  29 #include <fsl_esdhc.h>
  30 #include <miiphy.h>
  31 #include <mmc.h>
  32 #include <mtd_node.h>
  33 #include <netdev.h>
  34 #include <power/pmic.h>
  35 #include <power/ltc3676_pmic.h>
  36 #include <power/pfuze100_pmic.h>
  37 #include <fdt_support.h>
  38 #include <jffs2/load_kernel.h>
  39 #include <spi_flash.h>
  40
  41 #include "gsc.h"
  42 #include "ventana_eeprom.h"
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 /* GPIO's common to all baseboards */
  47 #define GP_PHY_RST      IMX_GPIO_NR(1, 30)
  48 #define GP_USB_OTG_PWR  IMX_GPIO_NR(3, 22)
  49 #define GP_SD3_CD       IMX_GPIO_NR(7, 0)
  50 #define GP_RS232_EN     IMX_GPIO_NR(2, 11)
  51 #define GP_MSATA_SEL    IMX_GPIO_NR(2, 8)
  52
  53 /* I2C bus numbers */
  54 #define I2C_GSC         0
  55 #define I2C_PMIC        1
  56
  57 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  58         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  59         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  60
  61 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  62         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
  63         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  64
  65 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  66         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  67         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  68
  69 #define SPI_PAD_CTRL (PAD_CTL_HYS |                             \
  70         PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
  71         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  72
  73 #define DIO_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |              \
  74         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  75         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  76
  77 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  78         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  79         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  80
  81 #define IRQ_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |              \
  82         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  83         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  84
  85 #define DIO_PAD_CFG   (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION)
  86
  87
  88 /*
  89  * EEPROM board info struct populated by read_eeprom so that we only have to
  90  * read it once.
  91  */
  92 static struct ventana_board_info ventana_info;
  93
  94 int board_type;
  95
  96 /* UART1: Function varies per baseboard */
  97 iomux_v3_cfg_t const uart1_pads[] = {
  98         IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  99         IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 100 };
 101
 102 /* UART2: Serial Console */
 103 iomux_v3_cfg_t const uart2_pads[] = {
 104         IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 105         IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 106 };
 107
 108 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 109
 110 /* I2C1: GSC */
 111 struct i2c_pads_info mx6q_i2c_pad_info0 = {
 112         .scl = {
 113                 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
 114                 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
 115                 .gp = IMX_GPIO_NR(3, 21)
 116         },
 117         .sda = {
 118                 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
 119                 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
 120                 .gp = IMX_GPIO_NR(3, 28)
 121         }
 122 };
 123 struct i2c_pads_info mx6dl_i2c_pad_info0 = {
 124         .scl = {
 125                 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
 126                 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
 127                 .gp = IMX_GPIO_NR(3, 21)
 128         },
 129         .sda = {
 130                 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
 131                 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
 132                 .gp = IMX_GPIO_NR(3, 28)
 133         }
 134 };
 135
 136 /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
 137 struct i2c_pads_info mx6q_i2c_pad_info1 = {
 138         .scl = {
 139                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
 140                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
 141                 .gp = IMX_GPIO_NR(4, 12)
 142         },
 143         .sda = {
 144                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
 145                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 146                 .gp = IMX_GPIO_NR(4, 13)
 147         }
 148 };
 149 struct i2c_pads_info mx6dl_i2c_pad_info1 = {
 150         .scl = {
 151                 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
 152                 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
 153                 .gp = IMX_GPIO_NR(4, 12)
 154         },
 155         .sda = {
 156                 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
 157                 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 158                 .gp = IMX_GPIO_NR(4, 13)
 159         }
 160 };
 161
 162 /* I2C3: Misc/Expansion */
 163 struct i2c_pads_info mx6q_i2c_pad_info2 = {
 164         .scl = {
 165                 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
 166                 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
 167                 .gp = IMX_GPIO_NR(1, 3)
 168         },
 169         .sda = {
 170                 .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
 171                 .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
 172                 .gp = IMX_GPIO_NR(1, 6)
 173         }
 174 };
 175 struct i2c_pads_info mx6dl_i2c_pad_info2 = {
 176         .scl = {
 177                 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
 178                 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
 179                 .gp = IMX_GPIO_NR(1, 3)
 180         },
 181         .sda = {
 182                 .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
 183                 .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
 184                 .gp = IMX_GPIO_NR(1, 6)
 185         }
 186 };
 187
 188 /* MMC */
 189 iomux_v3_cfg_t const usdhc3_pads[] = {
 190         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 191         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 192         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 193         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 194         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 195         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 196         /* CD */
 197         IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00  | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 198 };
 199
 200 /* ENET */
 201 iomux_v3_cfg_t const enet_pads[] = {
 202         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 203         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 204         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 205         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 206         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 207         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 208         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 209         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
 210                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 211         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
 212                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 213         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 214         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 215         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 216         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 217         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 218         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
 219                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 220         /* PHY nRST */
 221         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
 222 };
 223
 224 /* NAND */
 225 iomux_v3_cfg_t const nfc_pads[] = {
 226         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 227         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 228         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 229         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 230         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 231         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 232         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 233         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 234         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 235         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 236         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 237         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 238         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 239         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 240         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 241 };
 242
 243 #ifdef CONFIG_CMD_NAND
 244 static void setup_gpmi_nand(void)
 245 {
 246         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 247
 248         /* config gpmi nand iomux */
 249         SETUP_IOMUX_PADS(nfc_pads);
 250
 251         /* config gpmi and bch clock to 100 MHz */
 252         clrsetbits_le32(&mxc_ccm->cs2cdr,
 253                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 254                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 255                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 256                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 257                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 258                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 259
 260         /* enable gpmi and bch clock gating */
 261         setbits_le32(&mxc_ccm->CCGR4,
 262                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 263                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 264                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 265                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 266                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 267
 268         /* enable apbh clock gating */
 269         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 270 }
 271 #endif
 272
 273 static void setup_iomux_enet(void)
 274 {
 275         SETUP_IOMUX_PADS(enet_pads);
 276
 277         /* toggle PHY_RST# */
 278         gpio_direction_output(GP_PHY_RST, 0);
 279         mdelay(2);
 280         gpio_set_value(GP_PHY_RST, 1);
 281 }
 282
 283 static void setup_iomux_uart(void)
 284 {
 285         SETUP_IOMUX_PADS(uart1_pads);
 286         SETUP_IOMUX_PADS(uart2_pads);
 287 }
 288
 289 #ifdef CONFIG_USB_EHCI_MX6
 290 iomux_v3_cfg_t const usb_pads[] = {
 291         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID   | DIO_PAD_CFG),
 292         IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
 293         /* OTG PWR */
 294         IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22  | DIO_PAD_CFG),
 295 };
 296
 297 int board_ehci_hcd_init(int port)
 298 {
 299         struct ventana_board_info *info = &ventana_info;
 300
 301         SETUP_IOMUX_PADS(usb_pads);
 302
 303         /* Reset USB HUB (present on GW54xx/GW53xx) */
 304         switch (info->model[3]) {
 305         case '3': /* GW53xx */
 306                 SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG);
 307                 gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
 308                 mdelay(2);
 309                 gpio_set_value(IMX_GPIO_NR(1, 9), 1);
 310                 break;
 311         case '4': /* GW54xx */
 312                 SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG);
 313                 gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
 314                 mdelay(2);
 315                 gpio_set_value(IMX_GPIO_NR(1, 16), 1);
 316                 break;
 317         }
 318
 319         return 0;
 320 }
 321
 322 int board_ehci_power(int port, int on)
 323 {
 324         if (port)
 325                 return 0;
 326         gpio_set_value(GP_USB_OTG_PWR, on);
 327         return 0;
 328 }
 329 #endif /* CONFIG_USB_EHCI_MX6 */
 330
 331 #ifdef CONFIG_FSL_ESDHC
 332 struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
 333
 334 int board_mmc_getcd(struct mmc *mmc)
 335 {
 336         /* Card Detect */
 337         gpio_direction_input(GP_SD3_CD);
 338         return !gpio_get_value(GP_SD3_CD);
 339 }
 340
 341 int board_mmc_init(bd_t *bis)
 342 {
 343         /* Only one USDHC controller on Ventana */
 344         SETUP_IOMUX_PADS(usdhc3_pads);
 345         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 346         usdhc_cfg.max_bus_width = 4;
 347
 348         return fsl_esdhc_initialize(bis, &usdhc_cfg);
 349 }
 350 #endif /* CONFIG_FSL_ESDHC */
 351
 352 #ifdef CONFIG_MXC_SPI
 353 iomux_v3_cfg_t const ecspi1_pads[] = {
 354         /* SS1 */
 355         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 356         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 357         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 358         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 359 };
 360
 361 static void setup_spi(void)
 362 {
 363         gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
 364         SETUP_IOMUX_PADS(ecspi1_pads);
 365 }
 366 #endif
 367
 368 /* configure eth0 PHY board-specific LED behavior */
 369 int board_phy_config(struct phy_device *phydev)
 370 {
 371         unsigned short val;
 372
 373         /* Marvel 88E1510 */
 374         if (phydev->phy_id == 0x1410dd1) {
 375                 /*
 376                  * Page 3, Register 16: LED[2:0] Function Control Register
 377                  * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
 378                  * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
 379                  */
 380                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
 381                 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
 382                 val &= 0xff00;
 383                 val |= 0x0017;
 384                 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
 385                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 386         }
 387
 388         if (phydev->drv->config)
 389                 phydev->drv->config(phydev);
 390
 391         return 0;
 392 }
 393
 394 int board_eth_init(bd_t *bis)
 395 {
 396         setup_iomux_enet();
 397
 398 #ifdef CONFIG_FEC_MXC
 399         cpu_eth_init(bis);
 400 #endif
 401
 402 #ifdef CONFIG_CI_UDC
 403         /* For otg ethernet*/
 404         usb_eth_initialize(bis);
 405 #endif
 406
 407         return 0;
 408 }
 409
 410 #if defined(CONFIG_VIDEO_IPUV3)
 411
 412 static void enable_hdmi(struct display_info_t const *dev)
 413 {
 414         imx_enable_hdmi_phy();
 415 }
 416
 417 static int detect_i2c(struct display_info_t const *dev)
 418 {
 419         return i2c_set_bus_num(dev->bus) == 0 &&
 420                 i2c_probe(dev->addr) == 0;
 421 }
 422
 423 static void enable_lvds(struct display_info_t const *dev)
 424 {
 425         struct iomuxc *iomux = (struct iomuxc *)
 426                                 IOMUXC_BASE_ADDR;
 427
 428         /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
 429         u32 reg = readl(&iomux->gpr[2]);
 430         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 431         writel(reg, &iomux->gpr[2]);
 432
 433         /* Enable Backlight */
 434         SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
 435         gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
 436 }
 437
 438 struct display_info_t const displays[] = {{
 439         /* HDMI Output */
 440         .bus    = -1,
 441         .addr   = 0,
 442         .pixfmt = IPU_PIX_FMT_RGB24,
 443         .detect = detect_hdmi,
 444         .enable = enable_hdmi,
 445         .mode   = {
 446                 .name           = "HDMI",
 447                 .refresh        = 60,
 448                 .xres           = 1024,
 449                 .yres           = 768,
 450                 .pixclock       = 15385,
 451                 .left_margin    = 220,
 452                 .right_margin   = 40,
 453                 .upper_margin   = 21,
 454                 .lower_margin   = 7,
 455                 .hsync_len      = 60,
 456                 .vsync_len      = 10,
 457                 .sync           = FB_SYNC_EXT,
 458                 .vmode          = FB_VMODE_NONINTERLACED
 459 } }, {
 460         /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
 461         .bus    = 2,
 462         .addr   = 0x4,
 463         .pixfmt = IPU_PIX_FMT_LVDS666,
 464         .detect = detect_i2c,
 465         .enable = enable_lvds,
 466         .mode   = {
 467                 .name           = "Hannstar-XGA",
 468                 .refresh        = 60,
 469                 .xres           = 1024,
 470                 .yres           = 768,
 471                 .pixclock       = 15385,
 472                 .left_margin    = 220,
 473                 .right_margin   = 40,
 474                 .upper_margin   = 21,
 475                 .lower_margin   = 7,
 476                 .hsync_len      = 60,
 477                 .vsync_len      = 10,
 478                 .sync           = FB_SYNC_EXT,
 479                 .vmode          = FB_VMODE_NONINTERLACED
 480 } } };
 481 size_t display_count = ARRAY_SIZE(displays);
 482
 483 static void setup_display(void)
 484 {
 485         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 486         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 487         int reg;
 488
 489         enable_ipu_clock();
 490         imx_setup_hdmi();
 491         /* Turn on LDB0,IPU,IPU DI0 clocks */
 492         reg = __raw_readl(&mxc_ccm->CCGR3);
 493         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 494         writel(reg, &mxc_ccm->CCGR3);
 495
 496         /* set LDB0, LDB1 clk select to 011/011 */
 497         reg = readl(&mxc_ccm->cs2cdr);
 498         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 499                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 500         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 501               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 502         writel(reg, &mxc_ccm->cs2cdr);
 503
 504         reg = readl(&mxc_ccm->cscmr2);
 505         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 506         writel(reg, &mxc_ccm->cscmr2);
 507
 508         reg = readl(&mxc_ccm->chsccdr);
 509         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 510                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 511         writel(reg, &mxc_ccm->chsccdr);
 512
 513         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 514              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 515              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 516              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 517              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 518              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 519              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 520              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 521              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 522         writel(reg, &iomux->gpr[2]);
 523
 524         reg = readl(&iomux->gpr[3]);
 525         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 526             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 527                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 528         writel(reg, &iomux->gpr[3]);
 529
 530         /* Backlight CABEN on LVDS connector */
 531         SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
 532         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 533 }
 534 #endif /* CONFIG_VIDEO_IPUV3 */
 535
 536 /*
 537  * Baseboard specific GPIO
 538  */
 539
 540 /* common to add baseboards */
 541 static iomux_v3_cfg_t const gw_gpio_pads[] = {
 542         /* MSATA_EN */
 543         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
 544         /* RS232_EN# */
 545         IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
 546 };
 547
 548 /* prototype */
 549 static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
 550         /* PANLEDG# */
 551         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 552         /* PANLEDR# */
 553         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 554         /* LOCLED# */
 555         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 556         /* RS485_EN */
 557         IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
 558         /* IOEXP_PWREN# */
 559         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 560         /* IOEXP_IRQ# */
 561         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 562         /* VID_EN */
 563         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 564         /* DIOI2C_DIS# */
 565         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 566         /* PCICK_SSON */
 567         IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
 568         /* PCI_RST# */
 569         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 570 };
 571
 572 static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
 573         /* PANLEDG# */
 574         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 575         /* PANLEDR# */
 576         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 577         /* IOEXP_PWREN# */
 578         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 579         /* IOEXP_IRQ# */
 580         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 581
 582         /* GPS_SHDN */
 583         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 584         /* VID_PWR */
 585         IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
 586         /* PCI_RST# */
 587         IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
 588 };
 589
 590 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
 591         /* PANLEDG# */
 592         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 593         /* PANLEDR# */
 594         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 595         /* IOEXP_PWREN# */
 596         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 597         /* IOEXP_IRQ# */
 598         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 599
 600         /* MX6_LOCLED# */
 601         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 602         /* GPS_SHDN */
 603         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
 604         /* USBOTG_SEL */
 605         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
 606         /* VID_PWR */
 607         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 608         /* PCI_RST# */
 609         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 610 };
 611
 612 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
 613         /* PANLEDG# */
 614         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 615         /* PANLEDR# */
 616         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 617         /* IOEXP_PWREN# */
 618         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
 619         /* IOEXP_IRQ# */
 620         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 621         /* DIOI2C_DIS# */
 622         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 623
 624         /* MX6_LOCLED# */
 625         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 626         /* GPS_SHDN */
 627         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
 628         /* VID_EN */
 629         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 630         /* PCI_RST# */
 631         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 632 };
 633
 634 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
 635         /* PANLEDG# */
 636         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
 637         /* PANLEDR# */
 638         IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
 639         /* MX6_LOCLED# */
 640         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
 641         /* MIPI_DIO */
 642         IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG),
 643         /* RS485_EN */
 644         IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG),
 645         /* IOEXP_PWREN# */
 646         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
 647         /* IOEXP_IRQ# */
 648         IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
 649         /* DIOI2C_DIS# */
 650         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
 651         /* PCICK_SSON */
 652         IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
 653         /* PCI_RST# */
 654         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
 655         /* VID_EN */
 656         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
 657 };
 658
 659 /*
 660  * each baseboard has 4 user configurable Digital IO lines which can
 661  * be pinmuxed as a GPIO or in some cases a PWM
 662  */
 663 struct dio_cfg {
 664         iomux_v3_cfg_t gpio_padmux[2];
 665         unsigned gpio_param;
 666         iomux_v3_cfg_t pwm_padmux[2];
 667         unsigned pwm_param;
 668 };
 669
 670 struct ventana {
 671         /* pinmux */
 672         iomux_v3_cfg_t const *gpio_pads;
 673         int num_pads;
 674         /* DIO pinmux/val */
 675         struct dio_cfg dio_cfg[4];
 676         /* various gpios (0 if non-existent) */
 677         int leds[3];
 678         int pcie_rst;
 679         int mezz_pwren;
 680         int mezz_irq;
 681         int rs485en;
 682         int gps_shdn;
 683         int vidin_en;
 684         int dioi2c_en;
 685         int pcie_sson;
 686         int usb_sel;
 687 };
 688
 689 struct ventana gpio_cfg[] = {
 690         /* GW5400proto */
 691         {
 692                 .gpio_pads = gw54xx_gpio_pads,
 693                 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
 694                 .dio_cfg = {
 695                         {
 696                                 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
 697                                 IMX_GPIO_NR(1, 9),
 698                                 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
 699                                 1
 700                         },
 701                         {
 702                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 703                                 IMX_GPIO_NR(1, 19),
 704                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 705                                 2
 706                         },
 707                         {
 708                                 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
 709                                 IMX_GPIO_NR(2, 9),
 710                                 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
 711                                 3
 712                         },
 713                         {
 714                                 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
 715                                 IMX_GPIO_NR(2, 10),
 716                                 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
 717                                 4
 718                         },
 719                 },
 720                 .leds = {
 721                         IMX_GPIO_NR(4, 6),
 722                         IMX_GPIO_NR(4, 10),
 723                         IMX_GPIO_NR(4, 15),
 724                 },
 725                 .pcie_rst = IMX_GPIO_NR(1, 29),
 726                 .mezz_pwren = IMX_GPIO_NR(4, 7),
 727                 .mezz_irq = IMX_GPIO_NR(4, 9),
 728                 .rs485en = IMX_GPIO_NR(3, 24),
 729                 .dioi2c_en = IMX_GPIO_NR(4,  5),
 730                 .pcie_sson = IMX_GPIO_NR(1, 20),
 731         },
 732
 733         /* GW51xx */
 734         {
 735                 .gpio_pads = gw51xx_gpio_pads,
 736                 .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
 737                 .dio_cfg = {
 738                         {
 739                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 740                                 IMX_GPIO_NR(1, 16),
 741                                 { 0, 0 },
 742                                 0
 743                         },
 744                         {
 745                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 746                                 IMX_GPIO_NR(1, 19),
 747                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 748                                 2
 749                         },
 750                         {
 751                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 752                                 IMX_GPIO_NR(1, 17),
 753                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 754                                 3
 755                         },
 756                         {
 757                                 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
 758                                 IMX_GPIO_NR(1, 18),
 759                                 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
 760                                 4
 761                         },
 762                 },
 763                 .leds = {
 764                         IMX_GPIO_NR(4, 6),
 765                         IMX_GPIO_NR(4, 10),
 766                 },
 767                 .pcie_rst = IMX_GPIO_NR(1, 0),
 768                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 769                 .mezz_irq = IMX_GPIO_NR(2, 18),
 770                 .gps_shdn = IMX_GPIO_NR(1, 2),
 771                 .vidin_en = IMX_GPIO_NR(5, 20),
 772         },
 773
 774         /* GW52xx */
 775         {
 776                 .gpio_pads = gw52xx_gpio_pads,
 777                 .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
 778                 .dio_cfg = {
 779                         {
 780                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 781                                 IMX_GPIO_NR(1, 16),
 782                                 { 0, 0 },
 783                                 0
 784                         },
 785                         {
 786                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 787                                 IMX_GPIO_NR(1, 19),
 788                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 789                                 2
 790                         },
 791                         {
 792                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 793                                 IMX_GPIO_NR(1, 17),
 794                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 795                                 3
 796                         },
 797                         {
 798                                 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
 799                                 IMX_GPIO_NR(1, 20),
 800                                 { 0, 0 },
 801                                 0
 802                         },
 803                 },
 804                 .leds = {
 805                         IMX_GPIO_NR(4, 6),
 806                         IMX_GPIO_NR(4, 7),
 807                         IMX_GPIO_NR(4, 15),
 808                 },
 809                 .pcie_rst = IMX_GPIO_NR(1, 29),
 810                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 811                 .mezz_irq = IMX_GPIO_NR(2, 18),
 812                 .gps_shdn = IMX_GPIO_NR(1, 27),
 813                 .vidin_en = IMX_GPIO_NR(3, 31),
 814                 .usb_sel = IMX_GPIO_NR(1, 2),
 815         },
 816
 817         /* GW53xx */
 818         {
 819                 .gpio_pads = gw53xx_gpio_pads,
 820                 .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
 821                 .dio_cfg = {
 822                         {
 823                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 824                                 IMX_GPIO_NR(1, 16),
 825                                 { 0, 0 },
 826                                 0
 827                         },
 828                         {
 829                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 830                                 IMX_GPIO_NR(1, 19),
 831                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 832                                 2
 833                         },
 834                         {
 835                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 836                                 IMX_GPIO_NR(1, 17),
 837                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 838                                 3
 839                         },
 840                         {
 841                                 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
 842                                 IMX_GPIO_NR(1, 20),
 843                                 { 0, 0 },
 844                                 0
 845                         },
 846                 },
 847                 .leds = {
 848                         IMX_GPIO_NR(4, 6),
 849                         IMX_GPIO_NR(4, 7),
 850                         IMX_GPIO_NR(4, 15),
 851                 },
 852                 .pcie_rst = IMX_GPIO_NR(1, 29),
 853                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 854                 .mezz_irq = IMX_GPIO_NR(2, 18),
 855                 .gps_shdn = IMX_GPIO_NR(1, 27),
 856                 .vidin_en = IMX_GPIO_NR(3, 31),
 857         },
 858
 859         /* GW54xx */
 860         {
 861                 .gpio_pads = gw54xx_gpio_pads,
 862                 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
 863                 .dio_cfg = {
 864                         {
 865                                 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
 866                                 IMX_GPIO_NR(1, 9),
 867                                 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
 868                                 1
 869                         },
 870                         {
 871                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 872                                 IMX_GPIO_NR(1, 19),
 873                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 874                                 2
 875                         },
 876                         {
 877                                 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
 878                                 IMX_GPIO_NR(2, 9),
 879                                 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
 880                                 3
 881                         },
 882                         {
 883                                 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
 884                                 IMX_GPIO_NR(2, 10),
 885                                 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
 886                                 4
 887                         },
 888                 },
 889                 .leds = {
 890                         IMX_GPIO_NR(4, 6),
 891                         IMX_GPIO_NR(4, 7),
 892                         IMX_GPIO_NR(4, 15),
 893                 },
 894                 .pcie_rst = IMX_GPIO_NR(1, 29),
 895                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 896                 .mezz_irq = IMX_GPIO_NR(2, 18),
 897                 .rs485en = IMX_GPIO_NR(7, 1),
 898                 .vidin_en = IMX_GPIO_NR(3, 31),
 899                 .dioi2c_en = IMX_GPIO_NR(4,  5),
 900                 .pcie_sson = IMX_GPIO_NR(1, 20),
 901         },
 902 };
 903
 904 /* setup board specific PMIC */
 905 int power_init_board(void)
 906 {
 907         struct pmic *p;
 908         u32 reg;
 909
 910         /* configure PFUZE100 PMIC */
 911         if (board_type == GW54xx || board_type == GW54proto) {
 912                 power_pfuze100_init(I2C_PMIC);
 913                 p = pmic_get("PFUZE100");
 914                 if (p && !pmic_probe(p)) {
 915                         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 916                         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 917
 918                         /* Set VGEN1 to 1.5V and enable */
 919                         pmic_reg_read(p, PFUZE100_VGEN1VOL, &reg);
 920                         reg &= ~(LDO_VOL_MASK);
 921                         reg |= (LDOA_1_50V | LDO_EN);
 922                         pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
 923
 924                         /* Set SWBST to 5.0V and enable */
 925                         pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
 926                         reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
 927                         reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
 928                         pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
 929                 }
 930         }
 931
 932         /* configure LTC3676 PMIC */
 933         else {
 934                 power_ltc3676_init(I2C_PMIC);
 935                 p = pmic_get("LTC3676_PMIC");
 936                 if (p && !pmic_probe(p)) {
 937                         puts("PMIC:  LTC3676\n");
 938                         /* set board-specific scalar to 1225mV for IMX6Q@1GHz */
 939                         if (is_cpu_type(MXC_CPU_MX6Q)) {
 940                                 /* mask PGOOD during SW1 transition */
 941                                 reg = 0x1d | LTC3676_PGOOD_MASK;
 942                                 pmic_reg_write(p, LTC3676_DVB1B, reg);
 943                                 /* set SW1 (VDD_SOC) to 1259mV */
 944                                 reg = 0x1d;
 945                                 pmic_reg_write(p, LTC3676_DVB1A, reg);
 946
 947                                 /* mask PGOOD during SW3 transition */
 948                                 reg = 0x1d | LTC3676_PGOOD_MASK;
 949                                 pmic_reg_write(p, LTC3676_DVB3B, reg);
 950                                 /*set SW3 (VDD_ARM) to 1259mV */
 951                                 reg = 0x1d;
 952                                 pmic_reg_write(p, LTC3676_DVB3A, reg);
 953                         }
 954                 }
 955         }
 956
 957         return 0;
 958 }
 959
 960 /* setup GPIO pinmux and default configuration per baseboard */
 961 static void setup_board_gpio(int board)
 962 {
 963         struct ventana_board_info *info = &ventana_info;
 964         const char *s;
 965         char arg[10];
 966         size_t len;
 967         int i;
 968         int quiet = simple_strtol(getenv("quiet"), NULL, 10);
 969
 970         if (board >= GW_UNKNOWN)
 971                 return;
 972
 973         /* RS232_EN# */
 974         gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
 975
 976         /* MSATA Enable */
 977         if (is_cpu_type(MXC_CPU_MX6Q) &&
 978             test_bit(EECONFIG_SATA, info->config)) {
 979                 gpio_direction_output(GP_MSATA_SEL,
 980                                       (hwconfig("msata")) ?  1 : 0);
 981         } else {
 982                 gpio_direction_output(GP_MSATA_SEL, 0);
 983         }
 984
 985         /*
 986          * assert PCI_RST# (released by OS when clock is valid)
 987          * TODO: figure out why leaving this de-asserted from PCI scan on boot
 988          *       causes linux pcie driver to hang during enumeration
 989          */
 990         gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
 991
 992         /* turn off (active-high) user LED's */
 993         for (i = 0; i < 4; i++) {
 994                 if (gpio_cfg[board].leds[i])
 995                         gpio_direction_output(gpio_cfg[board].leds[i], 1);
 996         }
 997
 998         /* Expansion Mezzanine IO */
 999         gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
1000         gpio_direction_input(gpio_cfg[board].mezz_irq);
1001
1002         /* RS485 Transmit Enable */
1003         if (gpio_cfg[board].rs485en)
1004                 gpio_direction_output(gpio_cfg[board].rs485en, 0);
1005
1006         /* GPS_SHDN */
1007         if (gpio_cfg[board].gps_shdn)
1008                 gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
1009
1010         /* Analog video codec power enable */
1011         if (gpio_cfg[board].vidin_en)
1012                 gpio_direction_output(gpio_cfg[board].vidin_en, 1);
1013
1014         /* DIOI2C_DIS# */
1015         if (gpio_cfg[board].dioi2c_en)
1016                 gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
1017
1018         /* PCICK_SSON: disable spread-spectrum clock */
1019         if (gpio_cfg[board].pcie_sson)
1020                 gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
1021
1022         /* USBOTG Select (PCISKT or FrontPanel) */
1023         if (gpio_cfg[board].usb_sel)
1024                 gpio_direction_output(gpio_cfg[board].usb_sel, 0);
1025
1026         /*
1027          * Configure DIO pinmux/padctl registers
1028          * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
1029          */
1030         for (i = 0; i < 4; i++) {
1031                 struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
1032                 iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
1033                 unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
1034
1035                 sprintf(arg, "dio%d", i);
1036                 if (!hwconfig(arg))
1037                         continue;
1038                 s = hwconfig_subarg(arg, "padctrl", &len);
1039                 if (s) {
1040                         ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16)
1041                                             & 0x1ffff) | MUX_MODE_SION;
1042                 }
1043                 if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
1044                         if (!quiet) {
1045                                 printf("DIO%d:  GPIO%d_IO%02d (gpio-%d)\n", i,
1046                                        (cfg->gpio_param/32)+1,
1047                                        cfg->gpio_param%32,
1048                                        cfg->gpio_param);
1049                         }
1050                         imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
1051                                                ctrl);
1052                         gpio_direction_input(cfg->gpio_param);
1053                 } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
1054                            cfg->pwm_padmux) {
1055                         if (!quiet)
1056                                 printf("DIO%d:  pwm%d\n", i, cfg->pwm_param);
1057                         imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
1058                                                MUX_PAD_CTRL(ctrl));
1059                 }
1060         }
1061
1062         if (!quiet) {
1063                 if (is_cpu_type(MXC_CPU_MX6Q) &&
1064                     (test_bit(EECONFIG_SATA, info->config))) {
1065                         printf("MSATA: %s\n", (hwconfig("msata") ?
1066                                "enabled" : "disabled"));
1067                 }
1068                 printf("RS232: %s\n", (hwconfig("rs232")) ?
1069                        "enabled" : "disabled");
1070         }
1071 }
1072
1073 #if defined(CONFIG_CMD_PCI)
1074 int imx6_pcie_toggle_reset(void)
1075 {
1076         if (board_type < GW_UNKNOWN) {
1077                 uint pin = gpio_cfg[board_type].pcie_rst;
1078                 gpio_direction_output(pin, 0);
1079                 mdelay(50);
1080                 gpio_direction_output(pin, 1);
1081         }
1082         return 0;
1083 }
1084 #endif /* CONFIG_CMD_PCI */
1085
1086 #ifdef CONFIG_SERIAL_TAG
1087 /*
1088  * called when setting up ATAGS before booting kernel
1089  * populate serialnum from the following (in order of priority):
1090  *   serial# env var
1091  *   eeprom
1092  */
1093 void get_board_serial(struct tag_serialnr *serialnr)
1094 {
1095         char *serial = getenv("serial#");
1096
1097         if (serial) {
1098                 serialnr->high = 0;
1099                 serialnr->low = simple_strtoul(serial, NULL, 10);
1100         } else if (ventana_info.model[0]) {
1101                 serialnr->high = 0;
1102                 serialnr->low = ventana_info.serial;
1103         } else {
1104                 serialnr->high = 0;
1105                 serialnr->low = 0;
1106         }
1107 }
1108 #endif
1109
1110 /*
1111  * Board Support
1112  */
1113
1114 /* called from SPL board_init_f() */
1115 int board_early_init_f(void)
1116 {
1117         setup_iomux_uart();
1118         gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
1119
1120 #if defined(CONFIG_VIDEO_IPUV3)
1121         setup_display();
1122 #endif
1123         return 0;
1124 }
1125
1126 int dram_init(void)
1127 {
1128         gd->ram_size = imx_ddr_size();
1129         return 0;
1130 }
1131
1132 int board_init(void)
1133 {
1134         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
1135
1136         clrsetbits_le32(&iomuxc_regs->gpr[1],
1137                         IOMUXC_GPR1_OTG_ID_MASK,
1138                         IOMUXC_GPR1_OTG_ID_GPIO1);
1139
1140         /* address of linux boot parameters */
1141         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
1142
1143 #ifdef CONFIG_CMD_NAND
1144         setup_gpmi_nand();
1145 #endif
1146 #ifdef CONFIG_MXC_SPI
1147         setup_spi();
1148 #endif
1149         if (is_cpu_type(MXC_CPU_MX6Q)) {
1150                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
1151                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
1152                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
1153         } else {
1154                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
1155                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
1156                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
1157         }
1158
1159 #ifdef CONFIG_CMD_SATA
1160         setup_sata();
1161 #endif
1162         /* read Gateworks EEPROM into global struct (used later) */
1163         board_type = read_eeprom(I2C_GSC, &ventana_info);
1164
1165         /* board-specifc GPIO iomux */
1166         SETUP_IOMUX_PADS(gw_gpio_pads);
1167         if (board_type < GW_UNKNOWN) {
1168                 iomux_v3_cfg_t const *p = gpio_cfg[board_type].gpio_pads;
1169                 int count = gpio_cfg[board_type].num_pads;
1170
1171                 imx_iomux_v3_setup_multiple_pads(p, count);
1172         }
1173
1174         return 0;
1175 }
1176
1177 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
1178 /*
1179  * called during late init (after relocation and after board_init())
1180  * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
1181  * EEPROM read.
1182  */
1183 int checkboard(void)
1184 {
1185         struct ventana_board_info *info = &ventana_info;
1186         unsigned char buf[4];
1187         const char *p;
1188         int quiet; /* Quiet or minimal output mode */
1189
1190         quiet = 0;
1191         p = getenv("quiet");
1192         if (p)
1193                 quiet = simple_strtol(p, NULL, 10);
1194         else
1195                 setenv("quiet", "0");
1196
1197         puts("\nGateworks Corporation Copyright 2014\n");
1198         if (info->model[0]) {
1199                 printf("Model: %s\n", info->model);
1200                 printf("MFGDate: %02x-%02x-%02x%02x\n",
1201                        info->mfgdate[0], info->mfgdate[1],
1202                        info->mfgdate[2], info->mfgdate[3]);
1203                 printf("Serial:%d\n", info->serial);
1204         } else {
1205                 puts("Invalid EEPROM - board will not function fully\n");
1206         }
1207         if (quiet)
1208                 return 0;
1209
1210         /* Display GSC firmware revision/CRC/status */
1211         i2c_set_bus_num(I2C_GSC);
1212         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) {
1213                 printf("GSC:   v%d", buf[0]);
1214                 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) {
1215                         printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */
1216                         printf(" 0x%02x", buf[0]); /* irq status */
1217                 }
1218                 puts("\n");
1219         }
1220         /* Display RTC */
1221         if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
1222                 printf("RTC:   %d\n",
1223                        buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
1224         }
1225
1226         return 0;
1227 }
1228 #endif
1229
1230 #ifdef CONFIG_CMD_BMODE
1231 /*
1232  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
1233  * see Table 8-11 and Table 5-9
1234  *  BOOT_CFG1[7] = 1 (boot from NAND)
1235  *  BOOT_CFG1[5] = 0 - raw NAND
1236  *  BOOT_CFG1[4] = 0 - default pad settings
1237  *  BOOT_CFG1[3:2] = 00 - devices = 1
1238  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
1239  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
1240  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
1241  *  BOOT_CFG2[0] = 0 - Reset time 12ms
1242  */
1243 static const struct boot_mode board_boot_modes[] = {
1244         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
1245         { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
1246         { NULL, 0 },
1247 };
1248 #endif
1249
1250 /* late init */
1251 int misc_init_r(void)
1252 {
1253         struct ventana_board_info *info = &ventana_info;
1254         unsigned char reg;
1255
1256         /* set env vars based on EEPROM data */
1257         if (ventana_info.model[0]) {
1258                 char str[16], fdt[36];
1259                 char *p;
1260                 const char *cputype = "";
1261                 int i;
1262
1263                 /*
1264                  * FDT name will be prefixed with CPU type.  Three versions
1265                  * will be created each increasingly generic and bootloader
1266                  * env scripts will try loading each from most specific to
1267                  * least.
1268                  */
1269                 if (is_cpu_type(MXC_CPU_MX6Q) ||
1270                     is_cpu_type(MXC_CPU_MX6D))
1271                         cputype = "imx6q";
1272                 else if (is_cpu_type(MXC_CPU_MX6DL) ||
1273                          is_cpu_type(MXC_CPU_MX6SOLO))
1274                         cputype = "imx6dl";
1275                 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
1276                         setenv("flash_layout", "large");
1277                 else
1278                         setenv("flash_layout", "normal");
1279                 memset(str, 0, sizeof(str));
1280                 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
1281                         str[i] = tolower(info->model[i]);
1282                 if (!getenv("model"))
1283                         setenv("model", str);
1284                 if (!getenv("fdt_file")) {
1285                         sprintf(fdt, "%s-%s.dtb", cputype, str);
1286                         setenv("fdt_file", fdt);
1287                 }
1288                 p = strchr(str, '-');
1289                 if (p) {
1290                         *p++ = 0;
1291
1292                         setenv("model_base", str);
1293                         if (!getenv("fdt_file1")) {
1294                                 sprintf(fdt, "%s-%s.dtb", cputype, str);
1295                                 setenv("fdt_file1", fdt);
1296                         }
1297                         str[4] = 'x';
1298                         str[5] = 'x';
1299                         str[6] = 0;
1300                         if (!getenv("fdt_file2")) {
1301                                 sprintf(fdt, "%s-%s.dtb", cputype, str);
1302                                 setenv("fdt_file2", fdt);
1303                         }
1304                 }
1305
1306                 /* initialize env from EEPROM */
1307                 if (test_bit(EECONFIG_ETH0, info->config) &&
1308                     !getenv("ethaddr")) {
1309                         eth_setenv_enetaddr("ethaddr", info->mac0);
1310                 }
1311                 if (test_bit(EECONFIG_ETH1, info->config) &&
1312                     !getenv("eth1addr")) {
1313                         eth_setenv_enetaddr("eth1addr", info->mac1);
1314                 }
1315
1316                 /* board serial-number */
1317                 sprintf(str, "%6d", info->serial);
1318                 setenv("serial#", str);
1319         }
1320
1321
1322         /* setup baseboard specific GPIO pinmux and config */
1323         setup_board_gpio(board_type);
1324
1325 #ifdef CONFIG_CMD_BMODE
1326         add_board_boot_modes(board_boot_modes);
1327 #endif
1328
1329         /*
1330          *  The Gateworks System Controller implements a boot
1331          *  watchdog (always enabled) as a workaround for IMX6 boot related
1332          *  errata such as:
1333          *    ERR005768 - no fix
1334          *    ERR006282 - fixed in silicon r1.3
1335          *    ERR007117 - fixed in silicon r1.3
1336          *    ERR007220 - fixed in silicon r1.3
1337          *  see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
1338          *
1339          * Disable the boot watchdog and display/clear the timeout flag if set
1340          */
1341         i2c_set_bus_num(I2C_GSC);
1342         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) {
1343                 reg |= (1 << GSC_SC_CTRL1_WDDIS);
1344                 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
1345                         puts("Error: could not disable GSC Watchdog\n");
1346         } else {
1347                 puts("Error: could not disable GSC Watchdog\n");
1348         }
1349         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1)) {
1350                 if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */
1351                         puts("GSC boot watchdog timeout detected\n");
1352                         reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */
1353                         gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1);
1354                 }
1355         }
1356
1357         return 0;
1358 }
1359
1360 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1361
1362 /* FDT aliases associated with EEPROM config bits */
1363 const char *fdt_aliases[] = {
1364         "ethernet0",
1365         "ethernet1",
1366         "hdmi_out",
1367         "ahci0",
1368         "pcie",
1369         "ssi0",
1370         "ssi1",
1371         "lcd0",
1372         "lvds0",
1373         "lvds1",
1374         "usb0",
1375         "usb1",
1376         "mmc0",
1377         "mmc1",
1378         "mmc2",
1379         "mmc3",
1380         "uart0",
1381         "uart1",
1382         "uart2",
1383         "uart3",
1384         "uart4",
1385         "ipu0",
1386         "ipu1",
1387         "can0",
1388         "mipi_dsi",
1389         "mipi_csi",
1390         "tzasc0",
1391         "tzasc1",
1392         "i2c0",
1393         "i2c1",
1394         "i2c2",
1395         "vpu",
1396         "csi0",
1397         "csi1",
1398         NULL,
1399         NULL,
1400         NULL,
1401         NULL,
1402         NULL,
1403         NULL,
1404         "spi0",
1405         "spi1",
1406         "spi2",
1407         "spi3",
1408         "spi4",
1409         "spi5",
1410         NULL,
1411         NULL,
1412         "pps",
1413         NULL,
1414         NULL,
1415         NULL,
1416         "hdmi_in",
1417         "cvbs_out",
1418         "cvbs_in",
1419         "nand",
1420         NULL,
1421         NULL,
1422         NULL,
1423         NULL,
1424         NULL,
1425         NULL,
1426         NULL,
1427         NULL,
1428 };
1429
1430 /*
1431  * called prior to booting kernel or by 'fdt boardsetup' command
1432  *
1433  * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1434  *  - mtd partitions based on mtdparts/mtdids env
1435  *  - system-serial (board serial num from EEPROM)
1436  *  - board (full model from EEPROM)
1437  *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
1438  */
1439 void ft_board_setup(void *blob, bd_t *bd)
1440 {
1441         int bit;
1442         struct ventana_board_info *info = &ventana_info;
1443         struct node_info nodes[] = {
1444                 { "sst,w25q256",          MTD_DEV_TYPE_NOR, },  /* SPI flash */
1445                 { "fsl,imx6q-gpmi-nand",  MTD_DEV_TYPE_NAND, }, /* NAND flash */
1446         };
1447         const char *model = getenv("model");
1448
1449         if (getenv("fdt_noauto")) {
1450                 puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
1451                 return;
1452         }
1453
1454         /* Update partition nodes using info from mtdparts env var */
1455         puts("   Updating MTD partitions...\n");
1456         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1457
1458         if (!model) {
1459                 puts("invalid board info: Leaving FDT fully enabled\n");
1460                 return;
1461         }
1462         printf("   Adjusting FDT per EEPROM for %s...\n", model);
1463
1464         /* board serial number */
1465         fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
1466                     strlen(getenv("serial#")) + 1);
1467
1468         /* board (model contains model from device-tree) */
1469         fdt_setprop(blob, 0, "board", info->model,
1470                     strlen((const char *)info->model) + 1);
1471
1472         /*
1473          * Peripheral Config:
1474          *  remove nodes by alias path if EEPROM config tells us the
1475          *  peripheral is not loaded on the board.
1476          */
1477         for (bit = 0; bit < 64; bit++) {
1478                 if (!test_bit(bit, info->config))
1479                         fdt_del_node_and_alias(blob, fdt_aliases[bit]);
1480         }
1481 }
1482 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
1483