board/gdsys/405ep/dlvision-10g.c

   1 /*
   2  * (C) Copyright 2010
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <asm/processor.h>
  11 #include <asm/io.h>
  12 #include <asm/ppc4xx-gpio.h>
  13 #include <dtt.h>
  14
  15 #include "405ep.h"
  16 #include <gdsys_fpga.h>
  17
  18 #include "../common/osd.h"
  19
  20 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
  21 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
  22 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
  23 #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
  24
  25 #define LATCH2_MC2_PRESENT_N 0x0080
  26
  27 enum {
  28         UNITTYPE_VIDEO_USER = 0,
  29         UNITTYPE_MAIN_USER = 1,
  30         UNITTYPE_VIDEO_SERVER = 2,
  31         UNITTYPE_MAIN_SERVER = 3,
  32 };
  33
  34 enum {
  35         HWVER_101 = 0,
  36         HWVER_110 = 1,
  37         HWVER_120 = 2,
  38         HWVER_130 = 3,
  39 };
  40
  41 enum {
  42         AUDIO_NONE = 0,
  43         AUDIO_TX = 1,
  44         AUDIO_RX = 2,
  45         AUDIO_RXTX = 3,
  46 };
  47
  48 enum {
  49         SYSCLK_156250 = 2,
  50 };
  51
  52 enum {
  53         RAM_NONE = 0,
  54         RAM_DDR2_32 = 1,
  55         RAM_DDR2_64 = 2,
  56 };
  57
  58 int misc_init_r(void)
  59 {
  60         /* startup fans */
  61         dtt_init();
  62
  63         return 0;
  64 }
  65
  66 static unsigned int get_hwver(void)
  67 {
  68         u16 latch3 = in_le16((void *)LATCH3_BASE);
  69
  70         return latch3 & 0x0003;
  71 }
  72
  73 static unsigned int get_mc2_present(void)
  74 {
  75         u16 latch2 = in_le16((void *)LATCH2_BASE);
  76
  77         return !(latch2 & LATCH2_MC2_PRESENT_N);
  78 }
  79
  80 static void print_fpga_info(unsigned dev)
  81 {
  82         struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev);
  83         u16 versions = in_le16(&fpga->versions);
  84         u16 fpga_version = in_le16(&fpga->fpga_version);
  85         u16 fpga_features = in_le16(&fpga->fpga_features);
  86         unsigned unit_type;
  87         unsigned hardware_version;
  88         unsigned feature_rs232;
  89         unsigned feature_audio;
  90         unsigned feature_sysclock;
  91         unsigned feature_ramconfig;
  92         unsigned feature_carrier_speed;
  93         unsigned feature_carriers;
  94         unsigned feature_video_channels;
  95         int fpga_state = get_fpga_state(dev);
  96
  97         printf("FPGA%d: ", dev);
  98
  99         hardware_version = versions & 0x000f;
 100
 101         if (fpga_state
 102             && !((hardware_version == HWVER_101)
 103                  && (fpga_state == FPGA_STATE_DONE_FAILED))) {
 104                 puts("not available\n");
 105                 print_fpga_state(dev);
 106                 return;
 107         }
 108
 109         unit_type = (versions >> 4) & 0x000f;
 110         hardware_version = versions & 0x000f;
 111         feature_rs232 = fpga_features & (1<<11);
 112         feature_audio = (fpga_features >> 9) & 0x0003;
 113         feature_sysclock = (fpga_features >> 7) & 0x0003;
 114         feature_ramconfig = (fpga_features >> 5) & 0x0003;
 115         feature_carrier_speed = fpga_features & (1<<4);
 116         feature_carriers = (fpga_features >> 2) & 0x0003;
 117         feature_video_channels = fpga_features & 0x0003;
 118
 119         switch (unit_type) {
 120         case UNITTYPE_VIDEO_USER:
 121                 printf("Videochannel Userside");
 122                 break;
 123
 124         case UNITTYPE_MAIN_USER:
 125                 printf("Mainchannel Userside");
 126                 break;
 127
 128         case UNITTYPE_VIDEO_SERVER:
 129                 printf("Videochannel Serverside");
 130                 break;
 131
 132         case UNITTYPE_MAIN_SERVER:
 133                 printf("Mainchannel Serverside");
 134                 break;
 135
 136         default:
 137                 printf("UnitType %d(not supported)", unit_type);
 138                 break;
 139         }
 140
 141         switch (hardware_version) {
 142         case HWVER_101:
 143                 printf(" HW-Ver 1.01\n");
 144                 break;
 145
 146         case HWVER_110:
 147                 printf(" HW-Ver 1.10-1.12\n");
 148                 break;
 149
 150         case HWVER_120:
 151                 printf(" HW-Ver 1.20\n");
 152                 break;
 153
 154         case HWVER_130:
 155                 printf(" HW-Ver 1.30\n");
 156                 break;
 157
 158         default:
 159                 printf(" HW-Ver %d(not supported)\n",
 160                        hardware_version);
 161                 break;
 162         }
 163
 164         printf("       FPGA V %d.%02d, features:",
 165                 fpga_version / 100, fpga_version % 100);
 166
 167         printf(" %sRS232", feature_rs232 ? "" : "no ");
 168
 169         switch (feature_audio) {
 170         case AUDIO_NONE:
 171                 printf(", no audio");
 172                 break;
 173
 174         case AUDIO_TX:
 175                 printf(", audio tx");
 176                 break;
 177
 178         case AUDIO_RX:
 179                 printf(", audio rx");
 180                 break;
 181
 182         case AUDIO_RXTX:
 183                 printf(", audio rx+tx");
 184                 break;
 185
 186         default:
 187                 printf(", audio %d(not supported)", feature_audio);
 188                 break;
 189         }
 190
 191         switch (feature_sysclock) {
 192         case SYSCLK_156250:
 193                 printf(", clock 156.25 MHz");
 194                 break;
 195
 196         default:
 197                 printf(", clock %d(not supported)", feature_sysclock);
 198                 break;
 199         }
 200
 201         puts(",\n       ");
 202
 203         switch (feature_ramconfig) {
 204         case RAM_NONE:
 205                 printf("no RAM");
 206                 break;
 207
 208         case RAM_DDR2_32:
 209                 printf("RAM 32 bit DDR2");
 210                 break;
 211
 212         case RAM_DDR2_64:
 213                 printf("RAM 64 bit DDR2");
 214                 break;
 215
 216         default:
 217                 printf("RAM %d(not supported)", feature_ramconfig);
 218                 break;
 219         }
 220
 221         printf(", %d carrier(s) %s", feature_carriers,
 222                 feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
 223
 224         printf(", %d video channel(s)\n", feature_video_channels);
 225 }
 226
 227 /*
 228  * Check Board Identity:
 229  */
 230 int checkboard(void)
 231 {
 232         char *s = getenv("serial#");
 233
 234         puts("Board: ");
 235
 236         puts("DLVision 10G");
 237
 238         if (s != NULL) {
 239                 puts(", serial# ");
 240                 puts(s);
 241         }
 242
 243         puts("\n");
 244
 245         return 0;
 246 }
 247
 248 int last_stage_init(void)
 249 {
 250         struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
 251         u16 versions = in_le16(&fpga->versions);
 252
 253         print_fpga_info(0);
 254         if (get_mc2_present())
 255                 print_fpga_info(1);
 256
 257         if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
 258                 return 0;
 259
 260         if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
 261                 osd_probe(0);
 262
 263         if (get_mc2_present() &&
 264             (!get_fpga_state(1) || (get_hwver() == HWVER_101)))
 265                 osd_probe(1);
 266
 267         return 0;
 268 }
 269
 270 void gd405ep_init(void)
 271 {
 272 }
 273
 274 void gd405ep_set_fpga_reset(unsigned state)
 275 {
 276         if (state) {
 277                 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
 278                 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
 279         } else {
 280                 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
 281                 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
 282         }
 283 }
 284
 285 void gd405ep_setup_hw(void)
 286 {
 287         /*
 288          * set "startup-finished"-gpios
 289          */
 290         gpio_write_bit(21, 0);
 291         gpio_write_bit(22, 1);
 292 }
 293
 294 int gd405ep_get_fpga_done(unsigned fpga)
 295 {
 296         return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
 297 }