board/gdsys/405ex/405ex.c

   1 #include <common.h>
   2 #include <asm/ppc4xx.h>
   3 #include <asm/ppc405.h>
   4 #include <asm/processor.h>
   5 #include <asm/io.h>
   6
   7 #include <gdsys_fpga.h>
   8
   9 #include "405ex.h"
  10
  11 #define REFLECTION_TESTPATTERN 0xdede
  12 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
  13
  14 DECLARE_GLOBAL_DATA_PTR;
  15
  16 int get_fpga_state(unsigned dev)
  17 {
  18         return gd->arch.fpga_state[dev];
  19 }
  20
  21 void print_fpga_state(unsigned dev)
  22 {
  23         if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
  24                 puts("       Waiting for FPGA-DONE timed out.\n");
  25         if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
  26                 puts("       FPGA reflection test failed.\n");
  27 }
  28
  29 int board_early_init_f(void)
  30 {
  31         u32 val;
  32
  33         /*--------------------------------------------------------------------+
  34          | Interrupt controller setup
  35          +--------------------------------------------------------------------+
  36         +---------------------------------------------------------------------+
  37         |Interrupt| Source                            | Pol.  | Sensi.| Crit. |
  38         +---------+-----------------------------------+-------+-------+-------+
  39         | IRQ 00  | UART0                             | High  | Level | Non   |
  40         | IRQ 01  | UART1                             | High  | Level | Non   |
  41         | IRQ 02  | IIC0                              | High  | Level | Non   |
  42         | IRQ 03  | TBD                               | High  | Level | Non   |
  43         | IRQ 04  | TBD                               | High  | Level | Non   |
  44         | IRQ 05  | EBM                               | High  | Level | Non   |
  45         | IRQ 06  | BGI                               | High  | Level | Non   |
  46         | IRQ 07  | IIC1                              | Rising| Edge  | Non   |
  47         | IRQ 08  | SPI                               | High  | Lvl/ed| Non   |
  48         | IRQ 09  | External IRQ 0 - (PCI-Express)    | pgm H | Pgm   | Non   |
  49         | IRQ 10  | MAL TX EOB                        | High  | Level | Non   |
  50         | IRQ 11  | MAL RX EOB                        | High  | Level | Non   |
  51         | IRQ 12  | DMA Channel 0 FIFO Full           | High  | Level | Non   |
  52         | IRQ 13  | DMA Channel 0 Stat FIFO           | High  | Level | Non   |
  53         | IRQ 14  | DMA Channel 1 FIFO Full           | High  | Level | Non   |
  54         | IRQ 15  | DMA Channel 1 Stat FIFO           | High  | Level | Non   |
  55         | IRQ 16  | PCIE0 AL                          | high  | Level | Non   |
  56         | IRQ 17  | PCIE0 VPD access                  | rising| Edge  | Non   |
  57         | IRQ 18  | PCIE0 hot reset request           | rising| Edge  | Non   |
  58         | IRQ 19  | PCIE0 hot reset request           | faling| Edge  | Non   |
  59         | IRQ 20  | PCIE0 TCR                         | High  | Level | Non   |
  60         | IRQ 21  | PCIE0 MSI level0                  | High  | Level | Non   |
  61         | IRQ 22  | PCIE0 MSI level1                  | High  | Level | Non   |
  62         | IRQ 23  | Security EIP-94                   | High  | Level | Non   |
  63         | IRQ 24  | EMAC0 interrupt                   | High  | Level | Non   |
  64         | IRQ 25  | EMAC1 interrupt                   | High  | Level | Non   |
  65         | IRQ 26  | PCIE0 MSI level2                  | High  | Level | Non   |
  66         | IRQ 27  | External IRQ 4                    | pgm H | Pgm   | Non   |
  67         | IRQ 28  | UIC2 Non-critical Int.            | High  | Level | Non   |
  68         | IRQ 29  | UIC2 Critical Interrupt           | High  | Level | Crit. |
  69         | IRQ 30  | UIC1 Non-critical Int.            | High  | Level | Non   |
  70         | IRQ 31  | UIC1 Critical Interrupt           | High  | Level | Crit. |
  71         |----------------------------------------------------------------------
  72         | IRQ 32  | MAL Serr                          | High  | Level | Non   |
  73         | IRQ 33  | MAL Txde                          | High  | Level | Non   |
  74         | IRQ 34  | MAL Rxde                          | High  | Level | Non   |
  75         | IRQ 35  | PCIE0 bus master VC0              |falling| Edge  | Non   |
  76         | IRQ 36  | PCIE0 DCR Error                   | High  | Level | Non   |
  77         | IRQ 37  | EBC                               | High  |Lvl Edg| Non   |
  78         | IRQ 38  | NDFC                              | High  | Level | Non   |
  79         | IRQ 39  | GPT Compare Timer 8               | Risin | Edge  | Non   |
  80         | IRQ 40  | GPT Compare Timer 9               | Risin | Edge  | Non   |
  81         | IRQ 41  | PCIE1 AL                          | high  | Level | Non   |
  82         | IRQ 42  | PCIE1 VPD access                  | rising| edge  | Non   |
  83         | IRQ 43  | PCIE1 hot reset request           | rising| Edge  | Non   |
  84         | IRQ 44  | PCIE1 hot reset request           | faling| Edge  | Non   |
  85         | IRQ 45  | PCIE1 TCR                         | High  | Level | Non   |
  86         | IRQ 46  | PCIE1 bus master VC0              |falling| Edge  | Non   |
  87         | IRQ 47  | GPT Compare Timer 3               | Risin | Edge  | Non   |
  88         | IRQ 48  | GPT Compare Timer 4               | Risin | Edge  | Non   |
  89         | IRQ 49  | Ext. IRQ 7                        |pgm/Fal|pgm/Lvl| Non   |
  90         | IRQ 50  | Ext. IRQ 8 -                      |pgm (H)|pgm/Lvl| Non   |
  91         | IRQ 51  | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non   |
  92         | IRQ 52  | GPT Compare Timer 5               | high  | Edge  | Non   |
  93         | IRQ 53  | GPT Compare Timer 6               | high  | Edge  | Non   |
  94         | IRQ 54  | GPT Compare Timer 7               | high  | Edge  | Non   |
  95         | IRQ 55  | Serial ROM                        | High  | Level | Non   |
  96         | IRQ 56  | GPT Decrement Pulse               | High  | Level | Non   |
  97         | IRQ 57  | Ext. IRQ 2                        |pgm/Fal|pgm/Lvl| Non   |
  98         | IRQ 58  | Ext. IRQ 5                        |pgm/Fal|pgm/Lvl| Non   |
  99         | IRQ 59  | Ext. IRQ 6                        |pgm/Fal|pgm/Lvl| Non   |
 100         | IRQ 60  | EMAC0 Wake-up                     | High  | Level | Non   |
 101         | IRQ 61  | Ext. IRQ 1                        |pgm/Fal|pgm/Lvl| Non   |
 102         | IRQ 62  | EMAC1 Wake-up                     | High  | Level | Non   |
 103         |----------------------------------------------------------------------
 104         | IRQ 64  | PE0 AL                            | High  | Level | Non   |
 105         | IRQ 65  | PE0 VPD Access                    | Risin | Edge  | Non   |
 106         | IRQ 66  | PE0 Hot Reset Request             | Risin | Edge  | Non   |
 107         | IRQ 67  | PE0 Hot Reset Request             | Falli | Edge  | Non   |
 108         | IRQ 68  | PE0 TCR                           | High  | Level | Non   |
 109         | IRQ 69  | PE0 BusMaster VCO                 | Falli | Edge  | Non   |
 110         | IRQ 70  | PE0 DCR Error                     | High  | Level | Non   |
 111         | IRQ 71  | Reserved                          | N/A   | N/A   | Non   |
 112         | IRQ 72  | PE1 AL                            | High  | Level | Non   |
 113         | IRQ 73  | PE1 VPD Access                    | Risin | Edge  | Non   |
 114         | IRQ 74  | PE1 Hot Reset Request             | Risin | Edge  | Non   |
 115         | IRQ 75  | PE1 Hot Reset Request             | Falli | Edge  | Non   |
 116         | IRQ 76  | PE1 TCR                           | High  | Level | Non   |
 117         | IRQ 77  | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
 118         | IRQ 78  | PE1 DCR Error                     | High  | Level | Non   |
 119         | IRQ 79  | Reserved                          | N/A   | N/A   | Non   |
 120         | IRQ 80  | PE2 AL                            | High  | Level | Non   |
 121         | IRQ 81  | PE2 VPD Access                    | Risin | Edge  | Non   |
 122         | IRQ 82  | PE2 Hot Reset Request             | Risin | Edge  | Non   |
 123         | IRQ 83  | PE2 Hot Reset Request             | Falli | Edge  | Non   |
 124         | IRQ 84  | PE2 TCR                           | High  | Level | Non   |
 125         | IRQ 85  | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
 126         | IRQ 86  | PE2 DCR Error                     | High  | Level | Non   |
 127         | IRQ 87  | Reserved                          | N/A   | N/A   | Non   |
 128         | IRQ 88  | External IRQ(5)                   | Progr | Progr | Non   |
 129         | IRQ 89  | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
 130         | IRQ 90  | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
 131         | IRQ 91  | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
 132         | IRQ 92  | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
 133         | IRQ 93  | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
 134         | IRQ 94  | Reserved                          | N/A   | N/A   | Non   |
 135         | IRQ 95  | Reserved                          | N/A   | N/A   | Non   |
 136         |---------------------------------------------------------------------
 137         +---------+-----------------------------------+-------+-------+------*/
 138         /*--------------------------------------------------------------------+
 139          | Initialise UIC registers.  Clear all interrupts.  Disable all
 140          | interrupts.
 141          | Set critical interrupt values.  Set interrupt polarities.  Set
 142          | interrupt trigger levels.  Make bit 0 High  priority.  Clear all
 143          | interrupts again.
 144          +-------------------------------------------------------------------*/
 145
 146         mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */
 147         mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */
 148         mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
 149         mtdcr(UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
 150         mtdcr(UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
 151         mtdcr(UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
 152         mtdcr(UIC2SR, 0x00000000); /* clear all interrupts */
 153         mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */
 154
 155         mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */
 156         mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */
 157         mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
 158         mtdcr(UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
 159         mtdcr(UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
 160         mtdcr(UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
 161         mtdcr(UIC1SR, 0x00000000); /* clear all interrupts */
 162         mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */
 163
 164         mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */
 165         mtdcr(UIC0ER, 0x0000000a); /* Disable all interrupts */
 166                                    /* Except cascade UIC0 and UIC1 */
 167         mtdcr(UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
 168         mtdcr(UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
 169         mtdcr(UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
 170         mtdcr(UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
 171         mtdcr(UIC0SR, 0x00000000); /* clear all interrupts */
 172         mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */
 173
 174         /*
 175          * Note: Some cores are still in reset when the chip starts, so
 176          * take them out of reset
 177          */
 178         mtsdr(SDR0_SRST, 0);
 179
 180         /*
 181          * Configure PFC (Pin Function Control) registers
 182          */
 183         val = SDR0_PFC1_GPT_FREQ;
 184         mtsdr(SDR0_PFC1, val);
 185
 186         return 0;
 187 }
 188
 189 int board_early_init_r(void)
 190 {
 191         unsigned k;
 192         unsigned ctr;
 193
 194         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
 195                 gd->arch.fpga_state[k] = 0;
 196
 197         /*
 198          * reset FPGA
 199          */
 200         gd405ex_init();
 201
 202         gd405ex_set_fpga_reset(1);
 203
 204         gd405ex_setup_hw();
 205
 206         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
 207                 ctr = 0;
 208                 while (!gd405ex_get_fpga_done(k)) {
 209                         udelay(100000);
 210                         if (ctr++ > 5) {
 211                                 gd->arch.fpga_state[k] |=
 212                                         FPGA_STATE_DONE_FAILED;
 213                                 break;
 214                         }
 215                 }
 216         }
 217
 218         udelay(10);
 219
 220         gd405ex_set_fpga_reset(0);
 221
 222         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
 223                 struct ihs_fpga *fpga =
 224                         (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k);
 225 #ifdef CONFIG_SYS_FPGA_NO_RFL_HI
 226                 u16 *reflection_target = &fpga->reflection_low;
 227 #else
 228                 u16 *reflection_target = &fpga->reflection_high;
 229 #endif
 230                 /*
 231                  * wait for fpga out of reset
 232                  */
 233                 ctr = 0;
 234                 while (1) {
 235                         out_le16(&fpga->reflection_low,
 236                                 REFLECTION_TESTPATTERN);
 237
 238                         if (in_le16(reflection_target) ==
 239                                 REFLECTION_TESTPATTERN_INV)
 240                                 break;
 241
 242                         udelay(100000);
 243                         if (ctr++ > 5) {
 244                                 gd->arch.fpga_state[k] |=
 245                                         FPGA_STATE_REFLECTION_FAILED;
 246                                 break;
 247                         }
 248                 }
 249         }
 250
 251         return 0;
 252 }