board/icpdas/lp8x4x/lp8x4x.c

   1 /*
   2  * ICP DAS LP-8x4x Support
   3  *
   4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   5  * adapted from Voipac PXA270 Support by
   6  * Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <asm/arch/hardware.h>
  13 #include <asm/arch/regs-mmc.h>
  14 #include <asm/arch/pxa.h>
  15 #include <netdev.h>
  16 #include <serial.h>
  17 #include <asm/io.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 /*
  22  * Miscelaneous platform dependent initialisations
  23  */
  24 int board_init(void)
  25 {
  26         /* We have RAM, disable cache */
  27         dcache_disable();
  28         icache_disable();
  29
  30         /* memory and cpu-speed are setup before relocation */
  31         /* so we do _nothing_ here */
  32
  33         /* adress of boot parameters */
  34         gd->bd->bi_boot_params = 0xa0000100;
  35
  36         return 0;
  37 }
  38
  39 int dram_init(void)
  40 {
  41         pxa2xx_dram_init();
  42         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  43         return 0;
  44 }
  45
  46 void dram_init_banksize(void)
  47 {
  48         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  49         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  50 }
  51
  52 #ifdef  CONFIG_CMD_MMC
  53 int board_mmc_init(bd_t *bis)
  54 {
  55         pxa_mmc_register(0);
  56         return 0;
  57 }
  58 #endif
  59
  60 #ifdef  CONFIG_CMD_USB
  61 int usb_board_init(void)
  62 {
  63         writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
  64                 ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
  65                 UHCHR);
  66
  67         writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
  68
  69         while (readl(UHCHR) & UHCHR_FSBIR)
  70                 continue; /* required by checkpath.pl */
  71
  72         writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
  73         writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
  74
  75         /* Clear any OTG Pin Hold */
  76         if (readl(PSSR) & PSSR_OTGPH)
  77                 writel(readl(PSSR) | PSSR_OTGPH, PSSR);
  78
  79         writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
  80         writel(readl(UHCRHDA) | 0x100, UHCRHDA);
  81
  82         /* Set port power control mask bits, only 3 ports. */
  83         writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
  84
  85         /* enable port 2 */
  86         writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
  87                 UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
  88
  89         return 0;
  90 }
  91
  92 void usb_board_init_fail(void)
  93 {
  94         return;
  95 }
  96
  97 void usb_board_stop(void)
  98 {
  99         writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
 100         udelay(11);
 101         writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
 102
 103         writel(readl(UHCCOMS) | 1, UHCCOMS);
 104         udelay(10);
 105
 106         writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
 107
 108         return;
 109 }
 110 #endif
 111
 112 #ifdef CONFIG_DRIVER_DM9000
 113 void lp8x4x_eth1_mac_init(void)
 114 {
 115         u8 eth1addr[8];
 116         int i;
 117         u8 reg;
 118
 119         eth_getenv_enetaddr_by_index("eth", 1, eth1addr);
 120         if (!is_valid_ether_addr(eth1addr))
 121                 return;
 122
 123         for (i = 0, reg = 0x10; i < 6; i++, reg++) {
 124                 writeb(reg, (u8 *)(DM9000_IO_2));
 125                 writeb(eth1addr[i], (u8 *)(DM9000_DATA_2));
 126         }
 127 }
 128
 129 int board_eth_init(bd_t *bis)
 130 {
 131         lp8x4x_eth1_mac_init();
 132         return dm9000_initialize(bis);
 133 }
 134 #endif