2 #include <asm-offsets.h>
3 #include <configs/tx53.h>
4 #include <linux/linkage.h>
5 #include <asm/arch/imx-regs.h>
7 #define DEBUG_LED_BIT 20
8 #define LED_GPIO_BASE GPIO2_BASE_ADDR
9 #define LED_MUX_OFFSET 0x174
10 #define LED_MUX_MODE 0x11
12 #define SDRAM_CLK CONFIG_SYS_SDRAM_CLK
13 #define SDRAM_SIZE (CONFIG_SYS_SDRAM_SIZE / SZ_1M)
15 #define REG_CCGR0 0x68
16 #define REG_CCGR1 0x6c
17 #define REG_CCGR2 0x70
18 #define REG_CCGR3 0x74
19 #define REG_CCGR4 0x78
20 #define REG_CCGR5 0x7c
21 #define REG_CCGR6 0x80
22 #define REG_CCGR7 0x84
23 #define REG_CMEOR 0x88
25 #define CPU_2_BE_32(l) \
26 ((((l) << 24) & 0xFF000000) | \
27 (((l) << 8) & 0x00FF0000) | \
28 (((l) >> 8) & 0x0000FF00) | \
29 (((l) >> 24) & 0x000000FF))
32 CCM register set 0x53FD4000 0x53FD7FFF
33 EIM register set 0x63FDA000 0x63FDAFFF
34 NANDFC register set 0xF7FF0000 0xF7FFFFFF
35 IOMUX Control (IOMUXC) registers 0x53FA8000 0x53FABFFF
36 DPLLC1 register 0x63F80000 0x63F83FFF
37 DPLLC2 register 0x63F84000 0x63F87FFF
38 DPLLC3 register 0x63F88000 0x63F8BFFF
39 DPLLC4 register 0x63F8C000 0x63F8FFFF
40 ESD RAM controller register 0x63FD9000 0x63FD9FFF
41 M4IF register 0x63FD8000 0x63FD8FFF
42 DDR 0x70000000 0xEFFFFFFF
43 EIM 0xF0000000 0xF7FEFFFF
44 NANDFC Buffers 0xF7FF0000 0xF7FFFFFF
45 IRAM Free Space 0xF8006000 0xF8017FF0
46 GPU Memory 0xF8020000 0xF805FFFF
48 #define CHECK_DCD_ADDR(a) ( \
49 ((a) >= 0x53fd4000 && (a) <= 0x53fd7fff) /* CCM */ || \
50 ((a) >= 0x63fda000 && (a) <= 0x63fdafff) /* EIM (CS0) */ || \
51 ((a) >= 0x53fa8000 && (a) <= 0x53fabfff) /* IOMUXC */ || \
52 ((a) >= 0x63f80000 && (a) <= 0x63f8ffff) /* DPLLC1..4 */ || \
53 ((a) >= 0x63fd8000 && (a) <= 0x63fd9fff) /* M4IF & SDRAM Contr. */ || \
54 ((a) >= 0x70000000 && (a) <= 0xefffffff) /* SDRAM */ || \
55 ((a) >= 0xf0000000 && (a) <= 0xf7ffffff) /* EIM & NANDFC buffers */ || \
56 ((a) >= 0xf8006000 && (a) <= 0xf8017ff0) /* IRAM free space */ || \
57 ((a) >= 0xf8020000 && (a) <= 0xf805ffff) /* GPU RAM */)
59 .macro mxc_dcd_item addr, val
60 .ifne CHECK_DCD_ADDR(\addr)
61 .word CPU_2_BE_32(\addr), CPU_2_BE_32(\val)
63 .error "Address \addr not accessible from DCD"
67 #define MXC_DCD_ITEM(addr, val) mxc_dcd_item (addr), (val)
69 #define MXC_DCD_CMD_SZ_BYTE 1
70 #define MXC_DCD_CMD_SZ_SHORT 2
71 #define MXC_DCD_CMD_SZ_WORD 4
72 #define MXC_DCD_CMD_FLAG_WRITE 0x0
73 #define MXC_DCD_CMD_FLAG_CLR 0x1
74 #define MXC_DCD_CMD_FLAG_SET 0x3
75 #define MXC_DCD_CMD_FLAG_CHK_CLR ((0 << 0) | (0 << 1))
76 #define MXC_DCD_CMD_FLAG_CHK_SET ((0 << 0) | (1 << 1))
77 #define MXC_DCD_CMD_FLAG_CHK_ANY_CLR ((1 << 0) | (0 << 1))
78 #define MXC_DCD_CMD_FLAG_CHK_ANY_SET ((1 << 0) | (1 << 1))
80 #define MXC_DCD_START \
81 .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) ; \
86 .ifgt . - dcd_start - 1768
87 .error "DCD too large!"
94 #define MXC_DCD_CMD_WRT(type, flags) \
95 1: .word CPU_2_BE_32((0xcc << 24) | ((1f - .) << 8) | ((flags) << 3) | (type))
97 #define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
98 1: .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)), \
99 CPU_2_BE_32(addr), CPU_2_BE_32(mask)
101 #define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
102 1: .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)), \
103 CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
105 #define MXC_DCD_CMD_NOP() \
106 1: .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
109 #define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
110 #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
111 #define NS_TO_CK10(ns) DIV_ROUND_UP(NS_TO_CK(ns), 10)
112 #define NS_TO_CK100(ns) DIV_ROUND_UP(NS_TO_CK(ns), 100)
114 .macro CK_VAL, name, clks, offs, max
118 .ifle \clks - \offs - \max
119 .set \name, \clks - \offs
121 .error "Value \clks out of range for parameter \name"
126 .macro NS_VAL, name, ns, offs, max
130 CK_VAL \name, NS_TO_CK(\ns), \offs, \max
134 .macro CK_MAX, name, ck1, ck2, offs, max
136 CK_VAL \name, \ck1, \offs, \max
138 CK_VAL \name, \ck2, \offs, \max
142 #define ESDMISC_DDR_TYPE_DDR3 0
143 #define ESDMISC_DDR_TYPE_LPDDR2 1
144 #define ESDMISC_DDR_TYPE_DDR2 2
146 #define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d))
148 #define CKIL_FREQ_Hz 32768
149 #define ESDOR_CLK_PERIOD_ns (1000000000 / CKIL_FREQ_Hz / 2) /* base clock for ESDOR values */
152 #define BANK_ADDR_BITS CONFIG_NR_DRAM_BANKS
153 #define SDRAM_BURST_LENGTH 8
157 #define ADDR_MIRROR 0
158 #define DDR_TYPE ESDMISC_DDR_TYPE_DDR3
160 #if SDRAM_CLK > 666 && SDRAM_CLK <= 800
163 #elif SDRAM_CLK > 533 && SDRAM_CLK <= 666
164 #define CL_VAL 9 // or 10
166 #elif SDRAM_CLK > 400 && SDRAM_CLK <= 533
167 #define CL_VAL 7 // or 8
169 #elif SDRAM_CLK > 333 && SDRAM_CLK <= 400
172 #elif SDRAM_CLK >= 303 && SDRAM_CLK <= 333
176 #error SDRAM clock out of range: 303 .. 800
179 #if SDRAM_SIZE < 2048
180 /* 512/1024MiB SDRAM: NT5CB128M16FP-DII */
182 #define ROW_ADDR_BITS 14
183 #define COL_ADDR_BITS 10
186 NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
187 CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
188 CK_MAX tXP, NS_TO_CK10(75), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */
189 CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
190 NS_VAL tFAW, 50, 1, 31 /* clks - 1 (0..31) */
191 CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */
194 CK_VAL tRCD, NS_TO_CK10(125), 1, 7 /* clks - 1 (0..7) */ /* 12.5 */
195 CK_VAL tRP, NS_TO_CK10(125), 1, 7 /* clks - 1 (0..7) */ /* 12.5 */
196 NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */
197 CK_VAL tRAS, NS_TO_CK10(375), 1, 31 /* clks - 1 (0..31) */ /* 37.5 */
198 CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */
199 NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
200 CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
201 CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */
204 CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
205 CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
206 CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
207 CK_MAX tRRD, NS_TO_CK(10), 4, 1, 7 /* clks - 1 (0..7) */
210 CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
212 /* 4096MiB SDRAM: IM4G16D3EABG-125I */
214 #define ROW_ADDR_BITS 15
215 #define COL_ADDR_BITS 10
218 NS_VAL tRFC, 260, 1, 255 /* clks - 1 (0..255) */
219 CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
220 CK_MAX tXP, NS_TO_CK(6), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */
221 CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
222 NS_VAL tFAW, 30, 1, 31 /* clks - 1 (0..31) */
223 CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */
226 CK_VAL tRCD, NS_TO_CK100(1375), 1, 7 /* clks - 1 (0..7) */ /* 13.75 */
227 CK_VAL tRP, NS_TO_CK100(1375), 1, 7 /* clks - 1 (0..7) */ /* 13.75 */
228 CK_VAL tRC, NS_TO_CK100(4875), 1, 31 /* clks - 1 (0..31) */ /* 48.75 */
229 CK_VAL tRAS, NS_TO_CK(35), 1, 31 /* clks - 1 (0..31) */ /* 35 */
230 CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */
231 NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
232 CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
233 CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */
236 CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
237 CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
238 CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
239 CK_MAX tRRD, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
242 CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
245 #define tSDE_RST (DIV_ROUND_UP(200000, ESDOR_CLK_PERIOD_ns) + 1)
246 /* Add an extra (or two?) ESDOR_CLK_PERIOD_ns according to
247 * erroneous Erratum Engcm12377
249 #define tRST_CKE (DIV_ROUND_UP(500000 + 2 * ESDOR_CLK_PERIOD_ns, ESDOR_CLK_PERIOD_ns) + 1)
252 CK_VAL tAOFPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */
253 CK_VAL tAONPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */
254 CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
255 CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
256 CK_VAL tODTLon tCWL, 0, 7 /* clks - 1 (0..7) */ /* CWL+AL-2 */
257 CK_VAL tODTLoff tCWL, 0, 31 /* clks - 1 (0..31) */ /* CWL+AL-2 */
260 CK_MAX tCKE, NS_TO_CK(5), 3, 1, 7
261 CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7
262 CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7
269 #define ESDPDC_VAL_0 ( \
274 (BOTH_CS_PD << 6) | \
279 #define ESDPDC_VAL_1 (ESDPDC_VAL_0 | \
284 #define Rtt_Nom 1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */
285 #define Rtt_WR 0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */
286 #define DLL_DISABLE 0
289 .set mr0_val, (((1 - DLL_DISABLE) << 8) /* DLL Reset */ | \
290 (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
291 ((tWR + 1 - 4) << 9) | \
292 ((((tCL + 3) - 4) & 0x7) << 4) | \
293 ((((tCL + 3) - 4) & 0x8) >> 1))
295 .set mr0_val, ((1 << 8) /* DLL Reset */ | \
296 (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
297 (((tWR + 1) / 2) << 9) | \
298 ((((tCL + 3) - 4) & 0x7) << 4) | \
299 ((((tCL + 3) - 4) & 0x8) >> 1))
303 ((Rtt_Nom & 1) << 2) | \
304 (((Rtt_Nom >> 1) & 1) << 6) | \
305 (((Rtt_Nom >> 2) & 1) << 9) | \
306 (DLL_DISABLE << 0) | \
309 (Rtt_WR << 9) /* dynamic ODT */ | \
310 (0 << 7) /* SRT: Ext. temp. (mutually exclusive with ASR!) */ | \
311 (1 << 6) | /* ASR: Automatic Self Refresh */ \
312 (((tCWL + 2) - 5) << 3) | \
316 #define ESDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \
317 (1 << 15) /* CON_REQ */ | \
319 (3 << 4) /* MRS command */ | \
324 #define ESDCFG0_VAL ( \
332 #define ESDCFG1_VAL ( \
342 #define ESDCFG2_VAL ( \
348 #define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
350 #define ESDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
351 ((COL_ADDR_BITS - 9) << 20) | \
352 (BURST_LEN << 19) | \
353 (1 << 16) | /* SDRAM bus width */ \
354 ((-1) << (32 - BANK_ADDR_BITS)))
356 #define ESDMISC_VAL ((ADDR_MIRROR << 19) | \
363 #define ESDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
365 #define ESDOTC_VAL ((tAOFPD << 27) | \
374 .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
385 #ifdef CONFIG_SECURE_BOOT
392 .long CONFIG_SYS_TEXT_BASE
394 .long __uboot_img_len
398 #define DCD_VERSION 0x40
402 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
404 MXC_DCD_ITEM(0x53fa8004, 0x00194005) @ set LDO to 1.3V
406 /* disable all irrelevant clocks */
407 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR0, 0xffcf0fff)
408 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR1, 0x000fffcf)
409 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR2, 0x033c0000)
410 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR3, 0x000000ff)
411 #ifdef CONFIG_SECURE_BOOT
413 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR4, 0x0000c000)
415 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR4, 0x00000000)
417 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR5, 0x00fff033)
418 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR6, 0x0f00030f)
419 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR7, 0xfff00000)
420 MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CMEOR, 0x00000000)
422 MXC_DCD_ITEM(IOMUXC_BASE_ADDR + 0x340, 0x11) /* GPIO_17 => RESET_OUT */
424 MXC_DCD_ITEM(0x63fd800c, 0x00000000) /* M4IF: MUX NFC signals on WEIM */
426 MXC_DCD_ITEM(0x53fd4014, 0x00888944) /* CBCDR */
428 MXC_DCD_ITEM(0x53fd4014, 0x00888644) /* CBCDR */
430 MXC_DCD_ITEM(0x53fd4018, 0x00016154) /* CBCMR */
432 MXC_DCD_ITEM(0x53fd401c, 0xa6a2a020) /* CSCMR1 */
433 MXC_DCD_ITEM(0x53fd4020, 0xb6b12f0a) /* CSCMR2 */
434 MXC_DCD_ITEM(0x53fd4024, 0x00080b18) /* CSCDR1 */
436 #define DDR_SEL_VAL 0
440 #define DDR_SEL_SHIFT 25
443 #define DDR_INPUT_SHIFT 9
449 #define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT)
450 #define DSE_MASK (DSE_VAL << DSE_SHIFT)
451 #define ODT_MASK (ODT_VAL << ODT_SHIFT)
453 #define DQM_VAL DSE_MASK
454 #define SDQS_VAL (ODT_MASK | DSE_MASK | (1 << PUE_SHIFT))
455 #define SDODT_VAL (DSE_MASK | (0 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
456 #define SDCLK_VAL DSE_MASK
457 #define SDCKE_VAL ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
459 MXC_DCD_ITEM(0x53fa8724, DDR_SEL_MASK) /* DDR_TYPE: DDR3 */
460 MXC_DCD_ITEM(0x53fa86f4, 0 << DDR_INPUT_SHIFT) /* DDRMODE_CTL */
461 MXC_DCD_ITEM(0x53fa8714, 0 << DDR_INPUT_SHIFT) /* GRP_DDRMODE */
462 MXC_DCD_ITEM(0x53fa86fc, 1 << PKE_SHIFT) /* GRP_DDRPKE */
463 MXC_DCD_ITEM(0x53fa8710, 0 << HYS_SHIFT) /* GRP_DDRHYS */
464 MXC_DCD_ITEM(0x53fa8708, 1 << PUE_SHIFT) /* GRP_DDRPK */
466 MXC_DCD_ITEM(0x53fa8584, DQM_VAL) /* DQM0 */
467 MXC_DCD_ITEM(0x53fa8594, DQM_VAL) /* DQM1 */
468 MXC_DCD_ITEM(0x53fa8560, DQM_VAL) /* DQM2 */
469 MXC_DCD_ITEM(0x53fa8554, DQM_VAL) /* DQM3 */
471 MXC_DCD_ITEM(0x53fa857c, SDQS_VAL) /* SDQS0 */
472 MXC_DCD_ITEM(0x53fa8590, SDQS_VAL) /* SDQS1 */
473 MXC_DCD_ITEM(0x53fa8568, SDQS_VAL) /* SDQS2 */
474 MXC_DCD_ITEM(0x53fa8558, SDQS_VAL) /* SDQS3 */
476 MXC_DCD_ITEM(0x53fa8580, SDODT_VAL) /* SDODT0 */
477 MXC_DCD_ITEM(0x53fa8578, SDCLK_VAL) /* SDCLK0 */
479 MXC_DCD_ITEM(0x53fa8564, SDODT_VAL) /* SDODT1 */
480 MXC_DCD_ITEM(0x53fa8570, SDCLK_VAL) /* SDCLK1 */
482 MXC_DCD_ITEM(0x53fa858c, SDCKE_VAL) /* SDCKE0 */
483 MXC_DCD_ITEM(0x53fa855c, SDCKE_VAL) /* SDCKE1 */
485 MXC_DCD_ITEM(0x53fa8574, DSE_MASK) /* DRAM_CAS */
486 MXC_DCD_ITEM(0x53fa8588, DSE_MASK) /* DRAM_RAS */
488 MXC_DCD_ITEM(0x53fa86f0, DSE_MASK) /* GRP_ADDDS */
489 MXC_DCD_ITEM(0x53fa8720, DSE_MASK) /* GRP_CTLDS */
490 MXC_DCD_ITEM(0x53fa8718, DSE_MASK) /* GRP_B0DS */
491 MXC_DCD_ITEM(0x53fa871c, DSE_MASK) /* GRP_B1DS */
492 MXC_DCD_ITEM(0x53fa8728, DSE_MASK) /* GRP_B2DS */
493 MXC_DCD_ITEM(0x53fa872c, DSE_MASK) /* GRP_B3DS */
495 /* calibration defaults */
496 MXC_DCD_ITEM(0x63fd904c, 0x001f001f)
497 MXC_DCD_ITEM(0x63fd9050, 0x001f001f)
498 MXC_DCD_ITEM(0x63fd907c, 0x011e011e)
499 MXC_DCD_ITEM(0x63fd9080, 0x011f0120)
500 MXC_DCD_ITEM(0x63fd9088, 0x3a393d3b)
501 MXC_DCD_ITEM(0x63fd9090, 0x3f3f3f3f)
503 MXC_DCD_ITEM(0x63fd9018, ESDMISC_VAL)
504 MXC_DCD_ITEM(0x63fd9000, ESDCTL_VAL)
505 MXC_DCD_ITEM(0x63fd900c, ESDCFG0_VAL)
506 MXC_DCD_ITEM(0x63fd9010, ESDCFG1_VAL)
507 MXC_DCD_ITEM(0x63fd9014, ESDCFG2_VAL)
509 MXC_DCD_ITEM(0x63fd902c, 0x000026d2)
510 MXC_DCD_ITEM(0x63fd9030, ESDOR_VAL)
511 MXC_DCD_ITEM(0x63fd9008, ESDOTC_VAL)
512 MXC_DCD_ITEM(0x63fd9004, ESDPDC_VAL_0)
515 MXC_DCD_ITEM(0x63fd901c, 0x00008000) /* CON_REQ */
516 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x63fd901c, 0x00004000)
517 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
519 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 2, mr2_val)) /* MRS: MR2 */
520 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, mr3_val)) /* MRS: MR3 */
521 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: MR1 */
522 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 0, mr0_val)) /* MRS: MR0 */
523 #if BANK_ADDR_BITS > 1
525 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 2, 0x0000)) /* MRS: MR2 */
526 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 3, 0x0000)) /* MRS: MR3 */
527 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 1, 0x0040)) /* MRS: MR1 */
528 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 0, mr0_val)) /* MRS: MR0 */
530 MXC_DCD_ITEM(0x63fd9020, 3 << 14) /* disable refresh during calibration */
531 MXC_DCD_ITEM(0x63fd9058, 0x00022222)
533 MXC_DCD_ITEM(0x63fd90d0, 0x00000003) /* select default compare pattern for calibration */
536 MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
537 MXC_DCD_ITEM(0x63fd901c, 0x00008040) /* MRS: ZQ calibration */
538 MXC_DCD_ITEM(0x63fd9040, 0x0539002b) /* Force ZQ calibration */
539 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd9040, 0x00010000)
540 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
542 /* DQS calibration */
543 MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
544 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */
545 MXC_DCD_ITEM(0x63fd907c, 0x90000000) /* reset RD fifo and start DQS calib. */
547 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd907c, 0x90000000)
548 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
549 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
551 /* WR DL calibration */
552 MXC_DCD_ITEM(0x63fd901c, 0x00008000)
553 MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
554 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */
555 MXC_DCD_ITEM(0x63fd90a4, 0x00000010)
557 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd90a4, 0x00000010)
558 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
559 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
561 /* RD DL calibration */
562 MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
563 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */
564 MXC_DCD_ITEM(0x63fd90a0, 0x00000010)
566 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd90a0, 0x00000010)
567 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
568 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
569 MXC_DCD_ITEM(0x63fd9020, (3 << 11) | (0 << 14)) /* refresh interval: 4 cycles every 64kHz period */
570 MXC_DCD_ITEM(0x63fd9004, ESDPDC_VAL_1)
572 /* DDR calibration done */
573 MXC_DCD_ITEM(0x63fd901c, 0x00000000)
577 MXC_DCD_ITEM(0x53fa819c, 0x00000000) @ EIM_DA0
578 MXC_DCD_ITEM(0x53fa81a0, 0x00000000) @ EIM_DA1
579 MXC_DCD_ITEM(0x53fa81a4, 0x00000000) @ EIM_DA2
580 MXC_DCD_ITEM(0x53fa81a8, 0x00000000) @ EIM_DA3
581 MXC_DCD_ITEM(0x53fa81ac, 0x00000000) @ EIM_DA4
582 MXC_DCD_ITEM(0x53fa81b0, 0x00000000) @ EIM_DA5
583 MXC_DCD_ITEM(0x53fa81b4, 0x00000000) @ EIM_DA6
584 MXC_DCD_ITEM(0x53fa81b8, 0x00000000) @ EIM_DA7
585 MXC_DCD_ITEM(0x53fa81dc, 0x00000000) @ WE_B
586 MXC_DCD_ITEM(0x53fa81e0, 0x00000000) @ RE_B
587 MXC_DCD_ITEM(0x53fa8228, 0x00000000) @ CLE
588 MXC_DCD_ITEM(0x53fa822c, 0x00000000) @ ALE
589 MXC_DCD_ITEM(0x53fa8230, 0x00000000) @ WP_B
590 MXC_DCD_ITEM(0x53fa8234, 0x00000000) @ RB0
591 MXC_DCD_ITEM(0x53fa8238, 0x00000000) @ CS0
593 MXC_DCD_ITEM(0x53fa84ec, 0x000000e4) @ EIM_DA0
594 MXC_DCD_ITEM(0x53fa84f0, 0x000000e4) @ EIM_DA1
595 MXC_DCD_ITEM(0x53fa84f4, 0x000000e4) @ EIM_DA2
596 MXC_DCD_ITEM(0x53fa84f8, 0x000000e4) @ EIM_DA3
597 MXC_DCD_ITEM(0x53fa84fc, 0x000000e4) @ EIM_DA4
598 MXC_DCD_ITEM(0x53fa8500, 0x000000e4) @ EIM_DA5
599 MXC_DCD_ITEM(0x53fa8504, 0x000000e4) @ EIM_DA6
600 MXC_DCD_ITEM(0x53fa8508, 0x000000e4) @ EIM_DA7
601 MXC_DCD_ITEM(0x53fa852c, 0x00000004) @ NANDF_WE_B
602 MXC_DCD_ITEM(0x53fa8530, 0x00000004) @ NANDF_RE_B
603 MXC_DCD_ITEM(0x53fa85a0, 0x00000004) @ NANDF_CLE_B
604 MXC_DCD_ITEM(0x53fa85a4, 0x00000004) @ NANDF_ALE_B
605 MXC_DCD_ITEM(0x53fa85a8, 0x000000e4) @ NANDF_WE_B
606 MXC_DCD_ITEM(0x53fa85ac, 0x000000e4) @ NANDF_RB0
607 MXC_DCD_ITEM(0x53fa85b0, 0x00000004) @ NANDF_CS0