board/karo/tx6dl/tx6dl.c

   1 /*
   2  * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22 #ifndef DEBUG
  23 #define DEBUG
  24 #endif
  25 //#define TIMER_TEST
  26
  27 #include <common.h>
  28 #include <errno.h>
  29 #include <libfdt.h>
  30 #include <fdt_support.h>
  31 #include <lcd.h>
  32 #include <netdev.h>
  33 #include <mmc.h>
  34 #include <fsl_esdhc.h>
  35 #include <video_fb.h>
  36 #include <ipu.h>
  37 #include <mx2fb.h>
  38 #include <linux/fb.h>
  39 #include <i2c.h>
  40 #include <asm/io.h>
  41 #include <asm/gpio.h>
  42 #include <asm/arch/iomux-mx6.h>
  43 #include <asm/arch/clock.h>
  44 #include <asm/arch/imx-regs.h>
  45 #include <asm/arch/crm_regs.h>
  46 #include <asm/arch/sys_proto.h>
  47
  48 #include "../common/karo.h"
  49
  50 #define TX6DL_FEC_RST_GPIO              IMX_GPIO_NR(7, 6)
  51 #define TX6DL_FEC_PWR_GPIO              IMX_GPIO_NR(3, 20)
  52 #define TX6DL_FEC_INT_GPIO              IMX_GPIO_NR(2, 4)
  53 #define TX6DL_LED_GPIO                  IMX_GPIO_NR(2, 20)
  54
  55 #define TX6DL_LCD_PWR_GPIO              IMX_GPIO_NR(2, 31)
  56 #define TX6DL_LCD_RST_GPIO              IMX_GPIO_NR(3, 29)
  57 #define TX6DL_LCD_BACKLIGHT_GPIO                IMX_GPIO_NR(1, 1)
  58
  59 #define TX6DL_RESET_OUT_GPIO            IMX_GPIO_NR(7, 12)
  60
  61 #define TEMPERATURE_MIN                 -40
  62 #define TEMPERATURE_HOT                 80
  63 #define TEMPERATURE_MAX                 125
  64
  65 DECLARE_GLOBAL_DATA_PTR;
  66
  67 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  68
  69 static const iomux_v3_cfg_t tx6dl_pads[] = {
  70         /* NAND flash pads */
  71         MX6_PAD_NANDF_CLE__RAWNAND_CLE,
  72         MX6_PAD_NANDF_ALE__RAWNAND_ALE,
  73         MX6_PAD_NANDF_WP_B__RAWNAND_RESETN,
  74         MX6_PAD_NANDF_RB0__RAWNAND_READY0,
  75         MX6_PAD_NANDF_CS0__RAWNAND_CE0N,
  76         MX6_PAD_SD4_CMD__RAWNAND_RDN,
  77         MX6_PAD_SD4_CLK__RAWNAND_WRN,
  78         MX6_PAD_NANDF_D0__RAWNAND_D0,
  79         MX6_PAD_NANDF_D1__RAWNAND_D1,
  80         MX6_PAD_NANDF_D2__RAWNAND_D2,
  81         MX6_PAD_NANDF_D3__RAWNAND_D3,
  82         MX6_PAD_NANDF_D4__RAWNAND_D4,
  83         MX6_PAD_NANDF_D5__RAWNAND_D5,
  84         MX6_PAD_NANDF_D6__RAWNAND_D6,
  85         MX6_PAD_NANDF_D7__RAWNAND_D7,
  86
  87         /* RESET_OUT */
  88         MX6_PAD_GPIO_17__GPIO_7_12,
  89
  90         /* UART pads */
  91 #if CONFIG_MXC_UART_BASE == UART1_BASE
  92         MX6_PAD_SD3_DAT7__UART1_TXD,
  93         MX6_PAD_SD3_DAT6__UART1_RXD,
  94         MX6_PAD_SD3_DAT1__UART1_RTS,
  95         MX6_PAD_SD3_DAT0__UART1_CTS,
  96 #endif
  97 #if CONFIG_MXC_UART_BASE == UART2_BASE
  98         MX6_PAD_SD4_DAT4__UART2_RXD,
  99         MX6_PAD_SD4_DAT7__UART2_TXD,
 100         MX6_PAD_SD4_DAT5__UART2_RTS,
 101         MX6_PAD_SD4_DAT6__UART2_CTS,
 102 #endif
 103 #if CONFIG_MXC_UART_BASE == UART3_BASE
 104         MX6_PAD_EIM_D24__UART3_TXD,
 105         MX6_PAD_EIM_D25__UART3_RXD,
 106         MX6_PAD_SD3_RST__UART3_RTS,
 107         MX6_PAD_SD3_DAT3__UART3_CTS,
 108 #endif
 109         /* internal I2C */
 110         MX6_PAD_EIM_D28__I2C1_SDA,
 111         MX6_PAD_EIM_D21__I2C1_SCL,
 112
 113         /* FEC PHY GPIO functions */
 114         MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
 115         MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
 116         MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
 117 };
 118
 119 static const iomux_v3_cfg_t tx6dl_fec_pads[] = {
 120         /* FEC functions */
 121         MX6_PAD_ENET_MDC__ENET_MDC,
 122         MX6_PAD_ENET_MDIO__ENET_MDIO,
 123         MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
 124         MX6_PAD_ENET_RX_ER__ENET_RX_ER,
 125         MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
 126         MX6_PAD_ENET_RXD1__ENET_RDATA_1,
 127         MX6_PAD_ENET_RXD0__ENET_RDATA_0,
 128         MX6_PAD_ENET_TX_EN__ENET_TX_EN,
 129         MX6_PAD_ENET_TXD1__ENET_TDATA_1,
 130         MX6_PAD_ENET_TXD0__ENET_TDATA_0,
 131 };
 132
 133 static const struct gpio tx6dl_gpios[] = {
 134         { TX6DL_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 135         { TX6DL_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 136         { TX6DL_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 137         { TX6DL_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
 138 };
 139
 140 /*
 141  * Functions
 142  */
 143 /* placed in section '.data' to prevent overwriting relocation info
 144  * overlayed with bss
 145  */
 146 static u32 wrsr __attribute__((section(".data")));
 147
 148 #define WRSR_POR                        (1 << 4)
 149 #define WRSR_TOUT                       (1 << 1)
 150 #define WRSR_SFTW                       (1 << 0)
 151
 152 static void print_reset_cause(void)
 153 {
 154         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 155         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 156         u32 srsr;
 157         char *dlm = "";
 158
 159         printf("Reset cause: ");
 160
 161         srsr = readl(&src_regs->srsr);
 162         wrsr = readw(wdt_base + 4);
 163
 164         if (wrsr & WRSR_POR) {
 165                 printf("%sPOR", dlm);
 166                 dlm = " | ";
 167         }
 168         if (srsr & 0x00004) {
 169                 printf("%sCSU", dlm);
 170                 dlm = " | ";
 171         }
 172         if (srsr & 0x00008) {
 173                 printf("%sIPP USER", dlm);
 174                 dlm = " | ";
 175         }
 176         if (srsr & 0x00010) {
 177                 if (wrsr & WRSR_SFTW) {
 178                         printf("%sSOFT", dlm);
 179                         dlm = " | ";
 180                 }
 181                 if (wrsr & WRSR_TOUT) {
 182                         printf("%sWDOG", dlm);
 183                         dlm = " | ";
 184                 }
 185         }
 186         if (srsr & 0x00020) {
 187                 printf("%sJTAG HIGH-Z", dlm);
 188                 dlm = " | ";
 189         }
 190         if (srsr & 0x00040) {
 191                 printf("%sJTAG SW", dlm);
 192                 dlm = " | ";
 193         }
 194         if (srsr & 0x10000) {
 195                 printf("%sWARM BOOT", dlm);
 196                 dlm = " | ";
 197         }
 198         if (dlm[0] == '\0')
 199                 printf("unknown");
 200
 201         printf("\n");
 202 }
 203
 204 int read_cpu_temperature(void);
 205 int check_cpu_temperature(int boot);
 206
 207 static void print_cpuinfo(void)
 208 {
 209         u32 cpurev = get_cpu_rev();
 210         char *cpu_str = "?";
 211
 212         switch ((cpurev >> 12) & 0xff) {
 213         case MXC_CPU_MX6SL:
 214                 cpu_str = "SL";
 215                 break;
 216         case MXC_CPU_MX6DL:
 217                 cpu_str = "DL";
 218                 break;
 219         case MXC_CPU_MX6SOLO:
 220                 cpu_str = "SOLO";
 221                 break;
 222         case MXC_CPU_MX6Q:
 223                 cpu_str = "Q";
 224                 break;
 225         }
 226
 227         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 228                 cpu_str,
 229                 (cpurev & 0x000F0) >> 4,
 230                 (cpurev & 0x0000F) >> 0,
 231                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 232
 233         print_reset_cause();
 234         check_cpu_temperature(1);
 235 }
 236
 237 #define LTC3676_DVB2A           0x0C
 238 #define LTC3676_DVB2B           0x0D
 239 #define LTC3676_DVB4A           0x10
 240 #define LTC3676_DVB4B           0x11
 241
 242 #define VDD_SOC_mV              (1375 + 50)
 243 #define VDD_CORE_mV             (1375 + 50)
 244
 245 #define mV_to_regval(mV)        (((mV) * 360 / 330 - 825 + 1) / 25)
 246 #define regval_to_mV(v)         (((v) * 25 + 825) * 330 / 360)
 247
 248 static int setup_pmic_voltages(void)
 249 {
 250         int ret;
 251         unsigned char value;
 252
 253         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 254
 255         ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
 256         if (ret != 0) {
 257                 printf("Failed to initialize I2C\n");
 258                 return ret;
 259         }
 260
 261         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
 262         if (ret) {
 263                 printf("%s: i2c_read error: %d\n", __func__, ret);
 264                 return ret;
 265         }
 266
 267         /* VDDCORE/VDDSOC default 1.375V is not enough, considering
 268            pfuze tolerance and IR drop and ripple, need increase
 269            to 1.425V for SabreSD */
 270
 271         value = 0x39; /* VB default value & PGOOD not forced when slewing */
 272         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2B, 1, &value, 1);
 273         if (ret) {
 274                 printf("%s: failed to write PMIC DVB2B register: %d\n",
 275                         __func__, ret);
 276                 return ret;
 277         }
 278         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4B, 1, &value, 1);
 279         if (ret) {
 280                 printf("%s: failed to write PMIC DVB4B register: %d\n",
 281                         __func__, ret);
 282                 return ret;
 283         }
 284
 285         value = mV_to_regval(VDD_SOC_mV);
 286         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2A, 1, &value, 1);
 287         if (ret) {
 288                 printf("%s: failed to write PMIC DVB2A register: %d\n",
 289                         __func__, ret);
 290                 return ret;
 291         }
 292         printf("VDDSOC  set to %dmV\n", regval_to_mV(value));
 293
 294         value = mV_to_regval(VDD_CORE_mV);
 295         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4A, 1, &value, 1);
 296         if (ret) {
 297                 printf("%s: failed to write PMIC DVB4A register: %d\n",
 298                         __func__, ret);
 299                 return ret;
 300         }
 301         printf("VDDCORE set to %dmV\n", regval_to_mV(value));
 302         return 0;
 303 }
 304
 305 int board_early_init_f(void)
 306 {
 307         gpio_request_array(tx6dl_gpios, ARRAY_SIZE(tx6dl_gpios));
 308         imx_iomux_v3_setup_multiple_pads(tx6dl_pads, ARRAY_SIZE(tx6dl_pads));
 309
 310         return 0;
 311 }
 312
 313 int board_init(void)
 314 {
 315         int ret;
 316
 317         /* Address of boot parameters */
 318         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 319 #if 1
 320         gd->bd->bi_arch_number = 4429;
 321 #endif
 322         ret = setup_pmic_voltages();
 323         if (ret) {
 324                 printf("Failed to setup PMIC voltages\n");
 325                 hang();
 326         }
 327         return 0;
 328 }
 329
 330 int dram_init(void)
 331 {
 332         /* dram_init must store complete ramsize in gd->ram_size */
 333         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 334                                 PHYS_SDRAM_1_SIZE);
 335         return 0;
 336 }
 337
 338 void dram_init_banksize(void)
 339 {
 340         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 341         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 342                         PHYS_SDRAM_1_SIZE);
 343 #if CONFIG_NR_DRAM_BANKS > 1
 344         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 345         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 346                         PHYS_SDRAM_2_SIZE);
 347 #endif
 348 }
 349
 350 #ifdef  CONFIG_CMD_MMC
 351 static const iomux_v3_cfg_t mmc0_pads[] = {
 352         MX6_PAD_SD1_CMD__USDHC1_CMD,
 353         MX6_PAD_SD1_CLK__USDHC1_CLK,
 354         MX6_PAD_SD1_DAT0__USDHC1_DAT0,
 355         MX6_PAD_SD1_DAT1__USDHC1_DAT1,
 356         MX6_PAD_SD1_DAT2__USDHC1_DAT2,
 357         MX6_PAD_SD1_DAT3__USDHC1_DAT3,
 358         /* SD1 CD */
 359         MX6_PAD_SD3_CMD__GPIO_7_2,
 360 };
 361
 362 static const iomux_v3_cfg_t mmc1_pads[] = {
 363         MX6_PAD_SD2_CMD__USDHC2_CMD,
 364         MX6_PAD_SD2_CLK__USDHC2_CLK,
 365         MX6_PAD_SD2_DAT0__USDHC2_DAT0,
 366         MX6_PAD_SD2_DAT1__USDHC2_DAT1,
 367         MX6_PAD_SD2_DAT2__USDHC2_DAT2,
 368         MX6_PAD_SD2_DAT3__USDHC2_DAT3,
 369         /* SD2 CD */
 370         MX6_PAD_SD3_CLK__GPIO_7_3,
 371 };
 372
 373 static struct tx6dl_esdhc_cfg {
 374         const iomux_v3_cfg_t *pads;
 375         int num_pads;
 376         enum mxc_clock clkid;
 377         struct fsl_esdhc_cfg cfg;
 378 } tx6dl_esdhc_cfg[] = {
 379         {
 380                 .pads = mmc0_pads,
 381                 .num_pads = ARRAY_SIZE(mmc0_pads),
 382                 .clkid = MXC_ESDHC_CLK,
 383                 .cfg = {
 384                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 385                         .cd_gpio = IMX_GPIO_NR(7, 2),
 386                         .wp_gpio = -EINVAL,
 387                 },
 388         },
 389         {
 390                 .pads = mmc1_pads,
 391                 .num_pads = ARRAY_SIZE(mmc1_pads),
 392                 .clkid = MXC_ESDHC2_CLK,
 393                 .cfg = {
 394                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 395                         .cd_gpio = IMX_GPIO_NR(7, 3),
 396                         .wp_gpio = -EINVAL,
 397                 },
 398         },
 399 };
 400
 401 static inline struct tx6dl_esdhc_cfg *to_tx6dl_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 402 {
 403         void *p = cfg;
 404
 405         return p - offsetof(struct tx6dl_esdhc_cfg, cfg);
 406 }
 407
 408 int board_mmc_getcd(struct mmc *mmc)
 409 {
 410         struct fsl_esdhc_cfg *cfg = mmc->priv;
 411
 412         if (cfg->cd_gpio < 0)
 413                 return cfg->cd_gpio;
 414
 415         debug("SD card %d is %spresent\n",
 416                 to_tx6dl_esdhc_cfg(cfg) - tx6dl_esdhc_cfg, gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
 417         return !gpio_get_value(cfg->cd_gpio);
 418 }
 419
 420 int board_mmc_init(bd_t *bis)
 421 {
 422         int i;
 423
 424         for (i = 0; i < ARRAY_SIZE(tx6dl_esdhc_cfg); i++) {
 425                 struct mmc *mmc;
 426                 struct fsl_esdhc_cfg *cfg = &tx6dl_esdhc_cfg[i].cfg;
 427
 428                 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
 429                         break;
 430
 431                 cfg->sdhc_clk = mxc_get_clock(tx6dl_esdhc_cfg[i].clkid);
 432                 imx_iomux_v3_setup_multiple_pads(tx6dl_esdhc_cfg[i].pads,
 433                                                 tx6dl_esdhc_cfg[i].num_pads);
 434
 435                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 436                 fsl_esdhc_initialize(bis, cfg);
 437
 438                 mmc = find_mmc_device(i);
 439                 if (mmc == NULL)
 440                         continue;
 441                 if (board_mmc_getcd(mmc) > 0)
 442                         mmc_init(mmc);
 443         }
 444         return 0;
 445 }
 446 #endif /* CONFIG_CMD_MMC */
 447
 448 #ifdef CONFIG_FEC_MXC
 449
 450 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 451                         PAD_CTL_SRE_FAST)
 452 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 453 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 454
 455 #ifndef ETH_ALEN
 456 #define ETH_ALEN 6
 457 #endif
 458
 459 int board_eth_init(bd_t *bis)
 460 {
 461         int ret;
 462
 463         /* delay at least 21ms for the PHY internal POR signal to deassert */
 464         udelay(22000);
 465
 466         imx_iomux_v3_setup_multiple_pads(tx6dl_fec_pads, ARRAY_SIZE(tx6dl_fec_pads));
 467
 468         /* Deassert RESET to the external phy */
 469         gpio_set_value(TX6DL_FEC_RST_GPIO, 1);
 470
 471         ret = cpu_eth_init(bis);
 472         if (ret)
 473                 printf("cpu_eth_init() failed: %d\n", ret);
 474
 475         return ret;
 476 }
 477 #endif /* CONFIG_FEC_MXC */
 478
 479 enum {
 480         LED_STATE_INIT = -1,
 481         LED_STATE_OFF,
 482         LED_STATE_ON,
 483 };
 484
 485 static inline int calc_blink_rate(int tmp)
 486 {
 487         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 488                 (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 489                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 490 }
 491
 492 void show_activity(int arg)
 493 {
 494         static int led_state = LED_STATE_INIT;
 495         static int blink_rate;
 496         static ulong last;
 497
 498         if (led_state == LED_STATE_INIT) {
 499                 last = get_timer(0);
 500                 gpio_set_value(TX6DL_LED_GPIO, 1);
 501                 led_state = LED_STATE_ON;
 502                 blink_rate = calc_blink_rate(check_cpu_temperature(0));
 503         } else {
 504                 if (get_timer(last) > blink_rate) {
 505                         blink_rate = calc_blink_rate(check_cpu_temperature(0));
 506                         last = get_timer_masked();
 507                         if (led_state == LED_STATE_ON) {
 508                                 gpio_set_value(TX6DL_LED_GPIO, 0);
 509                         } else {
 510                                 gpio_set_value(TX6DL_LED_GPIO, 1);
 511                         }
 512                         led_state = 1 - led_state;
 513                 }
 514         }
 515 }
 516
 517 static const iomux_v3_cfg_t stk5_pads[] = {
 518         /* SW controlled LED on STK5 baseboard */
 519         MX6_PAD_EIM_A18__GPIO_2_20,
 520
 521         /* LCD data pins */
 522         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
 523         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
 524         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
 525         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
 526         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
 527         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
 528         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
 529         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
 530         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
 531         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
 532         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
 533         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
 534         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
 535         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
 536         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
 537         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
 538         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
 539         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
 540         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
 541         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
 542         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
 543         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
 544         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
 545         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
 546         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
 547         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
 548         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
 549         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
 550
 551         /* I2C bus on DIMM pins 40/41 */
 552         MX6_PAD_GPIO_6__I2C3_SDA,
 553         MX6_PAD_GPIO_3__I2C3_SCL,
 554
 555         /* TSC200x PEN IRQ */
 556         MX6_PAD_EIM_D26__GPIO_3_26,
 557
 558         /* EDT-FT5x06 Polytouch panel */
 559         MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
 560         MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */
 561         MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */
 562
 563         /* USBH1 */
 564         MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
 565         MX6_PAD_EIM_D30__GPIO_3_30, /* OC */
 566         /* USBOTG */
 567         MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
 568         MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
 569         MX6_PAD_GPIO_8__GPIO_1_8, /* OC */
 570 };
 571
 572 static const struct gpio stk5_gpios[] = {
 573         { TX6DL_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 574
 575         { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
 576         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
 577         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 578         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
 579         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 580 };
 581
 582 #ifdef CONFIG_LCD
 583 vidinfo_t panel_info = {
 584         /* set to max. size supported by SoC */
 585         .vl_col = 1920,
 586         .vl_row = 1080,
 587
 588         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 589 };
 590
 591 static struct fb_videomode tx6dl_fb_mode = {
 592         /* Standard VGA timing */
 593         .name           = "VGA",
 594         .refresh        = 60,
 595         .xres           = 640,
 596         .yres           = 480,
 597         .pixclock       = KHZ2PICOS(25175),
 598         .left_margin    = 48,
 599         .hsync_len      = 96,
 600         .right_margin   = 16,
 601         .upper_margin   = 31,
 602         .vsync_len      = 2,
 603         .lower_margin   = 12,
 604         .sync           = FB_SYNC_CLK_LAT_FALL,
 605         .vmode          = FB_VMODE_NONINTERLACED,
 606 };
 607
 608 static int lcd_enabled = 1;
 609
 610 void lcd_enable(void)
 611 {
 612         /* HACK ALERT:
 613          * global variable from common/lcd.c
 614          * Set to 0 here to prevent messages from going to LCD
 615          * rather than serial console
 616          */
 617         lcd_is_enabled = 0;
 618
 619         karo_load_splashimage(1);
 620         if (lcd_enabled) {
 621                 debug("Switching LCD on\n");
 622                 gpio_set_value(TX6DL_LCD_PWR_GPIO, 1);
 623                 udelay(100);
 624                 gpio_set_value(TX6DL_LCD_RST_GPIO, 1);
 625                 udelay(300000);
 626                 gpio_set_value(TX6DL_LCD_BACKLIGHT_GPIO, 0);
 627         }
 628 }
 629
 630 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 631         /* LCD RESET */
 632         MX6_PAD_EIM_D29__GPIO_3_29,
 633         /* LCD POWER_ENABLE */
 634         MX6_PAD_EIM_EB3__GPIO_2_31,
 635         /* LCD Backlight (PWM) */
 636         MX6_PAD_GPIO_1__GPIO_1_1,
 637
 638         /* Display */
 639         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
 640         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
 641         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
 642         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
 643         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
 644         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
 645         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
 646         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
 647         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
 648         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
 649         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
 650         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
 651         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
 652         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
 653         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
 654         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
 655         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
 656         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
 657         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
 658         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
 659         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
 660         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
 661         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
 662         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
 663         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
 664         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
 665         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
 666         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
 667 };
 668
 669 static const struct gpio stk5_lcd_gpios[] = {
 670         { TX6DL_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 671         { TX6DL_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 672         { TX6DL_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 673 };
 674
 675 void lcd_ctrl_init(void *lcdbase)
 676 {
 677         int color_depth = 24;
 678         char *vm;
 679         unsigned long val;
 680         int refresh = 60;
 681         struct fb_videomode *p = &tx6dl_fb_mode;
 682         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 683         int pix_fmt = 0;
 684         ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
 685         unsigned long di_clk_rate = 65000000;
 686
 687         if (!lcd_enabled) {
 688                 debug("LCD disabled\n");
 689                 return;
 690         }
 691
 692         if (tstc() || (wrsr & WRSR_TOUT)) {
 693                 debug("Disabling LCD\n");
 694                 lcd_enabled = 0;
 695                 return;
 696         }
 697
 698         vm = getenv("video_mode");
 699         if (vm == NULL) {
 700                 debug("Disabling LCD\n");
 701                 lcd_enabled = 0;
 702                 return;
 703         }
 704         while (*vm != '\0') {
 705                 if (*vm >= '0' && *vm <= '9') {
 706                         char *end;
 707
 708                         val = simple_strtoul(vm, &end, 0);
 709                         if (end > vm) {
 710                                 if (!xres_set) {
 711                                         if (val > panel_info.vl_col)
 712                                                 val = panel_info.vl_col;
 713                                         p->xres = val;
 714                                         panel_info.vl_col = val;
 715                                         xres_set = 1;
 716                                 } else if (!yres_set) {
 717                                         if (val > panel_info.vl_row)
 718                                                 val = panel_info.vl_row;
 719                                         p->yres = val;
 720                                         panel_info.vl_row = val;
 721                                         yres_set = 1;
 722                                 } else if (!bpp_set) {
 723                                         switch (val) {
 724                                         case 24:
 725                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666)
 726                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
 727                                                 /* fallthru */
 728                                         case 16:
 729                                         case 8:
 730                                                 color_depth = val;
 731                                                 break;
 732
 733                                         case 18:
 734                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 735                                                         color_depth = val;
 736                                                         break;
 737                                                 }
 738                                                 /* fallthru */
 739                                         default:
 740                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 741                                                         end - vm, vm, color_depth);
 742                                         }
 743                                         bpp_set = 1;
 744                                 } else if (!refresh_set) {
 745                                         refresh = val;
 746                                         refresh_set = 1;
 747                                 }
 748                         }
 749                         vm = end;
 750                 }
 751                 switch (*vm) {
 752                 case '@':
 753                         bpp_set = 1;
 754                         /* fallthru */
 755                 case '-':
 756                         yres_set = 1;
 757                         /* fallthru */
 758                 case 'x':
 759                         xres_set = 1;
 760                         /* fallthru */
 761                 case 'M':
 762                 case 'R':
 763                         vm++;
 764                         break;
 765
 766                 default:
 767                         if (!pix_fmt) {
 768                                 char *tmp;
 769
 770                                 if (strncmp(vm, "LVDS", 4) == 0) {
 771                                         pix_fmt = IPU_PIX_FMT_LVDS666;
 772                                         di_clk_parent = DI_PCLK_LDB;
 773                                 } else {
 774                                         pix_fmt = IPU_PIX_FMT_RGB24;
 775                                 }
 776                                 tmp = strchr(vm, ':');
 777                                 if (tmp)
 778                                         vm = tmp;
 779                         }
 780                         if (*vm != '\0')
 781                                 vm++;
 782                 }
 783         }
 784         switch (color_depth) {
 785         case 8:
 786                 panel_info.vl_bpix = 3;
 787                 break;
 788
 789         case 16:
 790                 panel_info.vl_bpix = 4;
 791                 break;
 792
 793         case 18:
 794         case 24:
 795                 panel_info.vl_bpix = 5;
 796         }
 797
 798         p->pixclock = KHZ2PICOS(refresh *
 799                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 800                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
 801                 / 1000);
 802         debug("Pixel clock set to %lu.%03lu MHz\n",
 803                 PICOS2KHZ(p->pixclock) / 1000,
 804                 PICOS2KHZ(p->pixclock) % 1000);
 805
 806         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 807         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
 808                                         ARRAY_SIZE(stk5_lcd_pads));
 809
 810         debug("Initializing FB driver\n");
 811         if (!pix_fmt)
 812                 pix_fmt = IPU_PIX_FMT_RGB24;
 813         else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 814                 writel(0x01, IOMUXC_BASE_ADDR + 8);
 815         } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
 816                 writel(0x21, IOMUXC_BASE_ADDR + 8);
 817         }
 818         if (pix_fmt != IPU_PIX_FMT_RGB24) {
 819                 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 820                 /* enable LDB & DI0 clock */
 821                 writel(readl(&ccm_regs->CCGR3) | (3 << 12) | (3 << 2),
 822                         &ccm_regs->CCGR3);
 823         }
 824
 825         if (karo_load_splashimage(0) == 0) {
 826                 debug("Initializing LCD controller\n");
 827                 ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
 828         } else {
 829                 debug("Skipping initialization of LCD controller\n");
 830         }
 831 }
 832 #else
 833 #define lcd_enabled 0
 834 #endif /* CONFIG_LCD */
 835
 836 static void stk5_board_init(void)
 837 {
 838         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
 839         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
 840 }
 841
 842 static void stk5v3_board_init(void)
 843 {
 844         stk5_board_init();
 845 }
 846
 847 static void stk5v5_board_init(void)
 848 {
 849         stk5_board_init();
 850
 851         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
 852                         "Flexcan Transceiver");
 853         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21);
 854 }
 855
 856 static void tx6dl_set_cpu_clock(void)
 857 {
 858         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
 859
 860         if (tstc() || (wrsr & WRSR_TOUT))
 861                 return;
 862
 863         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
 864                 return;
 865
 866         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
 867                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
 868                 printf("CPU clock set to %lu.%03lu MHz\n",
 869                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
 870         } else {
 871                 printf("Failed to set CPU clock to %lu MHz\n", cpu_clk);
 872         }
 873 }
 874
 875 static void tx6_init_mac(void)
 876 {
 877         u8 mac[ETH_ALEN];
 878         char mac_str[ETH_ALEN * 3] = "";
 879
 880         imx_get_mac_from_fuse(-1, mac);
 881         if (!is_valid_ether_addr(mac)) {
 882                 printf("No valid MAC address programmed\n");
 883                 return;
 884         }
 885
 886         snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x",
 887                 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 888         setenv("ethaddr", mac_str);
 889         printf("MAC addr from fuse: %02x:%02x:%02x:%02x:%02x:%02x\n",
 890                 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 891 }
 892
 893 int board_late_init(void)
 894 {
 895         int ret = 0;
 896         const char *baseboard;
 897
 898         tx6dl_set_cpu_clock();
 899         karo_fdt_move_fdt();
 900
 901         baseboard = getenv("baseboard");
 902         if (!baseboard)
 903                 goto exit;
 904
 905         printf("Baseboard: %s\n", baseboard);
 906
 907         if (strncmp(baseboard, "stk5", 4) == 0) {
 908                 if ((strlen(baseboard) == 4) ||
 909                         strcmp(baseboard, "stk5-v3") == 0) {
 910                         stk5v3_board_init();
 911                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
 912                         stk5v5_board_init();
 913                 } else {
 914                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
 915                                 baseboard + 4);
 916                 }
 917         } else {
 918                 printf("WARNING: Unsupported baseboard: '%s'\n",
 919                         baseboard);
 920                 ret = -EINVAL;
 921         }
 922
 923 exit:
 924         tx6_init_mac();
 925
 926         gpio_set_value(TX6DL_RESET_OUT_GPIO, 1);
 927         return ret;
 928 }
 929
 930 #define iomux_field(v,f)        (((iomux_v3_cfg_t)(v) << f##_SHIFT) & f##_MASK)
 931
 932 #define chk_iomux_field(f1,f2)  ({                                      \
 933         iomux_v3_cfg_t __c = iomux_field(~0, f1);                       \
 934         if (__c & f2##_MASK) {                                          \
 935                 printf("%18s[%016llx] overlaps with:\n%18s[%016llx]\n", \
 936                         #f1, f1##_MASK,                                 \
 937                         #f2, f2##_MASK);                                \
 938         }                                                               \
 939         (__c & f2##_MASK) != 0;                                         \
 940 })
 941
 942 #define chk_iomux_bit(f1,f2)    ({                                      \
 943         iomux_v3_cfg_t __c = iomux_field(~0, f1);                       \
 944         if (__c & f2) {                                                 \
 945                 printf("%18s[%016llx] overlaps with:\n%18s[%016llx]\n", \
 946                         #f1, f1##_MASK,                                 \
 947                         #f2, (iomux_v3_cfg_t)f2);                       \
 948         }                                                               \
 949         (__c & f2) != 0;                                                \
 950 })
 951
 952 int checkboard(void)
 953 {
 954         print_cpuinfo();
 955
 956         printf("Board: Ka-Ro TX6DL\n");
 957
 958         printf("mtdparts='%s'\n", MTDPARTS_DEFAULT);
 959
 960 #ifdef TIMER_TEST
 961         {
 962                 struct mxc_gpt {
 963                         unsigned int control;
 964                         unsigned int prescaler;
 965                         unsigned int status;
 966                         unsigned int nouse[6];
 967                         unsigned int counter;
 968                 };
 969                 const int us_delay = 10;
 970                 unsigned long start = get_timer(0);
 971                 unsigned long last = gd->arch.tbl;
 972                 unsigned long loop = 0;
 973                 unsigned long cnt = 0;
 974                 static struct mxc_gpt *timer_base = (struct mxc_gpt *)GPT1_BASE_ADDR;
 975
 976                 printf("GPT prescaler=%u\n", readl(&timer_base->prescaler) + 1);
 977                 printf("clock tick rate: %lu.%03lukHz\n",
 978                         gd->arch.timer_rate_hz / 1000, gd->arch.timer_rate_hz % 1000);
 979                 printf("ticks/us=%lu\n", gd->arch.timer_rate_hz / CONFIG_SYS_HZ / 1000);
 980
 981                 while (!tstc()) {
 982                         unsigned long elapsed = get_timer(start);
 983                         unsigned long diff = gd->arch.tbl - last;
 984
 985                         loop++;
 986                         last = gd->arch.tbl;
 987
 988                         printf("loop %4lu: t=%08lx diff=%08lx steps=%6lu elapsed time: %4lu",
 989                                 loop, gd->arch.tbl, diff, cnt, elapsed / CONFIG_SYS_HZ);
 990                         cnt = 0;
 991                         while (get_timer(elapsed + start) < CONFIG_SYS_HZ) {
 992                                 cnt++;
 993                                 udelay(us_delay);
 994                         }
 995                         printf(" counter=%08x udelay(%u)=%lu.%03luus\n",
 996                                 readl(&timer_base->counter), us_delay,
 997                                 1000000000 / cnt / 1000, 1000000000 / cnt % 1000);
 998                 }
 999         }
1000 #endif
1001         return 0;
1002 }
1003
1004 #ifdef CONFIG_SERIAL_TAG
1005 void get_board_serial(struct tag_serialnr *serialnr)
1006 {
1007         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
1008         struct fuse_bank0_regs *fuse = (void *)iim->bank[0].fuse_regs;
1009
1010         serialnr->low = readl(&fuse->cfg0);
1011         serialnr->high = readl(&fuse->cfg1);
1012 }
1013 #endif
1014
1015 #if defined(CONFIG_OF_BOARD_SETUP)
1016 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1017 #include <jffs2/jffs2.h>
1018 #include <mtd_node.h>
1019 struct node_info nodes[] = {
1020         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1021 };
1022
1023 #else
1024 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1025 #endif
1026
1027 static void tx6dl_fixup_flexcan(void *blob)
1028 {
1029         const char *baseboard = getenv("baseboard");
1030
1031         if (baseboard && strcmp(baseboard, "stk5-v5") == 0)
1032                 return;
1033         /* TODO: handle flexcan transceiver GPIO */
1034 }
1035
1036 void ft_board_setup(void *blob, bd_t *bd)
1037 {
1038         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1039         fdt_fixup_ethernet(blob);
1040
1041         karo_fdt_fixup_touchpanel(blob);
1042         karo_fdt_fixup_usb_otg(blob, "", 0);
1043         tx6dl_fixup_flexcan(blob);
1044 }
1045 #endif