2 #include <configs/tx6q.h>
3 #include <asm/arch/imx-regs.h>
5 #define DEBUG_LED_BIT 20
6 #define LED_GPIO_BASE GPIO2_BASE_ADDR
7 #define LED_MUX_OFFSET 0x0ec
8 #define LED_MUX_MODE 0x15
10 #define SDRAM_CLK CONFIG_SYS_SDRAM_CLK
12 #ifdef PHYS_SDRAM_2_SIZE
13 #define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
15 #define SDRAM_SIZE PHYS_SDRAM_1_SIZE
18 #define CPU_2_BE_32(l) \
19 ((((l) << 24) & 0xFF000000) | \
20 (((l) << 8) & 0x00FF0000) | \
21 (((l) >> 8) & 0x0000FF00) | \
22 (((l) >> 24) & 0x000000FF))
24 #define MXC_DCD_ITEM(addr, val) .word CPU_2_BE_32(addr), CPU_2_BE_32(val)
26 #define CHECK_DCD_ADDR(a) ((((a) >= 0x00907000) && ((a) <= 0x00937FF0)) || \
27 (((a) >= 0x020C4000) && ((a) < 0x020C8000)) || \
28 (((a) >= 0x020C8000) && ((a) < 0x020C9000)) || \
29 (((a) >= 0x020E0000) && ((a) < 0x020E4000)) || \
30 (((a) >= 0x021B0000) && ((a) < 0x021B8000)) || \
31 (((a) >= 0x08000000) && ((a) < 0x0FFF0000)) || \
32 (((a) >= 0x10000000)))
34 #define MXC_DCD_CMD_SZ_BYTE 1
35 #define MXC_DCD_CMD_SZ_SHORT 2
36 #define MXC_DCD_CMD_SZ_WORD 4
37 #define MXC_DCD_CMD_FLAG_WRITE 0x0
38 #define MXC_DCD_CMD_FLAG_CLR 0x1
39 #define MXC_DCD_CMD_FLAG_SET 0x3
40 #define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0)
41 #define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1)
42 #define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1)
44 #define MXC_DCD_CMD_WRT(type, flags, next) \
45 .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
47 #define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
48 .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\
49 CPU_2_BE_32(addr), CPU_2_BE_32(mask)
51 #define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
52 .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\
53 CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
55 #define MXC_DCD_CMD_NOP \
56 .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
58 #define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
59 #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
61 .macro CK_VAL, name, clks, offs, max
65 .ifle \clks - \offs - \max
66 .set \name, \clks - \offs
71 .macro NS_VAL, name, ns, offs, max
75 CK_VAL \name, NS_TO_CK(\ns), \offs, \max
79 .macro CK_MAX, name, ck1, ck2, offs, max
81 CK_VAL \name, \ck1, \offs, \max
83 CK_VAL \name, \ck2, \offs, \max
87 #define MDMISC_DDR_TYPE_DDR3 0
88 #define MDMISC_DDR_TYPE_LPDDR2 1
89 #define MDMISC_DDR_TYPE_DDR2 2
91 #define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d))
93 #define MDOR_CLK_PERIOD_ns 15258 /* base clock for MDOR values */
96 #if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
97 #define BANK_ADDR_BITS 2
99 #define BANK_ADDR_BITS 1
101 #define SDRAM_BURST_LENGTH 8
105 #define ADDR_MIRROR 1
106 #define DDR_TYPE MDMISC_DDR_TYPE_DDR3
108 /* 512/1024MiB SDRAM: NT5CB128M16P-CG */
110 NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
111 CK_MAX tXS, tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
112 CK_MAX tXP, 3, NS_TO_CK(6), 1, 7 /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */
113 CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
114 NS_VAL tFAW, 45, 1, 31 /* clks - 1 (0..31) */
115 CK_VAL tCL, 8, 3, 8 /* clks - 3 (0..8) CAS Latency */
118 NS_VAL tRCD, 14, 1, 7 /* clks - 1 (0..7) */
119 NS_VAL tRP, 14, 1, 7 /* clks - 1 (0..7) */
120 NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */
121 NS_VAL tRAS, 36, 1, 31 /* clks - 1 (0..31) */
122 CK_VAL tRPA, 0, 0, 1 /* clks (0..1) */
123 NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
124 CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
125 CK_VAL tCWL, 6, 2, 6 /* clks - 2 (0..6) */
128 CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
129 CK_MAX tRTP, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
130 CK_MAX tWTR, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
131 CK_MAX tRRD, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
134 CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
135 #define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2)
136 #define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2)
139 NS_VAL tAOFPD, 9, 1, 7 /* clks - 1 (0..7) */
140 NS_VAL tAONPD, 9, 1, 7 /* clks - 1 (0..7) */
141 CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
142 CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
143 CK_VAL tODTLon tCWL, 1, 7 /* clks - 1 (0..7) */
144 CK_VAL tODTLoff tCWL, 1, 31 /* clks - 1 (0..31) */
147 CK_MAX tCKE, NS_TO_CK(6), 3, 1, 7
148 CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7
149 CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7
156 #define MDPDC_VAL_0 ( \
161 (BOTH_CS_PD << 6) | \
166 #define MDPDC_VAL_1 (MDPDC_VAL_0 | \
171 #define ROW_ADDR_BITS 14
172 #define COL_ADDR_BITS 10
175 .set mr0_val, ((1 << 8) /* DLL Reset */ | \
176 ((tWR + 1 - 4) << 9) | \
177 (((tCL + 3) - 4) << 4))
179 .set mr0_val, ((1 << 8) /* DLL Reset */ | \
180 (((tWR + 1) / 2) << 9) | \
181 (((tCL + 3) - 4) << 4))
183 #define MDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \
184 (1 << 15) /* CON REQ */ | \
185 (3 << 4) /* MRS command */ | \
189 #define mr1_val 0x0040
190 #define mr2_val 0x0408
192 #define MDCFG0_VAL ( \
200 #define MDCFG1_VAL ( \
210 #define MDCFG2_VAL ( \
216 #define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
217 #define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
218 ((COL_ADDR_BITS - 9) << 20) | \
219 (BURST_LEN << 19) | \
220 (2 << 16) | /* SDRAM bus width */ \
221 ((-1) << (32 - BANK_ADDR_BITS)))
223 #define MDMISC_VAL ((ADDR_MIRROR << 19) | \
230 #define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
232 #define MDOTC_VAL ((tAOFPD << 27) | \
243 .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
259 .long CONFIG_U_BOOT_IMG_SIZE
263 #define DCD_VERSION 0x40
265 #define CLKCTL_CCGR0 0x68
266 #define CLKCTL_CCGR1 0x6c
267 #define CLKCTL_CCGR2 0x70
268 #define CLKCTL_CCGR3 0x74
269 #define CLKCTL_CCGR4 0x78
270 #define CLKCTL_CCGR5 0x7c
271 #define CLKCTL_CCGR6 0x80
272 #define CLKCTL_CCGR7 0x84
273 #define CLKCTL_CMEOR 0x88
275 #define DDR_SEL_VAL 3
279 #define DDR_SEL_SHIFT 18
280 #define DDR_MODE_SHIFT 17
288 #define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT)
289 #define DDR_MODE_MASK (1 << DDR_MODE_SHIFT)
290 #define DSE_MASK (DSE_VAL << DSE_SHIFT)
291 #define ODT_MASK (ODT_VAL << ODT_SHIFT)
293 #define DQM_MASK (DDR_MODE_MASK | DSE_MASK)
294 #define SDQS_MASK DSE_MASK
295 #define SDODT_MASK (DSE_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
296 #define SDCLK_MASK (DDR_MODE_MASK | DSE_MASK)
297 #define SDCKE_MASK ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
298 #define DDR_ADDR_MASK 0
299 #define DDR_CTRL_MASK (DDR_MODE_MASK | DSE_MASK)
302 .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
304 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_reset)
305 /* RESET_OUT GPIO_7_12 */
306 MXC_DCD_ITEM(0x020e024c, 0x00000005)
308 MXC_DCD_ITEM(0x020c402c, 0x01e436c1) /* CSC2CDR default: 0x007236c1 */
309 MXC_DCD_ITEM(0x020c80e0, 0x00002001) /* ENET PLL */
311 /* enable all relevant clocks... */
312 MXC_DCD_ITEM(0x020c4068, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */
313 MXC_DCD_ITEM(0x020c406c, 0xf0fc0c00) /* default: 0xf0fc0000 */
314 MXC_DCD_ITEM(0x020c4070, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */
315 MXC_DCD_ITEM(0x020c4074, 0x3ff00000) /* default: 0x3ff00000 */
316 MXC_DCD_ITEM(0x020c4078, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */
317 MXC_DCD_ITEM(0x020c407c, 0xff033f0f) /* default: 0xf0033f0f UART1 */
318 MXC_DCD_ITEM(0x020c4080, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */
321 MXC_DCD_ITEM(0x020e0004, 0x48640005) /* default: 0x48400005 ENET_CLK output */
322 /* UART1 pad config */
323 MXC_DCD_ITEM(0x020e02a8, 0x00000001) /* UART1 TXD */
324 MXC_DCD_ITEM(0x020e02ac, 0x00000001) /* UART1 RXD */
325 MXC_DCD_ITEM(0x020e0920, 0x00000003) /* UART1 RXD INPUT_SEL */
326 MXC_DCD_ITEM(0x020e02c0, 0x00000001) /* UART1 CTS */
327 MXC_DCD_ITEM(0x020e02c4, 0x00000001) /* UART1 RTS */
328 MXC_DCD_ITEM(0x020e091c, 0x00000003) /* UART1 RTS INPUT_SEL */
331 MXC_DCD_ITEM(0x020e02d4, 0x00000000) /* NANDF_CLE: NANDF_CLE */
332 MXC_DCD_ITEM(0x020e02d8, 0x00000000) /* NANDF_ALE: NANDF_ALE */
333 MXC_DCD_ITEM(0x020e02dc, 0x00000000) /* NANDF_WP_B: NANDF_WPn */
334 MXC_DCD_ITEM(0x020e02e0, 0x00000000) /* NANDF_RB0: NANDF_READY0 */
335 MXC_DCD_ITEM(0x020e02e4, 0x00000000) /* NANDF_CS0: NANDF_CS0 */
336 MXC_DCD_ITEM(0x020e02f4, 0x00000001) /* SD4_CMD: NANDF_RDn */
337 MXC_DCD_ITEM(0x020e02f8, 0x00000001) /* SD4_CLK: NANDF_WRn */
338 MXC_DCD_ITEM(0x020e02fc, 0x00000000) /* NANDF_D0: NANDF_D0 */
339 MXC_DCD_ITEM(0x020e0300, 0x00000000) /* NANDF_D1: NANDF_D1 */
340 MXC_DCD_ITEM(0x020e0304, 0x00000000) /* NANDF_D2: NANDF_D2 */
341 MXC_DCD_ITEM(0x020e0308, 0x00000000) /* NANDF_D3: NANDF_D3 */
342 MXC_DCD_ITEM(0x020e030c, 0x00000000) /* NANDF_D4: NANDF_D4 */
343 MXC_DCD_ITEM(0x020e0310, 0x00000000) /* NANDF_D5: NANDF_D5 */
344 MXC_DCD_ITEM(0x020e0314, 0x00000000) /* NANDF_D6: NANDF_D6 */
345 MXC_DCD_ITEM(0x020e0318, 0x00000000) /* NANDF_D7: NANDF_D7 */
348 MXC_DCD_ITEM(0x020e02ec, 0x00000000) /* NANDF_CS2: NANDF_CS2 */
350 MXC_DCD_ITEM(0x020e05ac, DQM_MASK)
351 MXC_DCD_ITEM(0x020e05b4, DQM_MASK)
352 MXC_DCD_ITEM(0x020e0528, DQM_MASK)
353 MXC_DCD_ITEM(0x020e0520, DQM_MASK)
354 MXC_DCD_ITEM(0x020e0514, DQM_MASK)
355 MXC_DCD_ITEM(0x020e0510, DQM_MASK)
356 MXC_DCD_ITEM(0x020e05bc, DQM_MASK)
357 MXC_DCD_ITEM(0x020e05c4, DQM_MASK)
359 MXC_DCD_ITEM(0x020e052c, DDR_ADDR_MASK)
360 MXC_DCD_ITEM(0x020e0530, DDR_ADDR_MASK)
361 MXC_DCD_ITEM(0x020e0534, DDR_ADDR_MASK)
362 MXC_DCD_ITEM(0x020e0538, DDR_ADDR_MASK)
363 MXC_DCD_ITEM(0x020e053c, DDR_ADDR_MASK)
364 MXC_DCD_ITEM(0x020e0540, DDR_ADDR_MASK)
365 MXC_DCD_ITEM(0x020e0544, DDR_ADDR_MASK)
366 MXC_DCD_ITEM(0x020e0548, DDR_ADDR_MASK)
367 MXC_DCD_ITEM(0x020e054c, DDR_ADDR_MASK)
368 MXC_DCD_ITEM(0x020e0550, DDR_ADDR_MASK)
369 MXC_DCD_ITEM(0x020e0554, DDR_ADDR_MASK)
370 MXC_DCD_ITEM(0x020e0558, DDR_ADDR_MASK)
371 MXC_DCD_ITEM(0x020e055c, DDR_ADDR_MASK)
372 MXC_DCD_ITEM(0x020e0560, DDR_ADDR_MASK)
373 MXC_DCD_ITEM(0x020e0564, DDR_ADDR_MASK)
374 MXC_DCD_ITEM(0x020e0568, DDR_ADDR_MASK)
376 MXC_DCD_ITEM(0x020e056c, DDR_CTRL_MASK)
378 MXC_DCD_ITEM(0x020e0578, DDR_CTRL_MASK)
379 /* DRAM_SDCLK[0..1] */
380 MXC_DCD_ITEM(0x020e0588, SDCLK_MASK)
381 MXC_DCD_ITEM(0x020e0594, SDCLK_MASK)
383 MXC_DCD_ITEM(0x020e057c, DDR_CTRL_MASK)
384 /* DRAM_SDCKE[0..1] */
385 MXC_DCD_ITEM(0x020e0590, SDCKE_MASK)
386 MXC_DCD_ITEM(0x020e0598, SDCKE_MASK)
387 /* DRAM_SDBA[0..2] */
388 MXC_DCD_ITEM(0x020e0580, 0x00000000)
389 MXC_DCD_ITEM(0x020e0584, 0x00000000)
390 MXC_DCD_ITEM(0x020e058c, 0x00000000)
391 /* DRAM_SDODT[0..1] */
392 MXC_DCD_ITEM(0x020e059c, SDODT_MASK)
393 MXC_DCD_ITEM(0x020e05a0, SDODT_MASK)
395 MXC_DCD_ITEM(0x020e0784, DSE_MASK)
396 MXC_DCD_ITEM(0x020e0788, DSE_MASK)
397 MXC_DCD_ITEM(0x020e0794, DSE_MASK)
398 MXC_DCD_ITEM(0x020e079c, DSE_MASK)
399 MXC_DCD_ITEM(0x020e07a0, DSE_MASK)
400 MXC_DCD_ITEM(0x020e07a4, DSE_MASK)
401 MXC_DCD_ITEM(0x020e07a8, DSE_MASK)
402 MXC_DCD_ITEM(0x020e0748, DSE_MASK)
404 MXC_DCD_ITEM(0x020e074c, DSE_MASK)
406 MXC_DCD_ITEM(0x020e0750, DDR_MODE_MASK)
408 MXC_DCD_ITEM(0x020e0758, 0x00000000)
410 MXC_DCD_ITEM(0x020e0774, DDR_MODE_MASK)
412 MXC_DCD_ITEM(0x020e078c, DSE_MASK)
414 MXC_DCD_ITEM(0x020e0798, DDR_SEL_MASK)
416 MXC_DCD_ITEM(0x020e0768, 1 << PUE_SHIFT)
418 MXC_DCD_ITEM(0x020e0770, 0x00000000)
420 MXC_DCD_ITEM(0x020e0754, ODT_MASK)
421 MXC_DCD_ITEM(0x020e075c, ODT_MASK)
422 MXC_DCD_ITEM(0x020e0760, ODT_MASK)
423 MXC_DCD_ITEM(0x020e0764, ODT_MASK)
424 MXC_DCD_ITEM(0x020e076c, ODT_MASK)
425 MXC_DCD_ITEM(0x020e0778, ODT_MASK)
426 MXC_DCD_ITEM(0x020e077c, ODT_MASK)
427 MXC_DCD_ITEM(0x020e0780, ODT_MASK)
429 /* SDRAM initialization */
430 /* MPRDDQBY[0..7]DL */
431 MXC_DCD_ITEM(0x021b081c, 0x33333333)
432 MXC_DCD_ITEM(0x021b481c, 0x33333333)
433 MXC_DCD_ITEM(0x021b0820, 0x33333333)
434 MXC_DCD_ITEM(0x021b4820, 0x33333333)
435 MXC_DCD_ITEM(0x021b0824, 0x33333333)
436 MXC_DCD_ITEM(0x021b4824, 0x33333333)
437 MXC_DCD_ITEM(0x021b0828, 0x33333333)
438 MXC_DCD_ITEM(0x021b4828, 0x33333333)
440 MXC_DCD_ITEM(0x021b0018, MDMISC_VAL | 2) /* reset MMDC FSM */
442 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0018, 0x00000002)
443 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack)
445 /* MSDSCR Conf Req */
446 MXC_DCD_ITEM(0x021b001c, 0x00008000)
448 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x021b001c, 0x00004000)
449 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_calib)
451 MXC_DCD_ITEM(0x021b0000, MDCTL_VAL)
453 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x021b0018, 0x40000000)
454 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)
456 MXC_DCD_ITEM(0x021b000c, MDCFG0_VAL)
457 MXC_DCD_ITEM(0x021b0010, MDCFG1_VAL)
458 MXC_DCD_ITEM(0x021b0014, MDCFG2_VAL)
459 MXC_DCD_ITEM(0x021b002c, 0x000026d2) /* MDRWD */
460 MXC_DCD_ITEM(0x021b0030, MDOR_VAL)
461 MXC_DCD_ITEM(0x021b0008, MDOTC_VAL)
462 MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_0)
463 MXC_DCD_ITEM(0x021b0040, 0x00000027) /* MDASP */
466 MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 0, mr0_val))
467 MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 1, mr1_val))
468 MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 2, mr2_val))
469 MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 0))
470 #if BANK_ADDR_BITS > 1
472 MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 0, mr0_val))
473 MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 1, mr1_val))
474 MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 2, mr2_val))
475 MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
477 MXC_DCD_ITEM(0x021b0020, 0x0000c000) /* disable refresh */
479 MXC_DCD_ITEM(0x021b0818, 0x00011112) /* MPODTCTRL */
480 MXC_DCD_ITEM(0x021b4818, 0x00011112)
482 /* DDR3 calibration */
483 MXC_DCD_ITEM(0x021b0890, 0x00000003) /* select default compare pattern for DQ calibration */
484 MXC_DCD_ITEM(0x021b0404, 0x00011007)
487 MXC_DCD_ITEM(0x021b001c, 0x04008010) /* precharge all */
488 MXC_DCD_ITEM(0x021b001c, 0x04008040) /* MRS: ZQ calibration */
490 MXC_DCD_ITEM(0x021b4800, 0xa138002b)
491 MXC_DCD_ITEM(0x021b0800, 0xa139002b)
493 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0800, 0x00010000)
494 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
497 MXC_DCD_ITEM(0x021b4800, 0xa1380000)
498 MXC_DCD_ITEM(0x021b0800, 0xa1380000)
500 MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
501 MXC_DCD_ITEM(0x021b001c, 0x00808231) /* MRS: start write leveling */
503 MXC_DCD_ITEM(0x021b0808, 0x00000001) /* initiate Write leveling */
505 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00000001)
506 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00000f00)
507 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00000001)
508 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00000f00)
509 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset)
511 MXC_DCD_ITEM(0x021b0800, 0xa138002b)
512 MXC_DCD_ITEM(0x021b4800, 0xa138002b)
514 MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */
516 /* DQS gating calibration */
517 MXC_DCD_ITEM(0x020e05a8, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */
518 MXC_DCD_ITEM(0x020e05b0, SDQS_MASK | 0x7000)
519 MXC_DCD_ITEM(0x020e0524, SDQS_MASK | 0x7000)
520 MXC_DCD_ITEM(0x020e051c, SDQS_MASK | 0x7000)
521 MXC_DCD_ITEM(0x020e0518, SDQS_MASK | 0x7000)
522 MXC_DCD_ITEM(0x020e050c, SDQS_MASK | 0x7000)
523 MXC_DCD_ITEM(0x020e05b8, SDQS_MASK | 0x7000)
524 MXC_DCD_ITEM(0x020e05c0, SDQS_MASK | 0x7000)
525 MXC_DCD_ITEM(0x021b0018, MDMISC_VAL | (7 << 6) | (3 << 16)) /* RALAT/WALAT max. */
527 MXC_DCD_ITEM(0x021b001c, 0x00008020) /* issue one refresh cycle */
528 MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */
530 MXC_DCD_ITEM(0x021b0848, 0x40404040) /* DQ RD Delay default values */
531 MXC_DCD_ITEM(0x021b4848, 0x40404040)
532 MXC_DCD_ITEM(0x021b0850, 0x40404040) /* DQ WR Delay default values */
533 MXC_DCD_ITEM(0x021b4850, 0x40404040)
534 MXC_DCD_ITEM(0x021b48b8, 0x00000800)
535 MXC_DCD_ITEM(0x021b08b8, 0x00000800)
537 MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue fifo reset */
539 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000)
540 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset2)
541 MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue 2nd fifo reset */
543 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000)
544 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)
545 MXC_DCD_ITEM(0x021b083c, 0x50800000) /* choose 32 wait cycles and start DQS calib. */
547 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x10000000)
548 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x00001000)
549 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b483c, 0x10000000)
550 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b483c, 0x00001000)
551 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
553 /* DRAM_SDQS[0..7] pad config */
554 MXC_DCD_ITEM(0x020e05a8, SDQS_MASK)
555 MXC_DCD_ITEM(0x020e05b0, SDQS_MASK)
556 MXC_DCD_ITEM(0x020e0524, SDQS_MASK)
557 MXC_DCD_ITEM(0x020e051c, SDQS_MASK)
558 MXC_DCD_ITEM(0x020e0518, SDQS_MASK)
559 MXC_DCD_ITEM(0x020e050c, SDQS_MASK)
560 MXC_DCD_ITEM(0x020e05b8, SDQS_MASK)
561 MXC_DCD_ITEM(0x020e05c0, SDQS_MASK)
563 MXC_DCD_ITEM(0x021b0018, MDMISC_VAL)
565 /* Read delay calibration */
566 MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */
567 MXC_DCD_ITEM(0x021b0860, 0x00000030) /* MPRDDLHWCTL: HW_RD_DL_EN */
569 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0860, 0x00000010)
570 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4860, 0x00000010)
571 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0860, 0x0000000f)
572 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4860, 0x0000000f)
573 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
575 MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */
576 MXC_DCD_ITEM(0x021b0864, 0x00000030) /* start WR DL calibration */
578 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0864, 0x00000010)
579 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4864, 0x00000010)
580 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0864, 0x0000000f)
581 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4864, 0x0000000f)
582 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack_clr)
584 MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
585 MXC_DCD_ITEM(0x021b0020, 0x00005800) /* MDREF */
586 MXC_DCD_ITEM(0x021b0404, 0x00011006) /* MAPSR */
587 MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_1)
589 /* MDSCR: Normal operation */
590 MXC_DCD_ITEM(0x021b001c, 0x00000000)
592 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b001c, 0x00004000)
594 .ifgt dcd_end - dcd_start - 1768