board/micronas/vct/ehci.c

   1 /*
   2  * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
   3  *
   4  * Original Author Guenter Gebhardt
   5  * Copyright (C) 2006 Micronas GmbH
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11
  12 #include "vct.h"
  13
  14 int vct_ehci_hcd_init(u32 *hccr, u32 *hcor)
  15 {
  16         int retval;
  17         u32 val;
  18         u32 addr;
  19
  20         dcgu_set_reset_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_ON);
  21         dcgu_set_reset_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_ON);
  22         dcgu_set_clk_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_ON);
  23         dcgu_set_clk_switch(DCGU_HW_MODULE_USB_PLL, DCGU_SWITCH_ON);
  24         dcgu_set_reset_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_OFF);
  25
  26         /* Wait until (DCGU_USBPHY_STAT == 7) */
  27         addr = DCGU_USBPHY_STAT(DCGU_BASE);
  28         val = reg_read(addr);
  29         while (val != 7)
  30                 val = reg_read(addr);
  31
  32         dcgu_set_clk_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_ON);
  33         dcgu_set_reset_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_OFF);
  34
  35         retval = scc_reset(SCC_USB_RW, 0);
  36         if (retval) {
  37                 printf("scc_reset(SCC_USB_RW, 0) returned: 0x%x\n", retval);
  38                 return retval;
  39         } else {
  40                 retval = scc_reset(SCC_CPU1_SPDMA_RW, 0);
  41                 if (retval) {
  42                         printf("scc_reset(SCC_CPU1_SPDMA_RW, 0) returned: 0x%x\n",
  43                                retval);
  44                         return retval;
  45                 }
  46         }
  47
  48         if (!retval) {
  49                 /*
  50                  * For the AGU bypass, where the  SCC client provides full
  51                  * physical address
  52                  */
  53                 scc_set_usb_address_generation_mode(1);
  54                 scc_setup_dma(SCC_USB_RW, BCU_USB_BUFFER_1, DMA_LINEAR,
  55                               USE_NO_FH, DMA_READ, 0);
  56                 scc_setup_dma(SCC_CPU1_SPDMA_RW, BCU_USB_BUFFER_1, DMA_LINEAR,
  57                               USE_NO_FH, DMA_WRITE, 0);
  58                 scc_setup_dma(SCC_USB_RW, BCU_USB_BUFFER_0, DMA_LINEAR,
  59                               USE_NO_FH, DMA_WRITE, 0);
  60                 scc_setup_dma(SCC_CPU1_SPDMA_RW, BCU_USB_BUFFER_0, DMA_LINEAR,
  61                               USE_NO_FH, DMA_READ, 0);
  62
  63                 /* Enable memory interface */
  64                 scc_enable(SCC_USB_RW, 1);
  65
  66                 /* Start (start_cmd=0) DMAs */
  67                 scc_dma_cmd(SCC_USB_RW, DMA_START, 0, DMA_READ);
  68                 scc_dma_cmd(SCC_USB_RW, DMA_START, 0, DMA_WRITE);
  69         } else {
  70                 printf("Cannot configure USB memory channel.\n");
  71                 printf("USB can not access RAM. SCC configuration failed.\n");
  72                 return retval;
  73         }
  74
  75         /* Wait a short while */
  76         udelay(300000);
  77
  78         reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c);
  79
  80         /* Set EHCI structures and DATA in RAM */
  81         reg_write(USBH_USBHMISC(USBH_BASE), 0x00840003);
  82         /* Set USBMODE to bigendian and set host mode */
  83         reg_write(USBH_USBMODE(USBH_BASE), 0x00000007);
  84
  85         /*
  86          * USBH_BURSTSIZE MUST EQUAL 0x00001c1c in order for
  87          * 512 byte USB transfers on the bulk pipe to work properly.
  88          * Set USBH_BURSTSIZE to 0x00001c1c
  89          */
  90         reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c);
  91
  92         /* Insert access register addresses */
  93         *hccr = REG_GLOBAL_START_ADDR + USBH_CAPLENGTH(USBH_BASE);
  94         *hcor = REG_GLOBAL_START_ADDR + USBH_USBCMD(USBH_BASE);
  95
  96         return 0;
  97 }