board/miromico/hammerhead/hammerhead.c

   1 /*
   2  * Copyright (C) 2008 Miromico AG
   3  *
   4  * Mostly copied form atmel ATNGW100 sources
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <netdev.h>
  27
  28 #include <asm/io.h>
  29 #include <asm/sdram.h>
  30 #include <asm/arch/clk.h>
  31 #include <asm/arch/hmatrix.h>
  32 #include <asm/arch/memory-map.h>
  33 #include <asm/arch/mmu.h>
  34 #include <asm/arch/portmux.h>
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
  39         {
  40                 .virt_pgno      = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
  41                 .nr_pages       = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
  42                 .phys           = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
  43                                         | MMU_VMR_CACHE_NONE,
  44         }, {
  45                 .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
  46                 .nr_pages       = EBI_SDRAM_SIZE >> PAGE_SHIFT,
  47                 .phys           = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
  48                                         | MMU_VMR_CACHE_WRBACK,
  49         },
  50 };
  51
  52 static const struct sdram_config sdram_config = {
  53         .data_bits      = SDRAM_DATA_32BIT,
  54         .row_bits       = 13,
  55         .col_bits       = 9,
  56         .bank_bits      = 2,
  57         .cas            = 3,
  58         .twr            = 2,
  59         .trc            = 7,
  60         .trp            = 2,
  61         .trcd           = 2,
  62         .tras           = 5,
  63         .txsr           = 5,
  64         /* 7.81 us */
  65         .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
  66 };
  67
  68 #ifdef CONFIG_CMD_NET
  69 int board_eth_init(bd_t *bis)
  70 {
  71         return macb_eth_initialize(0, (void *)MACB0_BASE, bis->bi_phy_id[0]);
  72 }
  73 #endif
  74
  75 int board_early_init_f(void)
  76 {
  77         /* Enable SDRAM in the EBI mux */
  78         hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
  79
  80         portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
  81         portmux_enable_usart1(PORTMUX_DRIVE_MIN);
  82
  83 #if defined(CONFIG_MACB)
  84         portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
  85 #endif
  86 #if defined(CONFIG_MMC)
  87         portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
  88 #endif
  89         return 0;
  90 }
  91
  92 phys_size_t initdram(int board_type)
  93 {
  94         unsigned long expected_size;
  95         unsigned long actual_size;
  96         void *sdram_base;
  97
  98         sdram_base = uncached(EBI_SDRAM_BASE);
  99
 100         expected_size = sdram_init(sdram_base, &sdram_config);
 101         actual_size = get_ram_size(sdram_base, expected_size);
 102
 103         if (expected_size != actual_size)
 104                 printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
 105                        actual_size >> 20, expected_size >> 20);
 106
 107         return actual_size;
 108 }
 109
 110 int board_early_init_r(void)
 111 {
 112         gd->bd->bi_phy_id[0] = 0x01;
 113         return 0;
 114 }
 115
 116 int board_postclk_init(void)
 117 {
 118         /* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */
 119         gclk_enable_output(3, PORTMUX_DRIVE_LOW);
 120         gclk_set_rate(3, GCLK_PARENT_OSC0, 25000000);
 121         return 0;
 122 }