2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/compiler.h>
13 #include <asm/arch/clock.h>
15 #include <asm/arch/display.h>
17 #include <asm/arch/funcmux.h>
18 #include <asm/arch/pinmux.h>
19 #include <asm/arch/pmu.h>
20 #ifdef CONFIG_PWM_TEGRA
21 #include <asm/arch/pwm.h>
23 #include <asm/arch/tegra.h>
24 #include <asm/arch-tegra/ap.h>
25 #include <asm/arch-tegra/board.h>
26 #include <asm/arch-tegra/clk_rst.h>
27 #include <asm/arch-tegra/pmc.h>
28 #include <asm/arch-tegra/sys_proto.h>
29 #include <asm/arch-tegra/uart.h>
30 #include <asm/arch-tegra/warmboot.h>
31 #ifdef CONFIG_TEGRA_CLOCK_SCALING
32 #include <asm/arch/emc.h>
34 #ifdef CONFIG_USB_EHCI_TEGRA
35 #include <asm/arch-tegra/usb.h>
38 #ifdef CONFIG_TEGRA_MMC
39 #include <asm/arch-tegra/tegra_mmc.h>
40 #include <asm/arch-tegra/mmc.h>
42 #include <asm/arch-tegra/xusb-padctl.h>
47 DECLARE_GLOBAL_DATA_PTR;
49 #ifdef CONFIG_SPL_BUILD
50 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
51 U_BOOT_DEVICE(tegra_gpios) = {
56 __weak void pinmux_init(void) {}
57 __weak void pin_mux_usb(void) {}
58 __weak void pin_mux_spi(void) {}
59 __weak void gpio_early_init_uart(void) {}
60 __weak void pin_mux_display(void) {}
62 #if defined(CONFIG_TEGRA_NAND)
63 __weak void pin_mux_nand(void)
65 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
70 * Routine: power_det_init
71 * Description: turn off power detects
73 static void power_det_init(void)
75 #if defined(CONFIG_TEGRA20)
76 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
78 /* turn off power detects */
79 writel(0, &pmc->pmc_pwr_det_latch);
80 writel(0, &pmc->pmc_pwr_det);
84 #ifdef CONFIG_DISPLAY_BOARDINFO
87 printf("Board: %s\n", CONFIG_TEGRA_BOARD_STRING);
91 #endif /* CONFIG_DISPLAY_BOARDINFO */
95 * Description: Early hardware init.
99 __maybe_unused int err;
101 /* Do clocks and UART first so that printf() works */
105 #ifdef CONFIG_TEGRA_SPI
109 #ifdef CONFIG_PWM_TEGRA
110 if (pwm_init(gd->fdt_blob))
111 debug("%s: Failed to init pwm\n", __func__);
115 tegra_lcd_check_next_stage(gd->fdt_blob, 0);
117 /* boot param addr */
118 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
122 #ifdef CONFIG_SYS_I2C_TEGRA
123 # ifdef CONFIG_TEGRA_PMU
124 if (pmu_set_nominal())
125 debug("Failed to select nominal voltages\n");
126 # ifdef CONFIG_TEGRA_CLOCK_SCALING
127 err = board_emc_init();
129 debug("Memory controller init failed: %d\n", err);
131 # endif /* CONFIG_TEGRA_PMU */
132 #endif /* CONFIG_SYS_I2C_TEGRA */
134 #ifdef CONFIG_USB_EHCI_TEGRA
136 usb_process_devicetree(gd->fdt_blob);
140 tegra_lcd_check_next_stage(gd->fdt_blob, 0);
143 #ifdef CONFIG_TEGRA_NAND
147 tegra_xusb_padctl_init(gd->fdt_blob);
149 #ifdef CONFIG_TEGRA_LP0
150 /* save Sdram params to PMC 2, 4, and 24 for WB0 */
151 warmboot_save_sdram_params();
153 /* prepare the WB code to LP0 location */
154 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
160 #ifdef CONFIG_BOARD_EARLY_INIT_F
161 static void __gpio_early_init(void)
165 void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
167 int board_early_init_f(void)
172 /* Initialize periph GPIOs */
174 gpio_early_init_uart();
176 tegra_lcd_early_init(gd->fdt_blob);
181 #endif /* EARLY_INIT */
183 int board_late_init(void)
186 /* Make sure we finish initing the LCD */
187 tegra_lcd_check_next_stage(gd->fdt_blob, 1);
189 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
190 if (tegra_cpu_is_non_secure()) {
191 printf("CPU is in NS mode\n");
192 setenv("cpu_ns_mode", "1");
194 setenv("cpu_ns_mode", "");
200 #if defined(CONFIG_TEGRA_MMC)
201 __weak void pin_mux_mmc(void)
205 /* this is a weak define that we are overriding */
206 int board_mmc_init(bd_t *bd)
208 debug("%s called\n", __func__);
210 /* Enable muxes, etc. for SDMMC controllers */
213 debug("%s: init MMC\n", __func__);
219 void pad_init_mmc(struct mmc_host *host)
221 #if defined(CONFIG_TEGRA30)
222 enum periph_id id = host->mmc_id;
225 debug("%s: sdmmc address = %08x, id = %d\n", __func__,
226 (unsigned int)host->reg, id);
228 /* Set the pad drive strength for SDMMC1 or 3 only */
229 if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
230 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
235 val = readl(&host->reg->sdmemcmppadctl);
237 val |= MEMCOMP_PADCTRL_VREF;
238 writel(val, &host->reg->sdmemcmppadctl);
240 val = readl(&host->reg->autocalcfg);
242 val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
243 writel(val, &host->reg->autocalcfg);