2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/tegra2.h>
28 #include <asm/arch/sys_proto.h>
30 #include <asm/arch/clk_rst.h>
31 #include <asm/arch/clock.h>
32 #include <asm/arch/pinmux.h>
33 #include <asm/arch/uart.h>
36 #ifdef CONFIG_TEGRA2_MMC
40 DECLARE_GLOBAL_DATA_PTR;
42 const struct tegra2_sysinfo sysinfo = {
43 CONFIG_TEGRA2_BOARD_STRING
48 * Description: init the timestamp and lastinc value
55 static void enable_uart(enum periph_id pid)
57 /* Assert UART reset and enable clock */
58 reset_set_enable(pid, 1);
60 clock_ll_set_source(pid, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
65 /* De-assert reset to UART */
66 reset_set_enable(pid, 0);
70 * Routine: clock_init_uart
71 * Description: init the PLL and clock for the UART(s)
73 static void clock_init_uart(void)
75 #if defined(CONFIG_TEGRA2_ENABLE_UARTA)
76 enable_uart(PERIPH_ID_UART1);
77 #endif /* CONFIG_TEGRA2_ENABLE_UARTA */
78 #if defined(CONFIG_TEGRA2_ENABLE_UARTD)
79 enable_uart(PERIPH_ID_UART4);
80 #endif /* CONFIG_TEGRA2_ENABLE_UARTD */
84 * Routine: pin_mux_uart
85 * Description: setup the pin muxes/tristate values for the UART(s)
87 static void pin_mux_uart(void)
89 struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
92 #if defined(CONFIG_TEGRA2_ENABLE_UARTA)
93 reg = readl(&pmt->pmt_ctl_c);
94 reg &= 0xFFF0FFFF; /* IRRX_/IRTX_SEL [19:16] = 00 UARTA */
95 writel(reg, &pmt->pmt_ctl_c);
97 pinmux_tristate_disable(PINGRP_IRRX);
98 pinmux_tristate_disable(PINGRP_IRTX);
99 #endif /* CONFIG_TEGRA2_ENABLE_UARTA */
100 #if defined(CONFIG_TEGRA2_ENABLE_UARTD)
101 reg = readl(&pmt->pmt_ctl_b);
102 reg &= 0xFFFFFFF3; /* GMC_SEL [3:2] = 00, UARTD */
103 writel(reg, &pmt->pmt_ctl_b);
105 pinmux_tristate_disable(PINGRP_GMC);
106 #endif /* CONFIG_TEGRA2_ENABLE_UARTD */
109 #ifdef CONFIG_TEGRA2_MMC
111 * Routine: clock_init_mmc
112 * Description: init the PLL and clocks for the SDMMC controllers
114 static void clock_init_mmc(void)
116 clock_start_periph_pll(PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH, 20000000);
117 clock_start_periph_pll(PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH, 20000000);
121 * Routine: pin_mux_mmc
122 * Description: setup the pin muxes/tristate values for the SDMMC(s)
124 static void pin_mux_mmc(void)
126 struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
130 /* config 2, x8 on 2nd set of pins */
131 reg = readl(&pmt->pmt_ctl_a);
132 reg |= (3 << 16); /* ATB_SEL [17:16] = 11 SDIO4 */
133 writel(reg, &pmt->pmt_ctl_a);
134 reg = readl(&pmt->pmt_ctl_b);
135 reg |= (3 << 0); /* GMA_SEL [1:0] = 11 SDIO4 */
136 writel(reg, &pmt->pmt_ctl_b);
137 reg = readl(&pmt->pmt_ctl_d);
138 reg |= (3 << 0); /* GME_SEL [1:0] = 11 SDIO4 */
139 writel(reg, &pmt->pmt_ctl_d);
141 pinmux_tristate_disable(PINGRP_ATB);
142 pinmux_tristate_disable(PINGRP_GMA);
143 pinmux_tristate_disable(PINGRP_GME);
146 /* SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */
147 reg = readl(&pmt->pmt_ctl_d);
149 reg |= (2 << 10); /* SDB_SEL [11:10] = 01 SDIO3 */
150 reg |= (2 << 12); /* SDC_SEL [13:12] = 01 SDIO3 */
151 reg |= (2 << 14); /* SDD_SEL [15:14] = 01 SDIO3 */
152 writel(reg, &pmt->pmt_ctl_d);
154 pinmux_tristate_disable(PINGRP_SDC);
155 pinmux_tristate_disable(PINGRP_SDD);
156 pinmux_tristate_disable(PINGRP_SDB);
161 * Routine: board_init
162 * Description: Early hardware init.
169 /* boot param addr */
170 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
175 #ifdef CONFIG_TEGRA2_MMC
176 /* this is a weak define that we are overriding */
177 int board_mmc_init(bd_t *bd)
179 debug("board_mmc_init called\n");
180 /* Enable clocks, muxes, etc. for SDMMC controllers */
184 debug("board_mmc_init: init eMMC\n");
185 /* init dev 0, eMMC chip, with 4-bit bus */
186 tegra2_mmc_init(0, 4);
188 debug("board_mmc_init: init SD slot\n");
189 /* init dev 1, SD slot, with 4-bit bus */
190 tegra2_mmc_init(1, 4);
195 /* this is a weak define that we are overriding */
196 int board_mmc_getcd(u8 *cd, struct mmc *mmc)
198 debug("board_mmc_getcd called\n");
200 * Hard-code CD presence for now. Need to add GPIO inputs
201 * for Seaboard & Harmony (& Kaen/Aebl/Wario?)
208 #ifdef CONFIG_BOARD_EARLY_INIT_F
209 int board_early_init_f(void)
211 /* Initialize essential common plls */
214 /* Initialize UART clocks */
217 /* Initialize periph pinmuxes */
220 /* Initialize periph GPIOs */
223 /* Init UART, scratch regs, and start CPU */
227 #endif /* EARLY_INIT */