board/omap2420h4/omap2420h4.c

   1 /*
   2  * (C) Copyright 2004
   3  * Texas Instruments, <www.ti.com>
   4  * Richard Woodruff <r-woodruff2@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24 #include <common.h>
  25 #include <asm/arch/omap2420.h>
  26 #include <asm/io.h>
  27 #include <asm/arch/bits.h>
  28 #include <asm/arch/mux.h>
  29 #include <asm/arch/sys_proto.h>
  30 #include <asm/arch/sys_info.h>
  31 #include <asm/arch/mem.h>
  32 #include <i2c.h>
  33 #include <asm/mach-types.h>
  34 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
  35 #include <linux/mtd/nand.h>
  36 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
  37 #endif
  38
  39 static void wait_for_command_complete(unsigned int wd_base);
  40
  41 /*******************************************************
  42  * Routine: delay
  43  * Description: spinning delay to use before udelay works
  44  ******************************************************/
  45 static inline void delay (unsigned long loops)
  46 {
  47         __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
  48                 "bne 1b":"=r" (loops):"0" (loops));
  49 }
  50
  51 /*****************************************
  52  * Routine: board_init
  53  * Description: Early hardware init.
  54  *****************************************/
  55 int board_init (void)
  56 {
  57         DECLARE_GLOBAL_DATA_PTR;
  58
  59         gpmc_init(); /* in SRAM or SDRM, finish GPMC */
  60
  61         gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4;             /* board id for linux */
  62         gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0+0x100);     /* adress of boot parameters */
  63
  64         return 0;
  65 }
  66
  67 /**********************************************************
  68  * Routine: s_init
  69  * Description: Does early system init of muxing and clocks.
  70  * - Called path is with sram stack.
  71  **********************************************************/
  72 void s_init(void)
  73 {
  74         int in_sdram = running_in_sdram();
  75
  76         watchdog_init();
  77         set_muxconf_regs();
  78         delay(100);
  79
  80         if(!in_sdram)
  81                 prcm_init();
  82
  83         peripheral_enable();
  84         icache_enable();
  85         if (!in_sdram)
  86                 sdrc_init();
  87 }
  88
  89 /*******************************************************
  90  * Routine: misc_init_r
  91  * Description: Init ethernet (done here so udelay works)
  92  ********************************************************/
  93 int misc_init_r (void)
  94 {
  95         ether_init(); /* better done here so timers are init'ed */
  96         return(0);
  97 }
  98
  99 /****************************************
 100  * Routine: watchdog_init
 101  * Description: Shut down watch dogs
 102  *****************************************/
 103 void watchdog_init(void)
 104 {
 105         int mode;
 106         #define GP (BIT8|BIT9)
 107
 108         /* There are 4 watch dogs.  1 secure, and 3 general purpose.
 109          * I would expect that the ROM takes care of the secure one,
 110          * but we will try also.  Of the 3 GP ones, 1 can reset us
 111          * directly, the other 2 only generate MPU interrupts.
 112          */
 113         mode = (__raw_readl(CONTROL_STATUS) & (BIT8|BIT9));
 114         if (mode == GP) {
 115                 __raw_writel(WD_UNLOCK1 ,WD1_BASE+WSPR);
 116                 wait_for_command_complete(WD1_BASE);
 117                 __raw_writel(WD_UNLOCK2 ,WD1_BASE+WSPR);
 118         }
 119         __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
 120         wait_for_command_complete(WD2_BASE);
 121         __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);
 122
 123 #if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/
 124         __raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR);
 125         wait_for_command_complete(WD3_BASE);
 126         __raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR);
 127
 128         __raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR);
 129         wait_for_command_complete(WD4_BASE);
 130         __raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR);
 131 #endif
 132 }
 133
 134 /******************************************************
 135  * Routine: wait_for_command_complete
 136  * Description: Wait for posting to finish on watchdog
 137  ******************************************************/
 138 static void wait_for_command_complete(unsigned int wd_base)
 139 {
 140         int pending = 1;
 141         do {
 142                 pending = __raw_readl(wd_base+WWPS);
 143         } while (pending);
 144 }
 145
 146 /*******************************************************************
 147  * Routine:ether_init
 148  * Description: take the Ethernet controller out of reset and wait
 149  *                 for the EEPROM load to complete.
 150  ******************************************************************/
 151 void ether_init (void)
 152 {
 153 #ifdef CONFIG_DRIVER_LAN91C96
 154         int cnt = 20;
 155
 156         __raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */
 157
 158         __raw_writew(0x0, LAN_RESET_REGISTER);
 159         do {
 160                 __raw_writew(0x1, LAN_RESET_REGISTER);
 161                 udelay (100);
 162                 if (cnt == 0)
 163                         goto h4reset_err_out;
 164                 --cnt;
 165         } while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
 166
 167         cnt = 20;
 168
 169         do {
 170                 __raw_writew(0x0, LAN_RESET_REGISTER);
 171                 udelay (100);
 172                 if (cnt == 0)
 173                         goto h4reset_err_out;
 174                 --cnt;
 175         } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
 176         udelay (1000);
 177
 178         *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
 179         udelay (1000);
 180
 181         h4reset_err_out:
 182         return;
 183 #endif
 184 }
 185
 186 /**********************************************
 187  * Routine: dram_init
 188  * Description: sets uboots idea of sdram size
 189  **********************************************/
 190 int dram_init (void)
 191 {
 192         DECLARE_GLOBAL_DATA_PTR;
 193         unsigned int size0=0,size1=0;
 194         u32 mtype, btype;
 195         u8 chg_on = 0x5; /* enable charge of back up battery */
 196         u8 vmode_on = 0x8C;
 197         #define NOT_EARLY 0
 198
 199         i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); /* need this a bit early */
 200
 201         btype = get_board_type();
 202         mtype = get_mem_type();
 203
 204         display_board_info(btype);
 205         if (btype == BOARD_H4_MENELAUS){
 206                 update_mux(btype,mtype); /* combo part on menelaus */
 207                 i2c_write(I2C_MENELAUS, 0x20, 1, &chg_on, 1); /*fix POR reset bug */
 208                 i2c_write(I2C_MENELAUS, 0x2, 1, &vmode_on, 1); /* VCORE change on VMODE */
 209         }
 210
 211         if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
 212                 do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */
 213                 size0 = size1 = SZ_32M;
 214         } else if (mtype == SDR_DISCRETE)
 215                 size0 = SZ_128M;
 216         else
 217                 size0 = SZ_64M;
 218
 219         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 220         gd->bd->bi_dram[0].size = size0;
 221         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 222         gd->bd->bi_dram[1].size = size1;
 223
 224         return 0;
 225 }
 226
 227 /**********************************************************
 228  * Routine: set_muxconf_regs
 229  * Description: Setting up the configuration Mux registers
 230  *              specific to the hardware
 231  *********************************************************/
 232 void set_muxconf_regs (void)
 233 {
 234         muxSetupSDRC();
 235         muxSetupGPMC();
 236         muxSetupUsb0();
 237         muxSetupUart3();
 238         muxSetupI2C1();
 239         muxSetupUART1();
 240         muxSetupLCD();
 241         muxSetupCamera();
 242         muxSetupMMCSD();
 243         muxSetupTouchScreen();
 244         muxSetupHDQ();
 245 }
 246
 247 /*****************************************************************
 248  * Routine: peripheral_enable
 249  * Description: Enable the clks & power for perifs (GPT2, UART1,...)
 250  ******************************************************************/
 251 void peripheral_enable(void)
 252 {
 253         unsigned int v, if_clks=0, func_clks=0;
 254
 255         /* Enable GP2 timer.*/
 256         if_clks |= BIT4;
 257         func_clks |= BIT4;
 258         v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP2420_GPT2 */
 259         __raw_writel(v, CM_CLKSEL2_CORE);
 260         __raw_writel(0x1, CM_CLKSEL_WKUP);
 261
 262 #ifdef CFG_NS16550
 263         /* Enable UART1 clock */
 264         func_clks |= BIT21;
 265         if_clks |= BIT21;
 266 #endif
 267         v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;     /* Interface clocks on */
 268         __raw_writel(v,CM_ICLKEN1_CORE );
 269         v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
 270         __raw_writel(v, CM_FCLKEN1_CORE);
 271         delay(1000);
 272
 273 #ifndef KERNEL_UPDATED
 274         {
 275 #define V1 0xffffffff
 276 #define V2 0x00000007
 277
 278                 __raw_writel(V1, CM_FCLKEN1_CORE);
 279                 __raw_writel(V2, CM_FCLKEN2_CORE);
 280                 __raw_writel(V1, CM_ICLKEN1_CORE);
 281                 __raw_writel(V1, CM_ICLKEN2_CORE);
 282         }
 283 #endif
 284 }
 285
 286 /****************************************
 287  * Routine: muxSetupUsb0   (ostboot)
 288  * Description: Setup usb muxing
 289  *****************************************/
 290 void muxSetupUsb0(void)
 291 {
 292         volatile uint8   *MuxConfigReg;
 293         volatile uint32  *otgCtrlReg;
 294
 295         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN;
 296         *MuxConfigReg &= (uint8)(~0x1F);
 297
 298         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP;
 299         *MuxConfigReg &= (uint8)(~0x1F);
 300
 301         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM;
 302         *MuxConfigReg &= (uint8)(~0x1F);
 303
 304         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV;
 305         *MuxConfigReg &= (uint8)(~0x1F);
 306
 307         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN;
 308         *MuxConfigReg &= (uint8)(~0x1F);
 309
 310         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0;
 311         *MuxConfigReg &= (uint8)(~0x1F);
 312
 313         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT;
 314         *MuxConfigReg &= (uint8)(~0x1F);
 315
 316         /* setup for USB VBus detection */
 317         otgCtrlReg = (volatile uint32 *)USB_OTG_CTRL;
 318         *otgCtrlReg |= 0x00040000; /* bit 18 */
 319 }
 320
 321 /****************************************
 322  * Routine: muxSetupUart3   (ostboot)
 323  * Description: Setup uart3 muxing
 324  *****************************************/
 325 void muxSetupUart3(void)
 326 {
 327         volatile uint8 *MuxConfigReg;
 328
 329         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_TX_IRTX;
 330         *MuxConfigReg &= (uint8)(~0x1F);
 331
 332         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_RX_IRRX;
 333         *MuxConfigReg &= (uint8)(~0x1F);
 334 }
 335
 336 /****************************************
 337  * Routine: muxSetupI2C1   (ostboot)
 338  * Description: Setup i2c muxing
 339  *****************************************/
 340 void muxSetupI2C1(void)
 341 {
 342         volatile unsigned char  *MuxConfigReg;
 343
 344         /* I2C1 Clock pin configuration, PIN = M19 */
 345         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SCL;
 346         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 347
 348         /* I2C1 Data pin configuration, PIN = L15 */
 349         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SDA;
 350         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 351
 352         /* Pull-up required on data line */
 353         /* external pull-up already present. */
 354         /* *MuxConfigReg |= 0x18 ;*/ /* Mode = 0, PullTypeSel=PU, PullUDEnable=Enabled */
 355 }
 356
 357 /****************************************
 358  * Routine: muxSetupUART1  (ostboot)
 359  * Description: Set up uart1 muxing
 360  *****************************************/
 361 void muxSetupUART1(void)
 362 {
 363         volatile unsigned char  *MuxConfigReg;
 364
 365         /* UART1_CTS pin configuration, PIN = D21 */
 366         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS;
 367         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 368
 369         /* UART1_RTS pin configuration, PIN = H21 */
 370         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS;
 371         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 372
 373         /* UART1_TX pin configuration, PIN = L20 */
 374         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX;
 375         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 376
 377         /* UART1_RX pin configuration, PIN = T21 */
 378         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX;
 379         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 380 }
 381
 382 /****************************************
 383  * Routine: muxSetupLCD   (ostboot)
 384  * Description: Setup lcd muxing
 385  *****************************************/
 386 void muxSetupLCD(void)
 387 {
 388         volatile unsigned char  *MuxConfigReg;
 389
 390         /* LCD_D0 pin configuration, PIN = Y7  */
 391         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0;
 392         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 393
 394         /* LCD_D1 pin configuration, PIN = P10 */
 395         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1;
 396         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 397
 398         /* LCD_D2 pin configuration, PIN = V8  */
 399         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2;
 400         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 401
 402         /* LCD_D3 pin configuration, PIN = Y8  */
 403         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3;
 404         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 405
 406         /* LCD_D4 pin configuration, PIN = W8  */
 407         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4;
 408         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 409
 410         /* LCD_D5 pin configuration, PIN = R10 */
 411         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5;
 412         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 413
 414         /* LCD_D6 pin configuration, PIN = Y9  */
 415         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6;
 416         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 417
 418         /* LCD_D7 pin configuration, PIN = V9  */
 419         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7;
 420         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 421
 422         /* LCD_D8 pin configuration, PIN = W9  */
 423         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8;
 424         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 425
 426         /* LCD_D9 pin configuration, PIN = P11 */
 427         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9;
 428         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 429
 430         /* LCD_D10 pin configuration, PIN = V10 */
 431         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10;
 432         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 433
 434         /* LCD_D11 pin configuration, PIN = Y10 */
 435         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11;
 436         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 437
 438         /* LCD_D12 pin configuration, PIN = W10 */
 439         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12;
 440         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 441
 442         /* LCD_D13 pin configuration, PIN = R11 */
 443         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13;
 444         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 445
 446         /* LCD_D14 pin configuration, PIN = V11 */
 447         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14;
 448         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 449
 450         /* LCD_D15 pin configuration, PIN = W11 */
 451         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15;
 452         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 453
 454         /* LCD_D16 pin configuration, PIN = P12 */
 455         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16;
 456         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 457
 458         /* LCD_D17 pin configuration, PIN = R12 */
 459         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17;
 460         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 461
 462         /* LCD_PCLK pin configuration,   PIN = W6   */
 463         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK;
 464         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 465
 466         /* LCD_VSYNC pin configuration,  PIN = V7  */
 467         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC;
 468         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 469
 470         /* LCD_HSYNC pin configuration,  PIN = Y6  */
 471         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC;
 472         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 473
 474         /* LCD_ACBIAS pin configuration, PIN = W7 */
 475         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS;
 476         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 477 }
 478
 479 /****************************************
 480  * Routine: muxSetupCamera  (ostboot)
 481  * Description: Setup camera muxing
 482  *****************************************/
 483 void muxSetupCamera(void)
 484 {
 485         volatile unsigned char  *MuxConfigReg;
 486
 487         /* CAMERA_RSTZ  pin configuration, PIN = Y16 */
 488         /* CAM_RST is connected through the I2C IO expander.*/
 489         /* MuxConfigReg = (volatile unsigned char *), CONTROL_PADCONF_SYS_NRESWARM*/
 490         /* *MuxConfigReg = 0x00 ; / * Mode = 0, PUPD=Disabled   */
 491
 492         /* CAMERA_XCLK  pin configuration, PIN = U3 */
 493         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_XCLK;
 494         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 495
 496         /* CAMERA_LCLK  pin configuration, PIN = V5 */
 497         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_LCLK;
 498         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 499
 500         /* CAMERA_VSYNC pin configuration, PIN = U2 */
 501         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_VS,
 502                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 503
 504         /* CAMERA_HSYNC pin configuration, PIN = T3 */
 505         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_HS,
 506                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 507
 508         /* CAMERA_DAT0 pin configuration, PIN = T4 */
 509         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D0,
 510                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 511
 512         /* CAMERA_DAT1 pin configuration, PIN = V2 */
 513         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D1,
 514                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 515
 516         /* CAMERA_DAT2 pin configuration, PIN = V3 */
 517         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D2,
 518                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 519
 520         /* CAMERA_DAT3 pin configuration, PIN = U4 */
 521         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D3,
 522                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 523
 524         /* CAMERA_DAT4 pin configuration, PIN = W2 */
 525         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D4,
 526                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 527
 528         /* CAMERA_DAT5 pin configuration, PIN = V4 */
 529         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D5,
 530                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 531
 532         /* CAMERA_DAT6 pin configuration, PIN = W3 */
 533         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D6,
 534                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 535
 536         /* CAMERA_DAT7 pin configuration, PIN = Y2 */
 537         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D7,
 538                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 539
 540         /* CAMERA_DAT8 pin configuration, PIN = Y4 */
 541         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D8,
 542                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 543
 544         /* CAMERA_DAT9 pin configuration, PIN = V6 */
 545         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D9,
 546                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 547 }
 548
 549 /****************************************
 550  * Routine: muxSetupMMCSD (ostboot)
 551  * Description: set up MMC muxing
 552  *****************************************/
 553 void muxSetupMMCSD(void)
 554 {
 555         volatile unsigned char  *MuxConfigReg;
 556
 557         /* SDMMC_CLKI pin configuration,  PIN = H15 */
 558         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI,
 559                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 560
 561         /* SDMMC_CLKO pin configuration,  PIN = G19 */
 562         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO,
 563                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 564
 565         /* SDMMC_CMD pin configuration,   PIN = H18 */
 566         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD,
 567                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 568         /* External pull-ups are present. */
 569         /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 570
 571         /* SDMMC_DAT0 pin configuration,  PIN = F20 */
 572         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0,
 573                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 574         /* External pull-ups are present. */
 575         /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 576
 577         /* SDMMC_DAT1 pin configuration,  PIN = H14 */
 578         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1,
 579                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 580         /* External pull-ups are present. */
 581         /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 582
 583         /* SDMMC_DAT2 pin configuration,  PIN = E19 */
 584         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2,
 585                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 586         /* External pull-ups are present. */
 587         /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 588
 589         /* SDMMC_DAT3 pin configuration,  PIN = D19 */
 590         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3,
 591                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 592         /* External pull-ups are present. */
 593         /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 594
 595         /* SDMMC_DDIR0 pin configuration, PIN = F19 */
 596         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0,
 597                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 598
 599         /* SDMMC_DDIR1 pin configuration, PIN = E20 */
 600         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1,
 601                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 602
 603         /* SDMMC_DDIR2 pin configuration, PIN = F18 */
 604         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2,
 605                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 606
 607         /* SDMMC_DDIR3 pin configuration, PIN = E18 */
 608         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3,
 609                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 610
 611         /* SDMMC_CDIR pin configuration,  PIN = G18 */
 612         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR,
 613                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 614
 615         /* MMC_CD pin configuration,      PIN = B3  ---2420IP ONLY---*/
 616         /* MMC_CD for 2422IP=K1 */
 617         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A14,
 618                                    *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
 619
 620         /* MMC_WP pin configuration,      PIN = B4  */
 621         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A13,
 622                                    *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
 623 }
 624
 625 /******************************************
 626  * Routine: muxSetupTouchScreen (ostboot)
 627  * Description:  Set up touch screen muxing
 628  *******************************************/
 629 void muxSetupTouchScreen(void)
 630 {
 631         volatile unsigned char  *MuxConfigReg;
 632
 633         /* SPI1_CLK pin configuration,  PIN = U18 */
 634         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK,
 635                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 636
 637         /* SPI1_MOSI pin configuration, PIN = V20 */
 638         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO,
 639                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 640
 641         /* SPI1_MISO pin configuration, PIN = T18 */
 642         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI,
 643                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 644
 645         /* SPI1_nCS0 pin configuration, PIN = U19 */
 646         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0,
 647                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 648
 649         /* PEN_IRQ pin configuration,   PIN = P20 */
 650         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MCBSP1_FSR,
 651                                    *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
 652 }
 653
 654 /****************************************
 655  * Routine: muxSetupHDQ (ostboot)
 656  * Description: setup 1wire mux
 657  *****************************************/
 658 void muxSetupHDQ(void)
 659 {
 660         volatile unsigned char  *MuxConfigReg;
 661
 662         /* HDQ_SIO pin configuration,  PIN = N18 */
 663         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_HDQ_SIO,
 664                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 665 }
 666
 667 /***************************************************************
 668  * Routine: muxSetupGPMC (ostboot)
 669  * Description: Configures balls which cam up in protected mode
 670  ***************************************************************/
 671 void muxSetupGPMC(void)
 672 {
 673         volatile uint8 *MuxConfigReg;
 674         volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C;
 675
 676         /* gpmc_io_dir */
 677         *MCR = 0x19000000;
 678
 679         /* NOR FLASH CS0 */
 680         /* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode - 0; Byte-3       Pull/up - N/A */
 681         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3,
 682                                    *MuxConfigReg = 0x00 ;
 683
 684         /* signal - Gpmc_iodir; pin - n2; offset - 0x008C; mode - 1; Byte-3     Pull/up - N/A */
 685         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3,
 686                                    *MuxConfigReg = 0x01 ;
 687
 688         /* MPDB(Multi Port Debug Port) CS1 */
 689         /* signal - gpmc_ncs1; pin - N8; offset - 0x008C; mode - 0; Byte-1      Pull/up - N/A */
 690         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1,
 691                                    *MuxConfigReg = 0x00 ;
 692
 693         /* signal - Gpmc_ncs2; pin - E2; offset - 0x008C; mode - 0; Byte-2      Pull/up - N/A */
 694         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2,
 695                                    *MuxConfigReg = 0x00 ;
 696 }
 697
 698 /****************************************************************
 699  * Routine: muxSetupSDRC  (ostboot)
 700  * Description: Configures balls which come up in protected mode
 701  ****************************************************************/
 702 void muxSetupSDRC(void)
 703 {
 704         volatile uint8 *MuxConfigReg;
 705
 706         /* signal - sdrc_ncs1; pin - C12; offset - 0x00A0; mode - 0; Byte-1     Pull/up - N/A */
 707         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE1,
 708                                    *MuxConfigReg = 0x00 ;
 709
 710         /* signal - sdrc_a12; pin - D11; offset - 0x0030; mode - 0; Byte-2      Pull/up - N/A */
 711         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE2,
 712                                    *MuxConfigReg = 0x00 ;
 713
 714         /* signal - sdrc_cke1; pin - B13; offset - 0x00A0; mode - 0; Byte-3     Pull/up - N/A */
 715         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE3,
 716                                    *MuxConfigReg = 0x00;
 717
 718         if (get_cpu_type() == CPU_2422) {
 719                 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE0,
 720                                            *MuxConfigReg = 0x1b;
 721         }
 722 }
 723
 724 /*****************************************************************************
 725  * Routine: update_mux()
 726  * Description: Update balls which are different beween boards.  All should be
 727  *              updated to match functionaly.  However, I'm only updating ones
 728  *              which I'll be using for now.  When power comes into play they
 729  *              all need updating.
 730  *****************************************************************************/
 731 void update_mux(u32 btype,u32 mtype)
 732 {
 733         u32 cpu, base = OMAP2420_CTRL_BASE;
 734         cpu = get_cpu_type();
 735
 736         if (btype == BOARD_H4_MENELAUS) {
 737                 if (cpu == CPU_2420) {
 738                         /* PIN = B3,  GPIO.0->KBR5,      mode 3,  (pun?),-DO-*/
 739                         __raw_writeb(0x3, base+0x30);
 740                         /* PIN = B13, GPIO.38->KBC6,     mode 3,  (pun?)-DO-*/
 741                         __raw_writeb(0x3, base+0xa3);
 742                         /* PIN = F1, GPIO.25->HSUSBxx    mode 3,  (for external HS USB)*/
 743                         /* PIN = H1, GPIO.26->HSUSBxx    mode 3,  (for external HS USB)*/
 744                         /* PIN = K1, GPMC_ncs6           mode 0,  (on board nand access)*/
 745                         /* PIN = L2, GPMC_ncs67          mode 0,  (for external HS USB)*/
 746                         /* PIN = M1 (HSUSBOTG) */
 747                         /* PIN = P1, GPIO.35->MEN_POK    mode 3,  (menelaus powerok)-DO-*/
 748                         __raw_writeb(0x3, base+0x9d);
 749                         /* PIN = U32, (WLAN_CLKREQ) */
 750                         /* PIN = Y11, WLAN */
 751                         /* PIN = AA4, GPIO.15->KBC2,     mode 3,  -DO- */
 752                         __raw_writeb(0x3, base+0xe7);
 753                         /* PIN = AA8, mDOC */
 754                         /* PIN = AA10, BT */
 755                         /* PIN = AA13, WLAN */
 756                         /* PIN = M18 GPIO.96->MMC2_WP    mode 3   -DO- */
 757                         __raw_writeb(0x3, base+0x10e);
 758                         /* PIN = N19 GPIO.98->WLAN_INT   mode 3   -DO- */
 759                         __raw_writeb(0x3, base+0x110);
 760                         /* PIN = J15 HHUSB */
 761                         /* PIN = H19 HSUSB */
 762                         /* PIN = W13, P13, R13, W16 ... */
 763                         /* PIN = V12 GPIO.25->I2C_CAMEN  mode 3   -DO- */
 764                         __raw_writeb(0x3, base+0xde);
 765                         /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
 766                         __raw_writeb(0x0, base+0x12c);
 767                         /* PIN = AA17->sys_clkreq        mode 0   -DO- */
 768                         __raw_writeb(0x0, base+0x136);
 769                 } else if (cpu == CPU_2422) {
 770                         /* PIN = B3,  GPIO.0->nc,        mode 3,  set above (pun?)*/
 771                         /* PIN = B13, GPIO.cke1->nc,     mode 0,  set above, (pun?)*/
 772                         /* PIN = F1, GPIO.25->HSUSBxx    mode 3,  (for external HS USB)*/
 773                         /* PIN = H1, GPIO.26->HSUSBxx    mode 3,  (for external HS USB)*/
 774                         /* PIN = K1, GPMC_ncs6           mode 0,  (on board nand access)*/
 775                         __raw_writeb(0x0, base+0x92);
 776                         /* PIN = L2, GPMC_ncs67          mode 0,  (for external HS USB)*/
 777                         /* PIN = M1 (HSUSBOTG) */
 778                         /* PIN = P1, GPIO.35->MEN_POK    mode 3,  (menelaus powerok)-DO-*/
 779                         __raw_writeb(0x3, base+0x10c);
 780                         /* PIN = U32, (WLAN_CLKREQ) */
 781                         /* PIN = AA4, GPIO.15->KBC2,     mode 3,  -DO- */
 782                         __raw_writeb(0x3, base+0x30);
 783                         /* PIN = AA8, mDOC */
 784                         /* PIN = AA10, BT */
 785                         /* PIN = AA12, WLAN */
 786                         /* PIN = M18 GPIO.96->MMC2_WP    mode 3   -DO- */
 787                         __raw_writeb(0x3, base+0x10e);
 788                         /* PIN = N19 GPIO.98->WLAN_INT   mode 3   -DO- */
 789                         __raw_writeb(0x3, base+0x110);
 790                         /* PIN = J15 HHUSB */
 791                         /* PIN = H19 HSUSB */
 792                         /* PIN = W13, P13, R13, W16 ... */
 793                         /* PIN = V12 GPIO.25->I2C_CAMEN  mode 3   -DO- */
 794                         __raw_writeb(0x3, base+0xde);
 795                         /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
 796                         __raw_writeb(0x0, base+0x12c);
 797                         /* PIN = AA17->sys_clkreq        mode 0   -DO- */
 798                         __raw_writeb(0x0, base+0x136);
 799                 }
 800
 801         } else if (btype == BOARD_H4_SDP) {
 802                 if (cpu == CPU_2420) {
 803                         /* PIN = B3,  GPIO.0->nc         mode 3,  set above (pun?)*/
 804                         /* PIN = B13, GPIO.cke1->nc,     mode 0,  set above, (pun?)*/
 805                         /* Pin = Y11 VLNQ */
 806                         /* Pin = AA4 VLNQ */
 807                         /* Pin = AA6 VLNQ */
 808                         /* Pin = AA8 VLNQ */
 809                         /* Pin = AA10 VLNQ */
 810                         /* Pin = AA12 VLNQ */
 811                         /* PIN = M18 GPIO.96->KBR5       mode 3   -DO- */
 812                         __raw_writeb(0x3, base+0x10e);
 813                         /* PIN = N19 GPIO.98->KBC6       mode 3   -DO- */
 814                         __raw_writeb(0x3, base+0x110);
 815                         /* PIN = J15 MDOC_nDMAREQ */
 816                         /* PIN = H19 GPIO.100->KBC2      mode 3   -DO- */
 817                         __raw_writeb(0x3, base+0x114);
 818                         /* PIN = W13, V12, P13, R13, W19, W16 ... */
 819                         /* PIN = AA17 sys_clkreq->bt_clk_req  mode 0  */
 820                 } else if (cpu == CPU_2422) {
 821                         /* PIN = B3,  GPIO.0->MMC_CD,    mode 3,  set above */
 822                         /* PIN = B13, GPIO.38->wlan_int, mode 3,  (pun?)*/
 823                         /* Pin = Y11 VLNQ */
 824                         /* Pin = AA4 VLNQ */
 825                         /* Pin = AA6 VLNQ */
 826                         /* Pin = AA8 VLNQ */
 827                         /* Pin = AA10 VLNQ */
 828                         /* Pin = AA12 VLNQ */
 829                         /* PIN = M18 GPIO.96->KBR5       mode 3   -DO- */
 830                         __raw_writeb(0x3, base+0x10e);
 831                         /* PIN = N19 GPIO.98->KBC6       mode 3   -DO- */
 832                         __raw_writeb(0x3, base+0x110);
 833                         /* PIN = J15 MDOC_nDMAREQ */
 834                         /* PIN = H19 GPIO.100->KBC2      mode 3   -DO- */
 835                         __raw_writeb(0x3, base+0x114);
 836                         /* PIN = W13, V12, P13, R13, W19, W16 ... */
 837                         /* PIN = AA17 sys_clkreq->bt_clk_req  mode 0 */
 838                 }
 839         }
 840 }
 841
 842 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 843 void nand_init(void)
 844 {
 845     extern flash_info_t flash_info[];
 846
 847     nand_probe(CFG_NAND_ADDR);
 848     if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
 849                 print_size(nand_dev_desc[0].totlen, "\n");
 850     }
 851
 852 #ifdef CFG_JFFS2_MEM_NAND
 853     flash_info[CFG_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id;
 854     flash_info[CFG_JFFS2_FIRST_BANK].size = 1024*1024*2;      /* only read kernel single meg partition */
 855         flash_info[CFG_JFFS2_FIRST_BANK].sector_count = 1024;   /* 1024 blocks in 16meg chip (use less for raw/copied partition) */
 856     flash_info[CFG_JFFS2_FIRST_BANK].start[0] = 0x80200000; /* ?, ram for now, open question, copy to RAM or adapt for NAND */
 857 #endif
 858 }
 859 #endif