board/renesas/lager/lager.c

   1 /*
   2  * board/renesas/lager/lager.c
   3  *     This file is lager board support.
   4  *
   5  * Copyright (C) 2013 Renesas Electronics Corporation
   6  * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
   7  *
   8  * SPDX-License-Identifier: GPL-2.0
   9  */
  10
  11 #include <common.h>
  12 #include <malloc.h>
  13 #include <netdev.h>
  14 #include <asm/processor.h>
  15 #include <asm/mach-types.h>
  16 #include <asm/io.h>
  17 #include <asm/errno.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/gpio.h>
  20 #include <asm/arch/rmobile.h>
  21 #include <miiphy.h>
  22 #include "qos.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #define s_init_wait(cnt) \
  27         ({      \
  28                 u32 i = 0x10000 * cnt;  \
  29                 while (i > 0)   \
  30                         i--;    \
  31         })
  32
  33 #define dbpdrgd_check(bsc) \
  34         ({      \
  35                 while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1)     \
  36                         ;       \
  37         })
  38
  39 #if defined(CONFIG_NORFLASH)
  40 static void bsc_init(void)
  41 {
  42         struct r8a7790_lbsc *lbsc = (struct r8a7790_lbsc *)LBSC_BASE;
  43         struct r8a7790_dbsc3 *dbsc3_0 = (struct r8a7790_dbsc3 *)DBSC3_0_BASE;
  44
  45         /* LBSC */
  46         writel(0x00000020, &lbsc->cs0ctrl);
  47         writel(0x00000020, &lbsc->cs1ctrl);
  48         writel(0x00002020, &lbsc->ecs0ctrl);
  49         writel(0x00002020, &lbsc->ecs1ctrl);
  50
  51         writel(0x077F077F, &lbsc->cswcr0);
  52         writel(0x077F077F, &lbsc->cswcr1);
  53         writel(0x077F077F, &lbsc->ecswcr0);
  54         writel(0x077F077F, &lbsc->ecswcr1);
  55
  56         /* DBSC3 */
  57         s_init_wait(10);
  58
  59         writel(0x0000A55A, &dbsc3_0->dbpdlck);
  60         writel(0x00000001, &dbsc3_0->dbpdrga);
  61         writel(0x80000000, &dbsc3_0->dbpdrgd);
  62         writel(0x00000004, &dbsc3_0->dbpdrga);
  63         dbpdrgd_check(dbsc3_0);
  64
  65         writel(0x00000006, &dbsc3_0->dbpdrga);
  66         writel(0x0001C000, &dbsc3_0->dbpdrgd);
  67
  68         writel(0x00000023, &dbsc3_0->dbpdrga);
  69         writel(0x00FD2480, &dbsc3_0->dbpdrgd);
  70
  71         writel(0x00000010, &dbsc3_0->dbpdrga);
  72         writel(0xF004649B, &dbsc3_0->dbpdrgd);
  73
  74         writel(0x0000000F, &dbsc3_0->dbpdrga);
  75         writel(0x00181EE4, &dbsc3_0->dbpdrgd);
  76
  77         writel(0x0000000E, &dbsc3_0->dbpdrga);
  78         writel(0x33C03812, &dbsc3_0->dbpdrgd);
  79
  80         writel(0x00000003, &dbsc3_0->dbpdrga);
  81         writel(0x0300C481, &dbsc3_0->dbpdrgd);
  82
  83         writel(0x00000007, &dbsc3_0->dbkind);
  84         writel(0x10030A02, &dbsc3_0->dbconf0);
  85         writel(0x00000001, &dbsc3_0->dbphytype);
  86         writel(0x00000000, &dbsc3_0->dbbl);
  87         writel(0x0000000B, &dbsc3_0->dbtr0);
  88         writel(0x00000008, &dbsc3_0->dbtr1);
  89         writel(0x00000000, &dbsc3_0->dbtr2);
  90         writel(0x0000000B, &dbsc3_0->dbtr3);
  91         writel(0x000C000B, &dbsc3_0->dbtr4);
  92         writel(0x00000027, &dbsc3_0->dbtr5);
  93         writel(0x0000001C, &dbsc3_0->dbtr6);
  94         writel(0x00000005, &dbsc3_0->dbtr7);
  95         writel(0x00000018, &dbsc3_0->dbtr8);
  96         writel(0x00000008, &dbsc3_0->dbtr9);
  97         writel(0x0000000C, &dbsc3_0->dbtr10);
  98         writel(0x00000009, &dbsc3_0->dbtr11);
  99         writel(0x00000012, &dbsc3_0->dbtr12);
 100         writel(0x000000D0, &dbsc3_0->dbtr13);
 101         writel(0x00140005, &dbsc3_0->dbtr14);
 102         writel(0x00050004, &dbsc3_0->dbtr15);
 103         writel(0x70233005, &dbsc3_0->dbtr16);
 104         writel(0x000C0000, &dbsc3_0->dbtr17);
 105         writel(0x00000300, &dbsc3_0->dbtr18);
 106         writel(0x00000040, &dbsc3_0->dbtr19);
 107         writel(0x00000001, &dbsc3_0->dbrnk0);
 108         writel(0x00020001, &dbsc3_0->dbadj0);
 109         writel(0x20082008, &dbsc3_0->dbadj2);
 110         writel(0x00020002, &dbsc3_0->dbwt0cnf0);
 111         writel(0x0000000F, &dbsc3_0->dbwt0cnf4);
 112
 113         writel(0x00000015, &dbsc3_0->dbpdrga);
 114         writel(0x00000D70, &dbsc3_0->dbpdrgd);
 115
 116         writel(0x00000016, &dbsc3_0->dbpdrga);
 117         writel(0x00000006, &dbsc3_0->dbpdrgd);
 118
 119         writel(0x00000017, &dbsc3_0->dbpdrga);
 120         writel(0x00000018, &dbsc3_0->dbpdrgd);
 121
 122         writel(0x00000012, &dbsc3_0->dbpdrga);
 123         writel(0x9D5CBB66, &dbsc3_0->dbpdrgd);
 124
 125         writel(0x00000013, &dbsc3_0->dbpdrga);
 126         writel(0x1A868300, &dbsc3_0->dbpdrgd);
 127
 128         writel(0x00000023, &dbsc3_0->dbpdrga);
 129         writel(0x00FDB6C0, &dbsc3_0->dbpdrgd);
 130
 131         writel(0x00000014, &dbsc3_0->dbpdrga);
 132         writel(0x300214D8, &dbsc3_0->dbpdrgd);
 133
 134         writel(0x0000001A, &dbsc3_0->dbpdrga);
 135         writel(0x930035C7, &dbsc3_0->dbpdrgd);
 136
 137         writel(0x00000060, &dbsc3_0->dbpdrga);
 138         writel(0x330657B2, &dbsc3_0->dbpdrgd);
 139
 140         writel(0x00000011, &dbsc3_0->dbpdrga);
 141         writel(0x1000040B, &dbsc3_0->dbpdrgd);
 142
 143         writel(0x0000FA00, &dbsc3_0->dbcmd);
 144         writel(0x00000001, &dbsc3_0->dbpdrga);
 145         writel(0x00000071, &dbsc3_0->dbpdrgd);
 146
 147         writel(0x00000004, &dbsc3_0->dbpdrga);
 148         dbpdrgd_check(dbsc3_0);
 149
 150         writel(0x0000FA00, &dbsc3_0->dbcmd);
 151         writel(0x2100FA00, &dbsc3_0->dbcmd);
 152         writel(0x0000FA00, &dbsc3_0->dbcmd);
 153         writel(0x0000FA00, &dbsc3_0->dbcmd);
 154         writel(0x0000FA00, &dbsc3_0->dbcmd);
 155         writel(0x0000FA00, &dbsc3_0->dbcmd);
 156         writel(0x0000FA00, &dbsc3_0->dbcmd);
 157         writel(0x0000FA00, &dbsc3_0->dbcmd);
 158         writel(0x0000FA00, &dbsc3_0->dbcmd);
 159
 160         writel(0x110000DB, &dbsc3_0->dbcmd);
 161
 162         writel(0x00000001, &dbsc3_0->dbpdrga);
 163         writel(0x00000181, &dbsc3_0->dbpdrgd);
 164
 165         writel(0x00000004, &dbsc3_0->dbpdrga);
 166         dbpdrgd_check(dbsc3_0);
 167
 168         writel(0x00000001, &dbsc3_0->dbpdrga);
 169         writel(0x0000FE01, &dbsc3_0->dbpdrgd);
 170
 171         writel(0x00000004, &dbsc3_0->dbpdrga);
 172         dbpdrgd_check(dbsc3_0);
 173
 174         writel(0x00000000, &dbsc3_0->dbbs0cnt1);
 175         writel(0x01004C20, &dbsc3_0->dbcalcnf);
 176         writel(0x014000AA, &dbsc3_0->dbcaltr);
 177         writel(0x00000140, &dbsc3_0->dbrfcnf0);
 178         writel(0x00081860, &dbsc3_0->dbrfcnf1);
 179         writel(0x00010000, &dbsc3_0->dbrfcnf2);
 180         writel(0x00000001, &dbsc3_0->dbrfen);
 181         writel(0x00000001, &dbsc3_0->dbacen);
 182 }
 183 #else
 184 #define bsc_init() do {} while (0)
 185 #endif /* CONFIG_NORFLASH */
 186
 187 void s_init(void)
 188 {
 189         struct r8a7790_rwdt *rwdt = (struct r8a7790_rwdt *)RWDT_BASE;
 190         struct r8a7790_swdt *swdt = (struct r8a7790_swdt *)SWDT_BASE;
 191
 192         /* Watchdog init */
 193         writel(0xA5A5A500, &rwdt->rwtcsra);
 194         writel(0xA5A5A500, &swdt->swtcsra);
 195
 196         /* QoS(Quality-of-Service) Init */
 197         qos_init();
 198
 199         /* BSC init */
 200         bsc_init();
 201 }
 202
 203 #define MSTPSR1 0xE6150038
 204 #define SMSTPCR1        0xE6150134
 205 #define TMU0_MSTP125    (1 << 25)
 206
 207 #define MSTPSR7 0xE61501C4
 208 #define SMSTPCR7        0xE615014C
 209 #define SCIF0_MSTP721   (1 << 21)
 210
 211 #define MSTPSR8 0xE61509A0
 212 #define SMSTPCR8        0xE6150990
 213 #define ETHER_MSTP813   (1 << 13)
 214
 215 #define PMMR    0xE6060000
 216 #define GPSR4   0xE6060014
 217 #define IPSR14  0xE6060058
 218
 219 #define set_guard_reg(addr, mask, value)        \
 220 { \
 221         u32     val; \
 222         val = (readl(addr) & ~(mask)) | (value);        \
 223         writel(~val, PMMR);     \
 224         writel(val, addr);      \
 225 }
 226
 227 #define mstp_setbits(type, addr, saddr, set) \
 228         out_##type((saddr), in_##type(addr) | (set))
 229 #define mstp_clrbits(type, addr, saddr, clear) \
 230         out_##type((saddr), in_##type(addr) & ~(clear))
 231 #define mstp_setbits_le32(addr, saddr, set)     \
 232                 mstp_setbits(le32, addr, saddr, set)
 233 #define mstp_clrbits_le32(addr, saddr, clear)   \
 234                 mstp_clrbits(le32, addr, saddr, clear)
 235
 236 int board_early_init_f(void)
 237 {
 238         /* TMU0 */
 239         mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
 240
 241 #if defined(CONFIG_NORFLASH)
 242         /* SCIF0 */
 243         set_guard_reg(GPSR4, 0x34000000, 0x00000000);
 244         set_guard_reg(IPSR14, 0x00000FC7, 0x00000481);
 245         set_guard_reg(GPSR4,  0x00000000, 0x34000000);
 246 #endif
 247
 248         mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
 249
 250         /* ETHER */
 251         mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
 252
 253         return 0;
 254 }
 255
 256 DECLARE_GLOBAL_DATA_PTR;
 257 int board_init(void)
 258 {
 259         /* board id for linux */
 260         gd->bd->bi_arch_number = MACH_TYPE_LAGER;
 261         /* adress of boot parameters */
 262         gd->bd->bi_boot_params = LAGER_SDRAM_BASE + 0x100;
 263
 264         /* Init PFC controller */
 265         r8a7790_pinmux_init();
 266
 267         /* ETHER Enable */
 268         gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
 269         gpio_request(GPIO_FN_ETH_RX_ER, NULL);
 270         gpio_request(GPIO_FN_ETH_RXD0, NULL);
 271         gpio_request(GPIO_FN_ETH_RXD1, NULL);
 272         gpio_request(GPIO_FN_ETH_LINK, NULL);
 273         gpio_request(GPIO_FN_ETH_REF_CLK, NULL);
 274         gpio_request(GPIO_FN_ETH_MDIO, NULL);
 275         gpio_request(GPIO_FN_ETH_TXD1, NULL);
 276         gpio_request(GPIO_FN_ETH_TX_EN, NULL);
 277         gpio_request(GPIO_FN_ETH_MAGIC, NULL);
 278         gpio_request(GPIO_FN_ETH_TXD0, NULL);
 279         gpio_request(GPIO_FN_ETH_MDC, NULL);
 280         gpio_request(GPIO_FN_IRQ0, NULL);
 281
 282         gpio_request(GPIO_GP_5_31, NULL);       /* PHY_RST */
 283         gpio_direction_output(GPIO_GP_5_31, 0);
 284         mdelay(20);
 285         gpio_set_value(GPIO_GP_5_31, 1);
 286         udelay(1);
 287
 288         return 0;
 289 }
 290
 291 #define CXR24 0xEE7003C0 /* MAC address high register */
 292 #define CXR25 0xEE7003C8 /* MAC address low register */
 293 int board_eth_init(bd_t *bis)
 294 {
 295         int ret = -ENODEV;
 296
 297 #ifdef CONFIG_SH_ETHER
 298         u32 val;
 299         unsigned char enetaddr[6];
 300
 301         ret = sh_eth_initialize(bis);
 302         if (!eth_getenv_enetaddr("ethaddr", enetaddr))
 303                 return ret;
 304
 305         /* Set Mac address */
 306         val = enetaddr[0] << 24 | enetaddr[1] << 16 |
 307             enetaddr[2] << 8 | enetaddr[3];
 308         writel(val, CXR24);
 309
 310         val = enetaddr[4] << 8 | enetaddr[5];
 311         writel(val, CXR25);
 312
 313 #endif
 314
 315         return ret;
 316 }
 317
 318 /* lager has KSZ8041NL/RNL */
 319 #define PHY_CONTROL1    0x1E
 320 #define PHY_LED_MODE    0xC0000
 321 #define PHY_LED_MODE_ACK        0x4000
 322 int board_phy_config(struct phy_device *phydev)
 323 {
 324         int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
 325         ret &= ~PHY_LED_MODE;
 326         ret |= PHY_LED_MODE_ACK;
 327         ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
 328
 329         return 0;
 330 }
 331
 332 int dram_init(void)
 333 {
 334         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 335         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 336
 337         return 0;
 338 }
 339
 340 const struct rmobile_sysinfo sysinfo = {
 341         CONFIG_RMOBILE_BOARD_STRING
 342 };
 343
 344 void dram_init_banksize(void)
 345 {
 346         gd->bd->bi_dram[0].start = LAGER_SDRAM_BASE;
 347         gd->bd->bi_dram[0].size = LAGER_SDRAM_SIZE;
 348 }
 349
 350 int board_late_init(void)
 351 {
 352         return 0;
 353 }
 354
 355 void reset_cpu(ulong addr)
 356 {
 357 }