board/renesas/r0p7734/lowlevel_init.S

   1 /*
   2  * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
   3  * Copyright (C) 2011 Renesas Solutions Corp.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20 #include <config.h>
  21 #include <version.h>
  22 #include <asm/processor.h>
  23 #include <asm/macro.h>
  24
  25 #include <asm/processor.h>
  26
  27         .global lowlevel_init
  28
  29         .text
  30         .align  2
  31
  32 lowlevel_init:
  33
  34         /* WDT */
  35         write32 WDTCSR_A, WDTCSR_D
  36
  37         /* MMU */
  38         write32 MMUCR_A, MMUCR_D
  39
  40         write32 FRQCR2_A, FRQCR2_D
  41         write32 FRQCR0_A, FRQCR0_D
  42
  43         write32 CS0CTRL_A, CS0CTRL_D
  44         write32 CS1CTRL_A, CS1CTRL_D
  45         write32 CS0CTRL2_A, CS0CTRL2_D
  46
  47         write32 CSPWCR0_A, CSPWCR0_D
  48         write32 CSPWCR1_A, CSPWCR1_D
  49         write32 CS1GDST_A, CS1GDST_D
  50
  51         # clock mode check
  52         mov.l   MODEMR, r1
  53         mov.l   @r1, r0
  54         and             #6, r0 /* Check 1 and 2 bit.*/
  55         cmp/eq  #2, r0 /* 0x02 is 533Mhz mode */
  56         bt      init_lbsc_533
  57
  58 init_lbsc_400:
  59
  60         write32 CSWCR0_A, CSWCR0_D_400
  61         write32 CSWCR1_A, CSWCR1_D
  62
  63         bra     init_dbsc3_400_pad
  64         nop
  65
  66         .align 2
  67
  68 MODEMR:         .long   0xFFCC0020
  69 WDTCSR_A:       .long   0xFFCC0004
  70 WDTCSR_D:       .long   0xA5000000
  71 MMUCR_A:        .long   0xFF000010
  72 MMUCR_D:        .long   0x00000004
  73
  74 FRQCR2_A:       .long   0xFFC80008
  75 FRQCR2_D:       .long   0x00000000
  76 FRQCR0_A:       .long   0xFFC80000
  77 FRQCR0_D:       .long   0xCF000001
  78
  79 CS0CTRL_A:      .long   0xFF800200
  80 CS0CTRL_D:      .long   0x00000020
  81 CS1CTRL_A:      .long   0xFF800204
  82 CS1CTRL_D:      .long   0x00000020
  83
  84 CS0CTRL2_A:     .long   0xFF800220
  85 CS0CTRL2_D:     .long   0x00004000
  86
  87 CSPWCR0_A:      .long   0xFF800280
  88 CSPWCR0_D:      .long   0x00000000
  89 CSPWCR1_A:      .long   0xFF800284
  90 CSPWCR1_D:      .long   0x00000000
  91 CS1GDST_A:      .long   0xFF8002C0
  92 CS1GDST_D:      .long   0x00000011
  93
  94 init_lbsc_533:
  95
  96         write32 CSWCR0_A, CSWCR0_D_533
  97         write32 CSWCR1_A, CSWCR1_D
  98
  99         bra     init_dbsc3_533_pad
 100         nop
 101
 102         .align 2
 103
 104 CSWCR0_A:       .long   0xFF800230
 105 CSWCR0_D_533:   .long   0x01120104
 106 CSWCR0_D_400:   .long   0x02120114
 107 /* CSWCR0_D_400:        .long   0x01160116 */
 108 CSWCR1_A:       .long   0xFF800234
 109 CSWCR1_D:       .long   0x077F077F
 110 /* CSWCR1_D_400:        .long   0x00120012 */
 111
 112 init_dbsc3_400_pad:
 113
 114         write32 DBPDCNT3_A,     DBPDCNT3_D
 115         wait_timer      WAIT_200US_400
 116
 117         write32 DBPDCNT0_A,     DBPDCNT0_D_400
 118         write32 DBPDCNT3_A,     DBPDCNT3_D0
 119         write32 DBPDCNT1_A,     DBPDCNT1_D
 120
 121         write32 DBPDCNT3_A,     DBPDCNT3_D1
 122         wait_timer WAIT_32MCLK
 123
 124         write32 DBPDCNT3_A,     DBPDCNT3_D2
 125         wait_timer WAIT_100US_400
 126
 127         write32 DBPDCNT3_A,     DBPDCNT3_D3
 128         wait_timer WAIT_16MCLK
 129
 130         write32 DBPDCNT3_A,     DBPDCNT3_D4
 131         wait_timer WAIT_200US_400
 132
 133         write32 DBPDCNT3_A,     DBPDCNT3_D5
 134         wait_timer WAIT_1MCLK
 135
 136         write32 DBPDCNT3_A,     DBPDCNT3_D6
 137         wait_timer WAIT_10KMCLK
 138
 139         bra init_dbsc3_ctrl_400
 140         nop
 141
 142         .align 2
 143
 144 init_dbsc3_533_pad:
 145
 146         write32 DBPDCNT3_A,     DBPDCNT3_D
 147         wait_timer      WAIT_200US_533
 148
 149         write32 DBPDCNT0_A,     DBPDCNT0_D_533
 150         write32 DBPDCNT3_A,     DBPDCNT3_D0
 151         write32 DBPDCNT1_A,     DBPDCNT1_D
 152
 153         write32 DBPDCNT3_A,     DBPDCNT3_D1
 154         wait_timer WAIT_32MCLK
 155
 156         write32 DBPDCNT3_A,     DBPDCNT3_D2
 157         wait_timer WAIT_100US_533
 158
 159         write32 DBPDCNT3_A,     DBPDCNT3_D3
 160         wait_timer WAIT_16MCLK
 161
 162         write32 DBPDCNT3_A,     DBPDCNT3_D4
 163         wait_timer WAIT_200US_533
 164
 165         write32 DBPDCNT3_A,     DBPDCNT3_D5
 166         wait_timer WAIT_1MCLK
 167
 168         write32 DBPDCNT3_A,     DBPDCNT3_D6
 169         wait_timer      WAIT_10KMCLK
 170
 171         bra init_dbsc3_ctrl_533
 172         nop
 173
 174         .align 2
 175
 176 WAIT_200US_400: .long   40000
 177 WAIT_200US_533: .long   53300
 178 WAIT_100US_400: .long   20000
 179 WAIT_100US_533: .long   26650
 180 WAIT_32MCLK:    .long   32
 181 WAIT_16MCLK:    .long   16
 182 WAIT_1MCLK:             .long   1
 183 WAIT_10KMCLK:   .long   10000
 184
 185 DBPDCNT0_A:             .long   0xFE800200
 186 DBPDCNT0_D_533: .long   0x00010245
 187 DBPDCNT0_D_400: .long   0x00010235
 188 DBPDCNT1_A:             .long   0xFE800204
 189 DBPDCNT1_D:             .long   0x00000014
 190 DBPDCNT3_A:             .long   0xFE80020C
 191 DBPDCNT3_D:             .long   0x80000000
 192 DBPDCNT3_D0:    .long   0x800F0000
 193 DBPDCNT3_D1:    .long   0x800F1000
 194 DBPDCNT3_D2:    .long   0x820F1000
 195 DBPDCNT3_D3:    .long   0x860F1000
 196 DBPDCNT3_D4:    .long   0x870F1000
 197 DBPDCNT3_D5:    .long   0x870F3000
 198 DBPDCNT3_D6:    .long   0x870F7000
 199
 200 init_dbsc3_ctrl_400:
 201
 202         write32 DBKIND_A, DBKIND_D
 203         write32 DBCONF_A, DBCONF_D
 204
 205         write32 DBTR0_A,        DBTR0_D_400
 206         write32 DBTR1_A,        DBTR1_D_400
 207         write32 DBTR2_A,        DBTR2_D
 208         write32 DBTR3_A,        DBTR3_D_400
 209         write32 DBTR4_A,        DBTR4_D_400
 210         write32 DBTR5_A,        DBTR5_D_400
 211         write32 DBTR6_A,        DBTR6_D_400
 212         write32 DBTR7_A,        DBTR7_D
 213         write32 DBTR8_A,        DBTR8_D_400
 214         write32 DBTR9_A,        DBTR9_D
 215         write32 DBTR10_A,       DBTR10_D_400
 216         write32 DBTR11_A,       DBTR11_D
 217         write32 DBTR12_A,       DBTR12_D_400
 218         write32 DBTR13_A,       DBTR13_D_400
 219         write32 DBTR14_A,       DBTR14_D
 220         write32 DBTR15_A,       DBTR15_D
 221         write32 DBTR16_A,       DBTR16_D_400
 222         write32 DBTR17_A,       DBTR17_D_400
 223         write32 DBTR18_A,       DBTR18_D_400
 224
 225         write32 DBBL_A, DBBL_D
 226         write32 DBRNK0_A,       DBRNK0_D
 227
 228         write32 DBCMD_A,        DBCMD_D0_400
 229         write32 DBCMD_A,        DBCMD_D1
 230         write32 DBCMD_A,        DBCMD_D2
 231         write32 DBCMD_A,        DBCMD_D3
 232         write32 DBCMD_A,        DBCMD_D4
 233         write32 DBCMD_A,        DBCMD_D5_400
 234         write32 DBCMD_A,        DBCMD_D6
 235         write32 DBCMD_A,        DBCMD_D7
 236         write32 DBCMD_A,        DBCMD_D8
 237         write32 DBCMD_A,        DBCMD_D9_400
 238         write32 DBCMD_A,        DBCMD_D10
 239         write32 DBCMD_A,        DBCMD_D11
 240         write32 DBCMD_A,        DBCMD_D12
 241
 242         write32 DBBS0CNT1_A,    DBBS0CNT1_D
 243         write32 DBPDNCNF_A,             DBPDNCNF_D
 244
 245         write32 DBRFCNF0_A,     DBRFCNF0_D
 246         write32 DBRFCNF1_A,     DBRFCNF1_D_400
 247         write32 DBRFCNF2_A,     DBRFCNF2_D
 248         write32 DBRFEN_A,       DBRFEN_D
 249         write32 DBACEN_A,       DBACEN_D
 250         write32 DBACEN_A,       DBACEN_D
 251
 252         /* Dummy read */
 253         mov.l DBWAIT_A, r1
 254         synco
 255         mov.l @r1, r0
 256         synco
 257
 258         /* Dummy read */
 259         mov.l SDRAM_A, r1
 260         synco
 261         mov.l @r1, r0
 262         synco
 263
 264         /* need sleep 186A0 */
 265
 266         bra     init_pfc_sh7734
 267         nop
 268
 269         .align 2
 270
 271 init_dbsc3_ctrl_533:
 272
 273         write32 DBKIND_A, DBKIND_D
 274         write32 DBCONF_A, DBCONF_D
 275
 276         write32 DBTR0_A,        DBTR0_D_533
 277         write32 DBTR1_A,        DBTR1_D_533
 278         write32 DBTR2_A,        DBTR2_D
 279         write32 DBTR3_A,        DBTR3_D_533
 280         write32 DBTR4_A,        DBTR4_D_533
 281         write32 DBTR5_A,        DBTR5_D_533
 282         write32 DBTR6_A,        DBTR6_D_533
 283         write32 DBTR7_A,        DBTR7_D
 284         write32 DBTR8_A,        DBTR8_D_533
 285         write32 DBTR9_A,        DBTR9_D
 286         write32 DBTR10_A,       DBTR10_D_533
 287         write32 DBTR11_A,       DBTR11_D
 288         write32 DBTR12_A,       DBTR12_D_533
 289         write32 DBTR13_A,       DBTR13_D_533
 290         write32 DBTR14_A,       DBTR14_D
 291         write32 DBTR15_A,       DBTR15_D
 292         write32 DBTR16_A,       DBTR16_D_533
 293         write32 DBTR17_A,       DBTR17_D_533
 294         write32 DBTR18_A,       DBTR18_D_533
 295
 296         write32 DBBL_A, DBBL_D
 297         write32 DBRNK0_A,       DBRNK0_D
 298
 299         write32 DBCMD_A,        DBCMD_D0_533
 300         write32 DBCMD_A,        DBCMD_D1
 301         write32 DBCMD_A,        DBCMD_D2
 302         write32 DBCMD_A,        DBCMD_D3
 303         write32 DBCMD_A,        DBCMD_D4
 304         write32 DBCMD_A,        DBCMD_D5_533
 305         write32 DBCMD_A,        DBCMD_D6
 306         write32 DBCMD_A,        DBCMD_D7
 307         write32 DBCMD_A,        DBCMD_D8
 308         write32 DBCMD_A,        DBCMD_D9_533
 309         write32 DBCMD_A,        DBCMD_D10
 310         write32 DBCMD_A,        DBCMD_D11
 311         write32 DBCMD_A,        DBCMD_D12
 312
 313         write32 DBBS0CNT1_A,    DBBS0CNT1_D
 314         write32 DBPDNCNF_A,             DBPDNCNF_D
 315
 316         write32 DBRFCNF0_A,     DBRFCNF0_D
 317         write32 DBRFCNF1_A,     DBRFCNF1_D_533
 318         write32 DBRFCNF2_A,     DBRFCNF2_D
 319         write32 DBRFEN_A,       DBRFEN_D
 320         write32 DBACEN_A,       DBACEN_D
 321         write32 DBACEN_A,       DBACEN_D
 322
 323         /* Dummy read */
 324         mov.l DBWAIT_A, r1
 325         synco
 326         mov.l @r1, r0
 327         synco
 328
 329         /* Dummy read */
 330         mov.l SDRAM_A, r1
 331         synco
 332         mov.l @r1, r0
 333         synco
 334
 335         /* need sleep 186A0 */
 336
 337         bra     init_pfc_sh7734
 338         nop
 339
 340         .align 2
 341
 342 DBKIND_A:       .long   0xFE800020
 343 DBKIND_D:       .long   0x00000005
 344 DBCONF_A:       .long   0xFE800024
 345 DBCONF_D:       .long   0x0D030A01
 346
 347 DBTR0_A:        .long   0xFE800040
 348 DBTR0_D_533:.long       0x00000004
 349 DBTR0_D_400:.long       0x00000003
 350 DBTR1_A:        .long   0xFE800044
 351 DBTR1_D_533:.long       0x00000003
 352 DBTR1_D_400:.long       0x00000002
 353 DBTR2_A:        .long   0xFE800048
 354 DBTR2_D:        .long   0x00000000
 355 DBTR3_A:        .long   0xFE800050
 356 DBTR3_D_533:.long       0x00000004
 357 DBTR3_D_400:.long       0x00000003
 358
 359 DBTR4_A:        .long   0xFE800054
 360 DBTR4_D_533:.long       0x00050004
 361 DBTR4_D_400:.long       0x00050003
 362
 363 DBTR5_A:        .long   0xFE800058
 364 DBTR5_D_533:.long       0x0000000F
 365 DBTR5_D_400:.long       0x0000000B
 366
 367 DBTR6_A:        .long   0xFE80005C
 368 DBTR6_D_533:.long       0x0000000B
 369 DBTR6_D_400:.long       0x00000008
 370
 371 DBTR7_A:        .long   0xFE800060
 372 DBTR7_D:        .long   0x00000002 /* common value */
 373
 374 DBTR8_A:        .long   0xFE800064
 375 DBTR8_D_533:.long       0x0000000D
 376 DBTR8_D_400:.long       0x0000000A
 377
 378 DBTR9_A:        .long   0xFE800068
 379 DBTR9_D:        .long   0x00000002 /* common value */
 380
 381 DBTR10_A:       .long   0xFE80006C
 382 DBTR10_D_533:.long      0x00000004
 383 DBTR10_D_400:.long      0x00000003
 384
 385 DBTR11_A:       .long   0xFE800070
 386 DBTR11_D:       .long   0x00000008 /* common value */
 387
 388 DBTR12_A:       .long   0xFE800074
 389 DBTR12_D_533:.long      0x00000009
 390 DBTR12_D_400:.long      0x00000008
 391
 392 DBTR13_A:       .long   0xFE800078
 393 DBTR13_D_533:.long      0x00000022
 394 DBTR13_D_400:.long      0x0000001A
 395
 396 DBTR14_A:       .long   0xFE80007C
 397 DBTR14_D:       .long   0x00070002 /* common value */
 398
 399 DBTR15_A:       .long   0xFE800080
 400 DBTR15_D:       .long   0x00000003 /* common value */
 401
 402 DBTR16_A:       .long   0xFE800084
 403 DBTR16_D_533:.long      0x120A1001
 404 DBTR16_D_400:.long      0x12091001
 405
 406 DBTR17_A:       .long   0xFE800088
 407 DBTR17_D_533:.long      0x00040000
 408 DBTR17_D_400:.long      0x00030000
 409
 410 DBTR18_A:       .long   0xFE80008C
 411 DBTR18_D_533:.long      0x02010200
 412 DBTR18_D_400:.long      0x02000207
 413
 414 DBBL_A: .long   0xFE8000B0
 415 DBBL_D: .long   0x00000000
 416
 417 DBRNK0_A:               .long   0xFE800100
 418 DBRNK0_D:               .long   0x00000001
 419
 420 DBCMD_A:                .long   0xFE800018
 421 DBCMD_D0_533:   .long   0x1100006B
 422 DBCMD_D0_400:   .long   0x11000050
 423 DBCMD_D1:               .long   0x0B000000 /* common value */
 424 DBCMD_D2:               .long   0x2A004000 /* common value */
 425 DBCMD_D3:               .long   0x2B006000 /* common value */
 426 DBCMD_D4:               .long   0x29002004 /* common value */
 427 DBCMD_D5_533:   .long   0x28000743
 428 DBCMD_D5_400:   .long   0x28000533
 429 DBCMD_D6:               .long   0x0B000000 /* common value */
 430 DBCMD_D7:               .long   0x0C000000 /* common value */
 431 DBCMD_D8:               .long   0x0C000000 /* common value */
 432 DBCMD_D9_533:   .long   0x28000643
 433 DBCMD_D9_400:   .long   0x28000433
 434 DBCMD_D10:              .long   0x000000C8 /* common value */
 435 DBCMD_D11:              .long   0x29002384 /* common value */
 436 DBCMD_D12:              .long   0x29002004 /* common value */
 437
 438 DBBS0CNT1_A:    .long   0xFE800304
 439 DBBS0CNT1_D:    .long   0x00000000
 440 DBPDNCNF_A:             .long   0xFE800180
 441 DBPDNCNF_D:             .long   0x00000200
 442
 443 DBRFCNF0_A:             .long   0xFE8000E0
 444 DBRFCNF0_D:             .long   0x000001FF
 445 DBRFCNF1_A:             .long   0xFE8000E4
 446 DBRFCNF1_D_533: .long   0x00000805
 447 DBRFCNF1_D_400: .long   0x00000618
 448
 449 DBRFCNF2_A:             .long   0xFE8000E8
 450 DBRFCNF2_D:             .long   0x00000000
 451
 452 DBRFEN_A:               .long   0xFE800014
 453 DBRFEN_D:               .long   0x00000001
 454
 455 DBACEN_A:               .long   0xFE800010
 456 DBACEN_D:               .long   0x00000001
 457
 458 DBWAIT_A:               .long   0xFE80001C
 459 SDRAM_A:                .long   0x0C000000
 460
 461 init_pfc_sh7734:
 462         write32 PFC_PMMR_A, PFC_PMMR_MODESEL1
 463         write32 PFC_MODESEL1_A, PFC_MODESEL1_D
 464
 465         write32 PFC_PMMR_A, PFC_PMMR_MODESEL2
 466         write32 PFC_MODESEL2_A, PFC_MODESEL2_D
 467
 468         write32 PFC_PMMR_A, PFC_PMMR_IPSR3
 469         write32 PFC_IPSR3_A, PFC_IPSR3_D
 470
 471         write32 PFC_PMMR_A, PFC_PMMR_IPSR4
 472         write32 PFC_IPSR4_A, PFC_IPSR4_D
 473
 474         write32 PFC_PMMR_A, PFC_PMMR_IPSR11
 475         write32 PFC_IPSR11_A, PFC_IPSR11_D
 476
 477         write32 PFC_PMMR_A, PFC_PMMR_GPSR0
 478         write32 PFC_GPSR0_A, PFC_GPSR0_D
 479
 480         write32 PFC_PMMR_A, PFC_PMMR_GPSR1
 481         write32 PFC_GPSR1_A, PFC_GPSR1_D
 482
 483         write32 PFC_PMMR_A, PFC_PMMR_GPSR2
 484         write32 PFC_GPSR2_A, PFC_GPSR2_D
 485
 486         write32 PFC_PMMR_A, PFC_PMMR_GPSR3
 487         write32 PFC_GPSR3_A, PFC_GPSR3_D
 488
 489         write32 PFC_PMMR_A, PFC_PMMR_GPSR4
 490         write32 PFC_GPSR4_A, PFC_GPSR4_D
 491
 492         write32 PFC_PMMR_A, PFC_PMMR_GPSR5
 493         write32 PFC_GPSR5_A, PFC_GPSR5_D
 494
 495         /* sleep 186A0 */
 496
 497         write32 GPIO2_INOUTSEL1_A, GPIO2_INOUTSEL1_D
 498         write32 GPIO1_OUTDT1_A, GPIO1_OUTDT1_D
 499         write32 GPIO2_INOUTSEL2_A, GPIO2_INOUTSEL2_D
 500         write32 GPIO2_OUTDT2_A, GPIO2_OUTDT2_D
 501         write32 GPIO4_INOUTSEL4_A,      GPIO4_INOUTSEL4_D
 502         write32 GPIO4_OUTDT4_A, GPIO4_OUTDT4_D
 503
 504         write32 CCR_A,  CCR_D
 505
 506         stc sr, r0
 507         mov.l  SR_MASK_D, r1
 508         and r1, r0
 509         ldc r0, sr
 510
 511         rts
 512         nop
 513
 514         .align  2
 515
 516 PFC_PMMR_A:             .long   0xFFFC0000
 517
 518 /* MODESEL
 519  * 28: Select IEBUS Group B
 520  */
 521 PFC_MODESEL1_A: .long   0xFFFC004C
 522 PFC_MODESEL1_D: .long   0x10000000
 523 PFC_PMMR_MODESEL1:      .long   0xEFFFFFFF
 524
 525 /* MODESEL
 526  * 9: Select SCIF3 Group B
 527  * 7: Select SCIF2 Group B
 528  * 4: Select SCIF1 Group B
 529  */
 530 PFC_MODESEL2_A: .long   0xFFFC0050
 531 PFC_MODESEL2_D: .long   0x00000290
 532 PFC_PMMR_MODESEL2:      .long   0xFFFFFD6F
 533
 534 # Enable functios
 535 # SD1_DAT2_A SD1_DAT1_A, SD1_DAT0_A,
 536 # EXWAIT0, RDW/RW, SD1_CMD_A, SD1_WP_A,
 537 # SD1_CD_A, TX3_B, RX3_B, CS1, D15
 538 PFC_IPSR3_A:    .long   0xFFFC0028
 539 PFC_IPSR3_D:    .long   0x09209248
 540 PFC_PMMR_IPSR3: .long   0xF6DF6DB7
 541
 542 # Enable functios
 543 # RMII0_MDIO_A , RMII0_MDC_A,
 544 # RMII0_CRS_DV_A, RMII0_RX_ER_A,
 545 # RMII0_TXD_EN_A, MII0_RXD1_A
 546 PFC_IPSR4_A:    .long   0xFFFC002C
 547 PFC_IPSR4_D:    .long   0x0001B6DB
 548 PFC_PMMR_IPSR4: .long   0xFFFE4924
 549
 550 # Enable functios
 551 # DACK1, DREQ1, SD1_DAT3_A, SD1_CLK_A, IERX_B,
 552 # IETX_B, TX0_A, RMII0_TXD0_A,
 553 # RMII0_TXD1_A, RMII0_TXD0_A, SDSEL, SDA0, SDA1, SCL1
 554 PFC_IPSR11_A:   .long   0xFFFC0048
 555 PFC_IPSR11_D:   .long   0x002C89B0
 556 PFC_PMMR_IPSR11:.long   0xFFD3764F
 557
 558 PFC_GPSR0_A:    .long   0xFFFC0004
 559 PFC_GPSR0_D:    .long   0xFFFFFFFF
 560 PFC_PMMR_GPSR0: .long   0x00000000
 561
 562 PFC_GPSR1_A:    .long   0xFFFC0008
 563 PFC_GPSR1_D:    .long   0x7FBF7FFF
 564 PFC_PMMR_GPSR1: .long   0x80408000
 565
 566 PFC_GPSR2_A:    .long   0xFFFC000C
 567 PFC_GPSR2_D:    .long   0xBFC07EDF
 568 PFC_PMMR_GPSR2: .long   0x403F8120
 569
 570 PFC_GPSR3_A:    .long   0xFFFC0010
 571 PFC_GPSR3_D:    .long   0xFFFFFFFF
 572 PFC_PMMR_GPSR3: .long   0x00000000
 573
 574 PFC_GPSR4_A:    .long   0xFFFC0014
 575 #if 0 /* orig */
 576 PFC_GPSR4_D:    .long   0xFFFFFFFF
 577 PFC_PMMR_GPSR4: .long   0x00000000
 578 #else
 579 PFC_GPSR4_D:    .long   0xFBFFFFFF
 580 PFC_PMMR_GPSR4: .long   0x04000000
 581 #endif
 582
 583 PFC_GPSR5_A:    .long   0xFFFC0018
 584 PFC_GPSR5_D:    .long   0x00000C01
 585 PFC_PMMR_GPSR5: .long   0xFFFFF3FE
 586
 587 I2C_ICCR2_A: .long      0xFFC70001
 588 I2C_ICCR2_D: .long      0x00
 589 I2C_ICCR2_D1: .long     0x20
 590
 591 GPIO2_INOUTSEL1_A:      .long   0xFFC41004
 592 GPIO2_INOUTSEL1_D:      .long   0x80408000
 593 GPIO1_OUTDT1_A:         .long   0xFFC41008      /* bit15: LED4, bit22: LED5 */
 594 GPIO1_OUTDT1_D:         .long   0x80408000
 595 GPIO2_INOUTSEL2_A:      .long   0xFFC42004
 596 GPIO2_INOUTSEL2_D:      .long   0x40000120
 597 GPIO2_OUTDT2_A:         .long   0xFFC42008
 598 GPIO2_OUTDT2_D:         .long   0x40000120
 599 GPIO4_INOUTSEL4_A:      .long   0xFFC44004
 600 GPIO4_INOUTSEL4_D:      .long   0x04000000
 601 GPIO4_OUTDT4_A:         .long   0xFFC44008
 602 GPIO4_OUTDT4_D:         .long   0x04000000
 603
 604 CCR_A:  .long   0xFF00001C
 605 CCR_D:  .long   0x0000090B
 606 SR_MASK_D:      .long   0xEFFFFF0F