board/renesas/rsk7203/lowlevel_init.S

   1 /*
   2  * Copyright (C) 2008 Nobuhiro Iwamatsu
   3  * Copyright (C) 2008 Renesas Solutions Corp.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7 #include <config.h>
   8 #include <version.h>
   9
  10 #include <asm/processor.h>
  11 #include <asm/macro.h>
  12
  13         .global lowlevel_init
  14
  15         .text
  16         .align  2
  17
  18 lowlevel_init:
  19         /* Cache setting */
  20         write32 CCR1_A ,CCR1_D
  21
  22         /* ConfigurePortPins */
  23         write16 PECRL3_A, PECRL3_D
  24
  25         write16 PCCRL4_A, PCCRL4_D0
  26
  27         write16 PECRL4_A, PECRL4_D0
  28
  29         write16 PEIORL_A, PEIORL_D0
  30
  31         write16 PCIORL_A, PCIORL_D
  32
  33         write16 PFCRH2_A, PFCRH2_D
  34
  35         write16 PFCRH3_A, PFCRH3_D
  36
  37         write16 PFCRH1_A, PFCRH1_D
  38
  39         write16 PFIORH_A, PFIORH_D
  40
  41         write16 PECRL1_A, PECRL1_D0
  42
  43         write16 PEIORL_A, PEIORL_D1
  44
  45         /* Configure Operating Frequency */
  46         write16 WTCSR_A, WTCSR_D0
  47
  48         write16 WTCSR_A, WTCSR_D1
  49
  50         write16 WTCNT_A, WTCNT_D
  51
  52         /* Set clock mode*/
  53         write16 FRQCR_A, FRQCR_D
  54
  55         /* Configure Bus And Memory */
  56 init_bsc_cs0:
  57         write16 PCCRL4_A, PCCRL4_D1
  58
  59         write16 PECRL1_A, PECRL1_D1
  60
  61         write32 CMNCR_A, CMNCR_D
  62
  63         write32 CS0BCR_A, CS0BCR_D
  64
  65         write32 CS0WCR_A, CS0WCR_D
  66
  67 init_bsc_cs1:
  68         write16 PECRL4_A, PECRL4_D1
  69
  70         write32 CS1WCR_A, CS1WCR_D
  71
  72 init_sdram:
  73         write16 PCCRL2_A, PCCRL2_D
  74
  75         write16 PCCRL4_A, PCCRL4_D2
  76
  77         write16 PCCRL1_A, PCCRL1_D
  78
  79         write16 PCCRL3_A, PCCRL3_D
  80
  81         write32 CS3BCR_A, CS3BCR_D
  82
  83         write32 CS3WCR_A, CS3WCR_D
  84
  85         write32 SDCR_A, SDCR_D
  86
  87         write32 RTCOR_A, RTCOR_D
  88
  89         write32 RTCSR_A, RTCSR_D
  90
  91         /* wait 200us */
  92         mov.l   REPEAT_D, r3
  93         mov     #0, r2
  94 repeat0:
  95         add     #1, r2
  96         cmp/hs  r3, r2
  97         bf      repeat0
  98         nop
  99
 100         mov.l   SDRAM_MODE, r1
 101         mov     #0, r0
 102         mov.l   r0, @r1
 103
 104         nop
 105         rts
 106
 107         .align 4
 108
 109 CCR1_A:         .long CCR1
 110 CCR1_D:         .long 0x0000090B
 111 PCCRL4_A:       .long 0xFFFE3910
 112 PCCRL4_D0:      .word 0x0000
 113 .align 2
 114 PECRL4_A:       .long 0xFFFE3A10
 115 PECRL4_D0:      .word 0x0000
 116 .align 2
 117 PECRL3_A:       .long 0xFFFE3A12
 118 PECRL3_D:       .word 0x0000
 119 .align 2
 120 PEIORL_A:       .long 0xFFFE3A06
 121 PEIORL_D0:      .word 0x1C00
 122 PEIORL_D1:      .word 0x1C02
 123 PCIORL_A:       .long 0xFFFE3906
 124 PCIORL_D:       .word 0x4000
 125 .align 2
 126 PFCRH2_A:       .long 0xFFFE3A8C
 127 PFCRH2_D:       .word 0x0000
 128 .align 2
 129 PFCRH3_A:       .long 0xFFFE3A8A
 130 PFCRH3_D:       .word 0x0000
 131 .align 2
 132 PFCRH1_A:       .long 0xFFFE3A8E
 133 PFCRH1_D:       .word 0x0000
 134 .align 2
 135 PFIORH_A:       .long 0xFFFE3A84
 136 PFIORH_D:       .word 0x0729
 137 .align 2
 138 PECRL1_A:       .long 0xFFFE3A16
 139 PECRL1_D0:      .word 0x0033
 140 .align 2
 141
 142
 143 WTCSR_A:        .long 0xFFFE0000
 144 WTCSR_D0:       .word 0xA518
 145 WTCSR_D1:       .word 0xA51D
 146 WTCNT_A:        .long 0xFFFE0002
 147 WTCNT_D:        .word 0x5A84
 148 .align 2
 149 FRQCR_A:        .long 0xFFFE0010
 150 FRQCR_D:        .word 0x0104
 151 .align 2
 152
 153 PCCRL4_D1:      .word 0x0010
 154 PECRL1_D1:      .word 0x0133
 155
 156 CMNCR_A:        .long 0xFFFC0000
 157 CMNCR_D:        .long 0x00001810
 158 CS0BCR_A:       .long 0xFFFC0004
 159 CS0BCR_D:       .long 0x10000400
 160 CS0WCR_A:       .long 0xFFFC0028
 161 CS0WCR_D:       .long 0x00000B41
 162 PECRL4_D1:      .word 0x0100
 163 .align 2
 164 CS1WCR_A:       .long 0xFFFC002C
 165 CS1WCR_D:       .long 0x00000B01
 166 PCCRL4_D2:      .word 0x0011
 167 .align 2
 168 PCCRL3_A:       .long 0xFFFE3912
 169 PCCRL3_D:       .word 0x0011
 170 .align 2
 171 PCCRL2_A:       .long 0xFFFE3914
 172 PCCRL2_D:       .word 0x1111
 173 .align 2
 174 PCCRL1_A:       .long 0xFFFE3916
 175 PCCRL1_D:       .word 0x1010
 176 .align 2
 177 PDCRL4_A:       .long 0xFFFE3990
 178 PDCRL4_D:       .word 0x0011
 179 .align 2
 180 PDCRL3_A:       .long 0xFFFE3992
 181 PDCRL3_D:       .word 0x00011
 182 .align 2
 183 PDCRL2_A:       .long 0xFFFE3994
 184 PDCRL2_D:       .word 0x1111
 185 .align 2
 186 PDCRL1_A:       .long 0xFFFE3996
 187 PDCRL1_D:       .word 0x1000
 188 .align 2
 189 CS3BCR_A:       .long 0xFFFC0010
 190 CS3BCR_D:       .long 0x00004400
 191 CS3WCR_A:       .long 0xFFFC0034
 192 CS3WCR_D:       .long 0x00002892
 193 SDCR_A:         .long 0xFFFC004C
 194 SDCR_D:         .long 0x00000809
 195 RTCOR_A:        .long 0xFFFC0058
 196 RTCOR_D:        .long 0xA55A0041
 197 RTCSR_A:        .long 0xFFFC0050
 198 RTCSR_D:        .long 0xa55a0010
 199
 200 SDRAM_MODE:     .long 0xFFFC5040
 201 REPEAT_D:       .long 0x00009C40