board/renesas/rsk7203/lowlevel_init.S

   1 /*
   2  * Copyright (C) 2008 Nobuhiro Iwamatsu
   3  * Copyright (C) 2008 Renesas Solutions Corp.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7 #include <config.h>
   8
   9 #include <asm/processor.h>
  10 #include <asm/macro.h>
  11
  12         .global lowlevel_init
  13
  14         .text
  15         .align  2
  16
  17 lowlevel_init:
  18         /* Cache setting */
  19         write32 CCR1_A ,CCR1_D
  20
  21         /* ConfigurePortPins */
  22         write16 PECRL3_A, PECRL3_D
  23
  24         write16 PCCRL4_A, PCCRL4_D0
  25
  26         write16 PECRL4_A, PECRL4_D0
  27
  28         write16 PEIORL_A, PEIORL_D0
  29
  30         write16 PCIORL_A, PCIORL_D
  31
  32         write16 PFCRH2_A, PFCRH2_D
  33
  34         write16 PFCRH3_A, PFCRH3_D
  35
  36         write16 PFCRH1_A, PFCRH1_D
  37
  38         write16 PFIORH_A, PFIORH_D
  39
  40         write16 PECRL1_A, PECRL1_D0
  41
  42         write16 PEIORL_A, PEIORL_D1
  43
  44         /* Configure Operating Frequency */
  45         write16 WTCSR_A, WTCSR_D0
  46
  47         write16 WTCSR_A, WTCSR_D1
  48
  49         write16 WTCNT_A, WTCNT_D
  50
  51         /* Set clock mode*/
  52         write16 FRQCR_A, FRQCR_D
  53
  54         /* Configure Bus And Memory */
  55 init_bsc_cs0:
  56         write16 PCCRL4_A, PCCRL4_D1
  57
  58         write16 PECRL1_A, PECRL1_D1
  59
  60         write32 CMNCR_A, CMNCR_D
  61
  62         write32 CS0BCR_A, CS0BCR_D
  63
  64         write32 CS0WCR_A, CS0WCR_D
  65
  66 init_bsc_cs1:
  67         write16 PECRL4_A, PECRL4_D1
  68
  69         write32 CS1WCR_A, CS1WCR_D
  70
  71 init_sdram:
  72         write16 PCCRL2_A, PCCRL2_D
  73
  74         write16 PCCRL4_A, PCCRL4_D2
  75
  76         write16 PCCRL1_A, PCCRL1_D
  77
  78         write16 PCCRL3_A, PCCRL3_D
  79
  80         write32 CS3BCR_A, CS3BCR_D
  81
  82         write32 CS3WCR_A, CS3WCR_D
  83
  84         write32 SDCR_A, SDCR_D
  85
  86         write32 RTCOR_A, RTCOR_D
  87
  88         write32 RTCSR_A, RTCSR_D
  89
  90         /* wait 200us */
  91         mov.l   REPEAT_D, r3
  92         mov     #0, r2
  93 repeat0:
  94         add     #1, r2
  95         cmp/hs  r3, r2
  96         bf      repeat0
  97         nop
  98
  99         mov.l   SDRAM_MODE, r1
 100         mov     #0, r0
 101         mov.l   r0, @r1
 102
 103         nop
 104         rts
 105
 106         .align 4
 107
 108 CCR1_A:         .long CCR1
 109 CCR1_D:         .long 0x0000090B
 110 PCCRL4_A:       .long 0xFFFE3910
 111 PCCRL4_D0:      .word 0x0000
 112 .align 2
 113 PECRL4_A:       .long 0xFFFE3A10
 114 PECRL4_D0:      .word 0x0000
 115 .align 2
 116 PECRL3_A:       .long 0xFFFE3A12
 117 PECRL3_D:       .word 0x0000
 118 .align 2
 119 PEIORL_A:       .long 0xFFFE3A06
 120 PEIORL_D0:      .word 0x1C00
 121 PEIORL_D1:      .word 0x1C02
 122 PCIORL_A:       .long 0xFFFE3906
 123 PCIORL_D:       .word 0x4000
 124 .align 2
 125 PFCRH2_A:       .long 0xFFFE3A8C
 126 PFCRH2_D:       .word 0x0000
 127 .align 2
 128 PFCRH3_A:       .long 0xFFFE3A8A
 129 PFCRH3_D:       .word 0x0000
 130 .align 2
 131 PFCRH1_A:       .long 0xFFFE3A8E
 132 PFCRH1_D:       .word 0x0000
 133 .align 2
 134 PFIORH_A:       .long 0xFFFE3A84
 135 PFIORH_D:       .word 0x0729
 136 .align 2
 137 PECRL1_A:       .long 0xFFFE3A16
 138 PECRL1_D0:      .word 0x0033
 139 .align 2
 140
 141
 142 WTCSR_A:        .long 0xFFFE0000
 143 WTCSR_D0:       .word 0xA518
 144 WTCSR_D1:       .word 0xA51D
 145 WTCNT_A:        .long 0xFFFE0002
 146 WTCNT_D:        .word 0x5A84
 147 .align 2
 148 FRQCR_A:        .long 0xFFFE0010
 149 FRQCR_D:        .word 0x0104
 150 .align 2
 151
 152 PCCRL4_D1:      .word 0x0010
 153 PECRL1_D1:      .word 0x0133
 154
 155 CMNCR_A:        .long 0xFFFC0000
 156 CMNCR_D:        .long 0x00001810
 157 CS0BCR_A:       .long 0xFFFC0004
 158 CS0BCR_D:       .long 0x10000400
 159 CS0WCR_A:       .long 0xFFFC0028
 160 CS0WCR_D:       .long 0x00000B41
 161 PECRL4_D1:      .word 0x0100
 162 .align 2
 163 CS1WCR_A:       .long 0xFFFC002C
 164 CS1WCR_D:       .long 0x00000B01
 165 PCCRL4_D2:      .word 0x0011
 166 .align 2
 167 PCCRL3_A:       .long 0xFFFE3912
 168 PCCRL3_D:       .word 0x0011
 169 .align 2
 170 PCCRL2_A:       .long 0xFFFE3914
 171 PCCRL2_D:       .word 0x1111
 172 .align 2
 173 PCCRL1_A:       .long 0xFFFE3916
 174 PCCRL1_D:       .word 0x1010
 175 .align 2
 176 PDCRL4_A:       .long 0xFFFE3990
 177 PDCRL4_D:       .word 0x0011
 178 .align 2
 179 PDCRL3_A:       .long 0xFFFE3992
 180 PDCRL3_D:       .word 0x00011
 181 .align 2
 182 PDCRL2_A:       .long 0xFFFE3994
 183 PDCRL2_D:       .word 0x1111
 184 .align 2
 185 PDCRL1_A:       .long 0xFFFE3996
 186 PDCRL1_D:       .word 0x1000
 187 .align 2
 188 CS3BCR_A:       .long 0xFFFC0010
 189 CS3BCR_D:       .long 0x00004400
 190 CS3WCR_A:       .long 0xFFFC0034
 191 CS3WCR_D:       .long 0x00002892
 192 SDCR_A:         .long 0xFFFC004C
 193 SDCR_D:         .long 0x00000809
 194 RTCOR_A:        .long 0xFFFC0058
 195 RTCOR_D:        .long 0xA55A0041
 196 RTCSR_A:        .long 0xFFFC0050
 197 RTCSR_D:        .long 0xa55a0010
 198
 199 SDRAM_MODE:     .long 0xFFFC5040
 200 REPEAT_D:       .long 0x00009C40