board/renesas/rsk7264/lowlevel_init.S

   1 /*
   2  * Copyright (C) 2011 Renesas Electronics Europe Ltd.
   3  * Copyright (C) 2008 Renesas Solutions Corp.
   4  * Copyright (C) 2008 Nobuhiro Iwamatsu
   5  *
   6  * Based on board/renesas/rsk7203/lowlevel_init.S
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10 #include <config.h>
  11 #include <version.h>
  12
  13 #include <asm/processor.h>
  14 #include <asm/macro.h>
  15
  16         .global lowlevel_init
  17
  18         .text
  19         .align  2
  20
  21 lowlevel_init:
  22         /* Cache setting */
  23         write32 CCR1_A ,CCR1_D
  24
  25         /* io_set_cpg */
  26         write8 STBCR3_A, STBCR3_D
  27         write8 STBCR4_A, STBCR4_D
  28         write8 STBCR5_A, STBCR5_D
  29         write8 STBCR6_A, STBCR6_D
  30         write8 STBCR7_A, STBCR7_D
  31         write8 STBCR8_A, STBCR8_D
  32
  33         /* ConfigurePortPins */
  34
  35         /* Leaving LED1 ON for sanity test */
  36         write16 PJCR1_A, PJCR1_D1
  37         write16 PJCR2_A, PJCR2_D
  38         write16 PJIOR0_A, PJIOR0_D1
  39         write16 PJDR0_A, PJDR0_D
  40         write16 PJPR0_A, PJPR0_D
  41
  42         /* Configure EN_PIN & RS_PIN */
  43         write16 PGCR2_A, PGCR2_D
  44         write16 PGIOR0_A, PGIOR0_D
  45
  46         /* Configure the port pins connected to UART */
  47         write16 PJCR1_A, PJCR1_D2
  48         write16 PJIOR0_A, PJIOR0_D2
  49
  50         /* Configure Operating Frequency */
  51         write16 WTCSR_A, WTCSR_D0
  52         write16 WTCSR_A, WTCSR_D1
  53         write16 WTCNT_A, WTCNT_D
  54
  55         /* Control of RESBANK */
  56         write16 IBNR_A, IBNR_D
  57         /* Enable SCIF3 module */
  58         write16 STBCR4_A, STBCR4_D
  59
  60         /* Set clock mode*/
  61         write16 FRQCR_A, FRQCR_D
  62
  63         /* Configure Bus And Memory */
  64 init_bsc_cs0:
  65
  66 pfc_settings:
  67         write16 PCCR2_A, PCCR2_D
  68         write16 PCCR1_A, PCCR1_D
  69         write16 PCCR0_A, PCCR0_D
  70
  71         write16 PBCR0_A, PBCR0_D
  72         write16 PBCR1_A, PBCR1_D
  73         write16 PBCR2_A, PBCR2_D
  74         write16 PBCR3_A, PBCR3_D
  75         write16 PBCR4_A, PBCR4_D
  76         write16 PBCR5_A, PBCR5_D
  77
  78         write16 PDCR0_A, PDCR0_D
  79         write16 PDCR1_A, PDCR1_D
  80         write16 PDCR2_A, PDCR2_D
  81         write16 PDCR3_A, PDCR3_D
  82
  83         write32 CS0WCR_A, CS0WCR_D
  84         write32 CS0BCR_A, CS0BCR_D
  85
  86 init_bsc_cs2:
  87         write16 PJCR0_A, PJCR0_D
  88         write32 CS2WCR_A, CS2WCR_D
  89
  90 init_sdram:
  91         write32 CS3BCR_A, CS3BCR_D
  92         write32 CS3WCR_A, CS3WCR_D
  93         write32 SDCR_A, SDCR_D
  94         write32 RTCOR_A, RTCOR_D
  95         write32 RTCSR_A, RTCSR_D
  96
  97         /* wait 200us */
  98         mov.l   REPEAT_D, r3
  99         mov     #0, r2
 100 repeat0:
 101         add     #1, r2
 102         cmp/hs  r3, r2
 103         bf      repeat0
 104         nop
 105
 106         mov.l   SDRAM_MODE, r1
 107         mov     #0, r0
 108         mov.l   r0, @r1
 109
 110         nop
 111         rts
 112
 113         .align 4
 114
 115 CCR1_A:         .long CCR1
 116 CCR1_D:         .long 0x0000090B
 117 FRQCR_A:        .long 0xFFFE0010
 118 FRQCR_D:        .word 0x1003
 119 .align 2
 120 STBCR3_A:       .long 0xFFFE0408
 121 STBCR3_D:       .long 0x00000002
 122 STBCR4_A:       .long 0xFFFE040C
 123 STBCR4_D:       .word 0x0000
 124 .align 2
 125 STBCR5_A:       .long 0xFFFE0410
 126 STBCR5_D:       .long 0x00000010
 127 STBCR6_A:       .long 0xFFFE0414
 128 STBCR6_D:       .long 0x00000002
 129 STBCR7_A:       .long 0xFFFE0418
 130 STBCR7_D:       .long 0x0000002A
 131 STBCR8_A:       .long 0xFFFE041C
 132 STBCR8_D:       .long 0x0000007E
 133 PJCR1_A:        .long 0xFFFE390C
 134 PJCR1_D1:       .word 0x0000
 135 PJCR1_D2:       .word 0x0022
 136 PJCR2_A:        .long 0xFFFE390A
 137 PJCR2_D:        .word 0x0000
 138 .align 2
 139 PJIOR0_A:       .long 0xFFFE3912
 140 PJIOR0_D1:      .word 0x0FC0
 141 PJIOR0_D2:      .word 0x0FE0
 142 PJDR0_A:        .long 0xFFFE3916
 143 PJDR0_D:        .word 0x0FBF
 144 .align 2
 145 PJPR0_A:        .long 0xFFFE391A
 146 PJPR0_D:        .long 0x00000FBF
 147 PGCR2_A:        .long 0xFFFE38CA
 148 PGCR2_D:        .word 0x0000
 149 .align 2
 150 PGIOR0_A:       .long 0xFFFE38D2
 151 PGIOR0_D:       .word 0x03F0
 152 .align 2
 153 WTCSR_A:        .long 0xFFFE0000
 154 WTCSR_D0:       .word 0x0000
 155 WTCSR_D1:       .word 0x0000
 156 WTCNT_A:        .long 0xFFFE0002
 157 WTCNT_D:        .word 0x0000
 158 .align 2
 159 PCCR0_A:        .long 0xFFFE384E
 160 PDCR0_A:        .long 0xFFFE386E
 161 PDCR1_A:        .long 0xFFFE386C
 162 PDCR2_A:        .long 0xFFFE386A
 163 PDCR3_A:        .long 0xFFFE3868
 164 PBCR0_A:        .long 0xFFFE382E
 165 PBCR1_A:        .long 0xFFFE382C
 166 PBCR2_A:        .long 0xFFFE382A
 167 PBCR3_A:        .long 0xFFFE3828
 168 PBCR4_A:        .long 0xFFFE3826
 169 PBCR5_A:        .long 0xFFFE3824
 170 PCCR0_D:        .word 0x1111
 171 PDCR0_D:        .word 0x1111
 172 PDCR1_D:        .word 0x1111
 173 PDCR2_D:        .word 0x1111
 174 PDCR3_D:        .word 0x1111
 175 PBCR0_D:        .word 0x1110
 176 PBCR1_D:        .word 0x1111
 177 PBCR2_D:        .word 0x1111
 178 PBCR3_D:        .word 0x1111
 179 PBCR4_D:        .word 0x1111
 180 PBCR5_D:        .word 0x0111
 181 .align 2
 182 CS0WCR_A:       .long 0xFFFC0028
 183 CS0WCR_D:       .long 0x00000B41
 184 CS0BCR_A:       .long 0xFFFC0004
 185 CS0BCR_D:       .long 0x10000400
 186 PJCR0_A:        .long 0xFFFE390E
 187 PJCR0_D:        .word 0x3300
 188 .align 2
 189 CS2WCR_A:       .long 0xFFFC0030
 190 CS2WCR_D:       .long 0x00000B01
 191 PCCR2_A:        .long 0xFFFE384A
 192 PCCR2_D:        .word 0x0001
 193 .align 2
 194 PCCR1_A:        .long 0xFFFE384C
 195 PCCR1_D:        .word 0x1111
 196 .align 2
 197 CS3BCR_A:       .long 0xFFFC0010
 198 CS3BCR_D:       .long 0x00004400
 199 CS3WCR_A:       .long 0xFFFC0034
 200 CS3WCR_D:       .long 0x0000288A
 201 SDCR_A:         .long 0xFFFC004C
 202 SDCR_D:         .long 0x00000812
 203 RTCOR_A:        .long 0xFFFC0058
 204 RTCOR_D:        .long 0xA55A0046
 205 RTCSR_A:        .long 0xFFFC0050
 206 RTCSR_D:        .long 0xA55A0010
 207 IBNR_A:         .long 0xFFFE080E
 208 IBNR_D: .word 0x0000
 209 .align 2
 210 SDRAM_MODE:     .long 0xFFFC5040
 211 REPEAT_D:       .long 0x00000085