board/samsung/goni/mem_setup.S

   1 /*
   2  * Copyright (C) 2009 Samsung Electrnoics
   3  * Minkyu Kang <mk7.kang@samsung.com>
   4  * Kyungmin Park <kyungmin.park@samsung.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <config.h>
  10
  11         .globl mem_ctrl_asm_init
  12 mem_ctrl_asm_init:
  13         cmp     r7, r8
  14
  15         ldreq   r0, =S5PC100_DMC_BASE                   @ 0xE6000000
  16         ldrne   r0, =S5PC110_DMC0_BASE                  @ 0xF0000000
  17         ldrne   r6, =S5PC110_DMC1_BASE                  @ 0xF1400000
  18
  19         /* DLL parameter setting */
  20         ldr     r1, =0x50101000
  21         str     r1, [r0, #0x018]                        @ PHYCONTROL0_OFFSET
  22         strne   r1, [r6, #0x018]                        @ PHYCONTROL0_OFFSET
  23         ldr     r1, =0x000000f4
  24         str     r1, [r0, #0x01C]                        @ PHYCONTROL1_OFFSET
  25         strne   r1, [r6, #0x01C]                        @ PHYCONTROL1_OFFSET
  26         ldreq   r1, =0x0
  27         streq   r1, [r0, #0x020]                        @ PHYCONTROL2_OFFSET
  28
  29         /* DLL on */
  30         ldr     r1, =0x50101002
  31         str     r1, [r0, #0x018]                        @ PHYCONTROL0_OFFSET
  32         strne   r1, [r6, #0x018]                        @ PHYCONTROL0_OFFSET
  33
  34         /* DLL start */
  35         ldr     r1, =0x50101003
  36         str     r1, [r0, #0x018]                        @ PHYCONTROL0_OFFSET
  37         strne   r1, [r6, #0x018]                        @ PHYCONTROL0_OFFSET
  38
  39         mov     r2, #0x4000
  40 wait:   subs    r2, r2, #0x1
  41         cmp     r2, #0x0
  42         bne     wait
  43
  44         cmp     r7, r8
  45         /* Force value locking for DLL off */
  46         str     r1, [r0, #0x018]                        @ PHYCONTROL0_OFFSET
  47         strne   r1, [r6, #0x018]                        @ PHYCONTROL0_OFFSET
  48
  49         /* DLL off */
  50         ldr     r1, =0x50101009
  51         str     r1, [r0, #0x018]                        @ PHYCONTROL0_OFFSET
  52         strne   r1, [r6, #0x018]                        @ PHYCONTROL0_OFFSET
  53
  54         /* auto refresh off */
  55         ldr     r1, =0xff001010 | (1 << 7)
  56         ldr     r2, =0xff001010 | (1 << 7)
  57         str     r1, [r0, #0x000]                        @ CONCONTROL_OFFSET
  58         strne   r2, [r6, #0x000]                        @ CONCONTROL_OFFSET
  59
  60         /*
  61          * Burst Length 4, 2 chips, 32-bit, LPDDR
  62          * OFF: dynamic self refresh, force precharge, dynamic power down off
  63          */
  64         ldr     r1, =0x00212100
  65         ldr     r2, =0x00212100
  66         str     r1, [r0, #0x004]                        @ MEMCONTROL_OFFSET
  67         strne   r2, [r6, #0x004]                        @ MEMCONTROL_OFFSET
  68
  69         /*
  70          * Note:
  71          * If Bank0 has Mobile RAM we place it at 0x3800'0000 (s5pc100 only)
  72          * So finally Bank1 OneDRAM should address start at at 0x3000'0000
  73          */
  74
  75         /*
  76          * DMC0: CS0 : S5PC100/S5PC110
  77          * 0x30 -> 0x30000000
  78          * 0xf8 -> 0x37FFFFFF
  79          * [15:12] 0: Linear
  80          * [11:8 ] 2: 9 bits
  81          * [ 7:4 ] 2: 14 bits
  82          * [ 3:0 ] 2: 4 banks
  83          */
  84         ldr     r3, =0x30f80222
  85         ldr     r4, =0x40f00222
  86 swap_memory:
  87         str     r3, [r0, #0x008]                        @ MEMCONFIG0_OFFSET
  88         str     r4, [r0, #0x00C]                        @ dummy write
  89
  90         /*
  91          * DMC1: CS0 : S5PC110
  92          * 0x40 -> 0x40000000
  93          * 0xf8 -> 0x47FFFFFF (1Gib)
  94          * 0x40 -> 0x40000000
  95          * 0xf0 -> 0x4FFFFFFF (2Gib)
  96          * [15:12] 0: Linear
  97          * [11:8 ] 2: 9 bits  - Col (1Gib)
  98          * [11:8 ] 3: 10 bits - Col (2Gib)
  99          * [ 7:4 ] 2: 14 bits - Row
 100          * [ 3:0 ] 2: 4 banks
 101          */
 102         /* Default : 2GiB */
 103         ldr     r4, =0x40f01322                         @ 2Gib: MCP B
 104         ldr     r5, =0x50f81312                         @ dummy: MCP D
 105         cmp     r9, #1
 106         ldreq   r4, =0x40f81222                         @ 1Gib: MCP A
 107         cmp     r9, #3
 108         ldreq   r5, =0x50f81312                         @ 2Gib + 1Gib: MCP D
 109         cmp     r9, #4
 110         ldreq   r5, =0x50f01312                         @ 2Gib + 2Gib: MCP E
 111
 112         cmp     r7, r8
 113         strne   r4, [r6, #0x008]                        @ MEMCONFIG0_OFFSET
 114         strne   r5, [r6, #0x00C]                        @ MEMCONFIG1_OFFSET
 115
 116         /*
 117          * DMC0: CS1: S5PC100
 118          * 0x38 -> 0x38000000
 119          * 0xf8 -> 0x3fFFFFFF
 120          * [15:12] 0: Linear
 121          * [11:8 ] 2: 9 bits
 122          * [ 7:4 ] 2: 14 bits
 123          * [ 3:0 ] 2: 4 banks
 124          */
 125         eoreq   r3, r3, #0x08000000
 126         streq   r3, [r0, #0xc]                          @ MEMCONFIG1_OFFSET
 127
 128         ldr     r1, =0x20000000
 129         str     r1, [r0, #0x014]                        @ PRECHCONFIG_OFFSET
 130         strne   r1, [r0, #0x014]                        @ PRECHCONFIG_OFFSET
 131         strne   r1, [r6, #0x014]                        @ PRECHCONFIG_OFFSET
 132
 133         /*
 134          * S5PC100:
 135          * DMC:  CS0: 166MHz
 136          *       CS1: 166MHz
 137          * S5PC110:
 138          * DMC0: CS0: 166MHz
 139          * DMC1: CS0: 200MHz
 140          *
 141          * 7.8us * 200MHz %LE %LONG1560(0x618)
 142          * 7.8us * 166MHz %LE %LONG1294(0x50E)
 143          * 7.8us * 133MHz %LE %LONG1038(0x40E),
 144          * 7.8us * 100MHz %LE %LONG780(0x30C),
 145          */
 146         ldr     r1, =0x0000050E
 147         str     r1, [r0, #0x030]                        @ TIMINGAREF_OFFSET
 148         ldrne   r1, =0x00000618
 149         strne   r1, [r6, #0x030]                        @ TIMINGAREF_OFFSET
 150
 151         ldr     r1, =0x14233287
 152         str     r1, [r0, #0x034]                        @ TIMINGROW_OFFSET
 153         ldrne   r1, =0x182332c8
 154         strne   r1, [r6, #0x034]                        @ TIMINGROW_OFFSET
 155
 156         ldr     r1, =0x12130005
 157         str     r1, [r0, #0x038]                        @ TIMINGDATA_OFFSET
 158         ldrne   r1, =0x13130005
 159         strne   r1, [r6, #0x038]                        @ TIMINGDATA_OFFSET
 160
 161         ldr     r1, =0x0E140222
 162         str     r1, [r0, #0x03C]                        @ TIMINGPOWER_OFFSET
 163         ldrne   r1, =0x0E180222
 164         strne   r1, [r6, #0x03C]                        @ TIMINGPOWER_OFFSET
 165
 166         /* chip0 Deselect */
 167         ldr     r1, =0x07000000
 168         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 169         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 170
 171         /* chip0 PALL */
 172         ldr     r1, =0x01000000
 173         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 174         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 175
 176         /* chip0 REFA */
 177         ldr     r1, =0x05000000
 178         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 179         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 180         /* chip0 REFA */
 181         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 182         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 183
 184         /* chip0 MRS */
 185         ldr     r1, =0x00000032
 186         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 187         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 188
 189         /* chip0 EMRS */
 190         ldr     r1, =0x00020020
 191         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 192         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 193
 194         /* chip1 Deselect */
 195         ldr     r1, =0x07100000
 196         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 197         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 198
 199         /* chip1 PALL */
 200         ldr     r1, =0x01100000
 201         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 202         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 203
 204         /* chip1 REFA */
 205         ldr     r1, =0x05100000
 206         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 207         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 208         /* chip1 REFA */
 209         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 210         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 211
 212         /* chip1 MRS */
 213         ldr     r1, =0x00100032
 214         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 215         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 216
 217         /* chip1 EMRS */
 218         ldr     r1, =0x00120020
 219         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 220         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 221
 222         /* auto refresh on */
 223         ldr     r1, =0xFF002030 | (1 << 7)
 224         str     r1, [r0, #0x000]                        @ CONCONTROL_OFFSET
 225         strne   r1, [r6, #0x000]                        @ CONCONTROL_OFFSET
 226
 227         /* PwrdnConfig */
 228         ldr     r1, =0x00100002
 229         str     r1, [r0, #0x028]                        @ PWRDNCONFIG_OFFSET
 230         strne   r1, [r6, #0x028]                        @ PWRDNCONFIG_OFFSET
 231
 232         ldr     r1, =0x00212113
 233         str     r1, [r0, #0x004]                        @ MEMCONTROL_OFFSET
 234         strne   r1, [r6, #0x004]                        @ MEMCONTROL_OFFSET
 235
 236         /* Skip when S5PC110 */
 237         bne     1f
 238
 239         /* Check OneDRAM access area at s5pc100 */
 240         ldreq   r3, =0x38f80222
 241         ldreq   r1, =0x37ffff00
 242         str     r3, [r1]
 243         ldr     r2, [r1]
 244         cmp     r2, r3
 245         beq     swap_memory
 246 1:
 247         mov     pc, lr
 248
 249         .ltorg