board/samsung/smdk5250/dmc_common.c

   1 /*
   2  * Mem setup common file for different types of DDR present on SMDK5250 boards.
   3  *
   4  * Copyright (C) 2012 Samsung Electronics
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/arch/spl.h>
  27
  28 #include "clock_init.h"
  29 #include "setup.h"
  30
  31 #define ZQ_INIT_TIMEOUT 10000
  32
  33 int dmc_config_zq(struct mem_timings *mem,
  34                   struct exynos5_phy_control *phy0_ctrl,
  35                   struct exynos5_phy_control *phy1_ctrl)
  36 {
  37         unsigned long val = 0;
  38         int i;
  39
  40         /*
  41          * ZQ Calibration:
  42          * Select Driver Strength,
  43          * long calibration for manual calibration
  44          */
  45         val = PHY_CON16_RESET_VAL;
  46         val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT;
  47         val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT;
  48         val |= ZQ_CLK_DIV_EN;
  49         writel(val, &phy0_ctrl->phy_con16);
  50         writel(val, &phy1_ctrl->phy_con16);
  51
  52         /* Disable termination */
  53         if (mem->zq_mode_noterm)
  54                 val |= PHY_CON16_ZQ_MODE_NOTERM_MASK;
  55         writel(val, &phy0_ctrl->phy_con16);
  56         writel(val, &phy1_ctrl->phy_con16);
  57
  58         /* ZQ_MANUAL_START: Enable */
  59         val |= ZQ_MANUAL_STR;
  60         writel(val, &phy0_ctrl->phy_con16);
  61         writel(val, &phy1_ctrl->phy_con16);
  62
  63         /* ZQ_MANUAL_START: Disable */
  64         val &= ~ZQ_MANUAL_STR;
  65
  66         /*
  67          * Since we are manaully calibrating the ZQ values,
  68          * we are looping for the ZQ_init to complete.
  69          */
  70         i = ZQ_INIT_TIMEOUT;
  71         while ((readl(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
  72                 sdelay(100);
  73                 i--;
  74         }
  75         if (!i)
  76                 return -1;
  77         writel(val, &phy0_ctrl->phy_con16);
  78
  79         i = ZQ_INIT_TIMEOUT;
  80         while ((readl(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
  81                 sdelay(100);
  82                 i--;
  83         }
  84         if (!i)
  85                 return -1;
  86         writel(val, &phy1_ctrl->phy_con16);
  87
  88         return 0;
  89 }
  90
  91 void update_reset_dll(struct exynos5_dmc *dmc, enum ddr_mode mode)
  92 {
  93         unsigned long val;
  94
  95         if (mode == DDR_MODE_DDR3) {
  96                 val = MEM_TERM_EN | PHY_TERM_EN | DMC_CTRL_SHGATE;
  97                 writel(val, &dmc->phycontrol0);
  98         }
  99
 100         /* Update DLL Information: Force DLL Resyncronization */
 101         val = readl(&dmc->phycontrol0);
 102         val |= FP_RSYNC;
 103         writel(val, &dmc->phycontrol0);
 104
 105         /* Reset Force DLL Resyncronization */
 106         val = readl(&dmc->phycontrol0);
 107         val &= ~FP_RSYNC;
 108         writel(val, &dmc->phycontrol0);
 109 }
 110
 111 void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc)
 112 {
 113         int channel, chip;
 114
 115         for (channel = 0; channel < mem->dmc_channels; channel++) {
 116                 unsigned long mask;
 117
 118                 mask = channel << DIRECT_CMD_CHANNEL_SHIFT;
 119                 for (chip = 0; chip < mem->chips_to_configure; chip++) {
 120                         int i;
 121
 122                         mask |= chip << DIRECT_CMD_CHIP_SHIFT;
 123
 124                         /* Sending NOP command */
 125                         writel(DIRECT_CMD_NOP | mask, &dmc->directcmd);
 126
 127                         /*
 128                          * TODO(alim.akhtar@samsung.com): Do we need these
 129                          * delays? This one and the next were not there for
 130                          * DDR3.
 131                          */
 132                         sdelay(0x10000);
 133
 134                         /* Sending EMRS/MRS commands */
 135                         for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {
 136                                 writel(mem->direct_cmd_msr[i] | mask,
 137                                        &dmc->directcmd);
 138                                 sdelay(0x10000);
 139                         }
 140
 141                         if (mem->send_zq_init) {
 142                                 /* Sending ZQINIT command */
 143                                 writel(DIRECT_CMD_ZQINIT | mask,
 144                                        &dmc->directcmd);
 145
 146                                 sdelay(10000);
 147                         }
 148                 }
 149         }
 150 }
 151
 152 void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc)
 153 {
 154         int channel, chip;
 155
 156         for (channel = 0; channel < mem->dmc_channels; channel++) {
 157                 unsigned long mask;
 158
 159                 mask = channel << DIRECT_CMD_CHANNEL_SHIFT;
 160                 for (chip = 0; chip < mem->chips_per_channel; chip++) {
 161                         mask |= chip << DIRECT_CMD_CHIP_SHIFT;
 162
 163                         /* PALL (all banks precharge) CMD */
 164                         writel(DIRECT_CMD_PALL | mask, &dmc->directcmd);
 165                         sdelay(0x10000);
 166                 }
 167         }
 168 }
 169
 170 void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc)
 171 {
 172         writel(mem->memconfig, &dmc->memconfig0);
 173         writel(mem->memconfig, &dmc->memconfig1);
 174         writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0);
 175         writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
 176 }
 177
 178 void mem_ctrl_init()
 179 {
 180         struct spl_machine_param *param = spl_get_machine_params();
 181         struct mem_timings *mem;
 182         int ret;
 183
 184         mem = clock_get_mem_timings();
 185
 186         /* If there are any other memory variant, add their init call below */
 187         if (param->mem_type == DDR_MODE_DDR3) {
 188                 ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size);
 189                 if (ret) {
 190                         /* will hang if failed to init memory control */
 191                         while (1)
 192                                 ;
 193                 }
 194         } else {
 195                 /* will hang if unknow memory type  */
 196                 while (1)
 197                         ;
 198         }
 199 }