board/samsung/smdk5250/dmc_init_ddr3.c

   1 /*
   2  * DDR3 mem setup file for SMDK5250 board based on EXYNOS5
   3  *
   4  * Copyright (C) 2012 Samsung Electronics
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <asm/io.h>
  27 #include <asm/arch/clock.h>
  28 #include <asm/arch/cpu.h>
  29 #include <asm/arch/dmc.h>
  30 #include "setup.h"
  31 #include "clock_init.h"
  32
  33 #define RDLVL_COMPLETE_TIMEOUT  10000
  34
  35 static void reset_phy_ctrl(void)
  36 {
  37         struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
  38
  39         writel(DDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl);
  40         writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
  41 }
  42
  43 int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
  44 {
  45         unsigned int val;
  46         struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
  47         struct exynos5_dmc *dmc;
  48         int i;
  49
  50         phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE;
  51         phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
  52         dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
  53
  54         reset_phy_ctrl();
  55
  56         /* Set Impedance Output Driver */
  57         val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) |
  58                 (mem->impedance << CA_CKE_DRVR_DS_OFFSET) |
  59                 (mem->impedance << CA_CS_DRVR_DS_OFFSET) |
  60                 (mem->impedance << CA_ADR_DRVR_DS_OFFSET);
  61         writel(val, &phy0_ctrl->phy_con39);
  62         writel(val, &phy1_ctrl->phy_con39);
  63
  64         /* Set Read Latency and Burst Length for PHY0 and PHY1 */
  65         val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
  66                 (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
  67         writel(val, &phy0_ctrl->phy_con42);
  68         writel(val, &phy1_ctrl->phy_con42);
  69
  70         /* ZQ Calibration */
  71         if (dmc_config_zq(mem, phy0_ctrl, phy1_ctrl))
  72                 return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
  73
  74         /* DQ Signal */
  75         writel(mem->phy0_pulld_dqs, &phy0_ctrl->phy_con14);
  76         writel(mem->phy1_pulld_dqs, &phy1_ctrl->phy_con14);
  77
  78         writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
  79                 | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT),
  80                 &dmc->concontrol);
  81
  82         update_reset_dll(dmc, DDR_MODE_DDR3);
  83
  84         /* DQS Signal */
  85         writel(mem->phy0_dqs, &phy0_ctrl->phy_con4);
  86         writel(mem->phy1_dqs, &phy1_ctrl->phy_con4);
  87
  88         writel(mem->phy0_dq, &phy0_ctrl->phy_con6);
  89         writel(mem->phy1_dq, &phy1_ctrl->phy_con6);
  90
  91         writel(mem->phy0_tFS, &phy0_ctrl->phy_con10);
  92         writel(mem->phy1_tFS, &phy1_ctrl->phy_con10);
  93
  94         val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) |
  95                 (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
  96                 (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
  97                 (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
  98         writel(val, &phy0_ctrl->phy_con12);
  99         writel(val, &phy1_ctrl->phy_con12);
 100
 101         /* Start DLL locking */
 102         writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
 103                 &phy0_ctrl->phy_con12);
 104         writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
 105                 &phy1_ctrl->phy_con12);
 106
 107         update_reset_dll(dmc, DDR_MODE_DDR3);
 108
 109         writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
 110                 &dmc->concontrol);
 111
 112         /* Memory Channel Inteleaving Size */
 113         writel(mem->iv_size, &dmc->ivcontrol);
 114
 115         writel(mem->memconfig, &dmc->memconfig0);
 116         writel(mem->memconfig, &dmc->memconfig1);
 117         writel(mem->membaseconfig0, &dmc->membaseconfig0);
 118         writel(mem->membaseconfig1, &dmc->membaseconfig1);
 119
 120         /* Precharge Configuration */
 121         writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
 122                 &dmc->prechconfig);
 123
 124         /* Power Down mode Configuration */
 125         writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |
 126                 mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT,
 127                 &dmc->pwrdnconfig);
 128
 129         /* TimingRow, TimingData, TimingPower and Timingaref
 130          * values as per Memory AC parameters
 131          */
 132         writel(mem->timing_ref, &dmc->timingref);
 133         writel(mem->timing_row, &dmc->timingrow);
 134         writel(mem->timing_data, &dmc->timingdata);
 135         writel(mem->timing_power, &dmc->timingpower);
 136
 137         /* Send PALL command */
 138         dmc_config_prech(mem, dmc);
 139
 140         /* Send NOP, MRS and ZQINIT commands */
 141         dmc_config_mrs(mem, dmc);
 142
 143         if (mem->gate_leveling_enable) {
 144                 val = PHY_CON0_RESET_VAL;
 145                 val |= P0_CMD_EN;
 146                 writel(val, &phy0_ctrl->phy_con0);
 147                 writel(val, &phy1_ctrl->phy_con0);
 148
 149                 val = PHY_CON2_RESET_VAL;
 150                 val |= INIT_DESKEW_EN;
 151                 writel(val, &phy0_ctrl->phy_con2);
 152                 writel(val, &phy1_ctrl->phy_con2);
 153
 154                 val = PHY_CON0_RESET_VAL;
 155                 val |= P0_CMD_EN;
 156                 val |= BYTE_RDLVL_EN;
 157                 writel(val, &phy0_ctrl->phy_con0);
 158                 writel(val, &phy1_ctrl->phy_con0);
 159
 160                 val = (mem->ctrl_start_point <<
 161                                 PHY_CON12_CTRL_START_POINT_SHIFT) |
 162                         (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
 163                         (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
 164                         (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
 165                         (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
 166                 writel(val, &phy0_ctrl->phy_con12);
 167                 writel(val, &phy1_ctrl->phy_con12);
 168
 169                 val = PHY_CON2_RESET_VAL;
 170                 val |= INIT_DESKEW_EN;
 171                 val |= RDLVL_GATE_EN;
 172                 writel(val, &phy0_ctrl->phy_con2);
 173                 writel(val, &phy1_ctrl->phy_con2);
 174
 175                 val = PHY_CON0_RESET_VAL;
 176                 val |= P0_CMD_EN;
 177                 val |= BYTE_RDLVL_EN;
 178                 val |= CTRL_SHGATE;
 179                 writel(val, &phy0_ctrl->phy_con0);
 180                 writel(val, &phy1_ctrl->phy_con0);
 181
 182                 val = PHY_CON1_RESET_VAL;
 183                 val &= ~(CTRL_GATEDURADJ_MASK);
 184                 writel(val, &phy0_ctrl->phy_con1);
 185                 writel(val, &phy1_ctrl->phy_con1);
 186
 187                 writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config);
 188                 i = RDLVL_COMPLETE_TIMEOUT;
 189                 while ((readl(&dmc->phystatus) &
 190                         (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) !=
 191                         (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) {
 192                         /*
 193                          * TODO(waihong): Comment on how long this take to
 194                          * timeout
 195                          */
 196                         sdelay(100);
 197                         i--;
 198                 }
 199                 if (!i)
 200                         return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
 201                 writel(CTRL_RDLVL_GATE_DISABLE, &dmc->rdlvl_config);
 202
 203                 writel(0, &phy0_ctrl->phy_con14);
 204                 writel(0, &phy1_ctrl->phy_con14);
 205
 206                 val = (mem->ctrl_start_point <<
 207                                 PHY_CON12_CTRL_START_POINT_SHIFT) |
 208                         (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
 209                         (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
 210                         (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
 211                         (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
 212                         (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
 213                 writel(val, &phy0_ctrl->phy_con12);
 214                 writel(val, &phy1_ctrl->phy_con12);
 215
 216                 update_reset_dll(dmc, DDR_MODE_DDR3);
 217         }
 218
 219         /* Send PALL command */
 220         dmc_config_prech(mem, dmc);
 221
 222         writel(mem->memcontrol, &dmc->memcontrol);
 223
 224         /* Set DMC Concontrol and enable auto-refresh counter */
 225         writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
 226                 | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol);
 227         return 0;
 228 }