2 * Copyright (C) 2012 Samsung Electronics
4 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/dwmmc.h>
17 #include <asm/arch/gpio.h>
18 #include <asm/arch/mmc.h>
19 #include <asm/arch/pinmux.h>
20 #include <asm/arch/power.h>
21 #include <asm/arch/sromc.h>
22 #include <asm/arch/dp_info.h>
23 #include <power/pmic.h>
24 #include <power/max77686_pmic.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #ifdef CONFIG_USB_EHCI_EXYNOS
29 int board_usb_vbus_init(void)
31 struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
32 samsung_get_base_gpio_part1();
34 /* Enable VBUS power switch */
35 s5p_gpio_direction_output(&gpio1->x2, 6, 1);
37 /* VBUS turn ON time */
44 #ifdef CONFIG_SOUND_MAX98095
45 static void board_enable_audio_codec(void)
47 struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
48 samsung_get_base_gpio_part1();
50 /* Enable MAX98095 Codec */
51 s5p_gpio_direction_output(&gpio1->x1, 7, 1);
52 s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
58 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
60 #ifdef CONFIG_EXYNOS_SPI
63 #ifdef CONFIG_USB_EHCI_EXYNOS
64 board_usb_vbus_init();
66 #ifdef CONFIG_SOUND_MAX98095
67 board_enable_audio_codec();
77 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
78 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
79 gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
84 #if defined(CONFIG_POWER)
85 static int pmic_reg_update(struct pmic *p, int reg, uint regval)
90 ret = pmic_reg_read(p, reg, &val);
92 debug("%s: PMIC %d register read failed\n", __func__, reg);
96 ret = pmic_reg_write(p, reg, val);
98 debug("%s: PMIC %d register write failed\n", __func__, reg);
104 int power_init_board(void)
110 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
112 if (pmic_init(I2C_PMIC))
115 p = pmic_get("MAX77686_PMIC");
122 if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
125 if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
126 MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
130 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
131 MAX77686_BUCK1OUT_1_05V)) {
132 debug("%s: PMIC %d register write failed\n", __func__,
133 MAX77686_REG_PMIC_BUCK1OUT);
137 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
138 MAX77686_BUCK1CTRL_EN))
142 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
143 MAX77686_BUCK2DVS1_1_3V)) {
144 debug("%s: PMIC %d register write failed\n", __func__,
145 MAX77686_REG_PMIC_BUCK2DVS1);
149 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
150 MAX77686_BUCK2CTRL_ON))
154 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
155 MAX77686_BUCK3DVS1_1_0125V)) {
156 debug("%s: PMIC %d register write failed\n", __func__,
157 MAX77686_REG_PMIC_BUCK3DVS1);
161 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
162 MAX77686_BUCK3CTRL_ON))
166 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
167 MAX77686_BUCK4DVS1_1_2V)) {
168 debug("%s: PMIC %d register write failed\n", __func__,
169 MAX77686_REG_PMIC_BUCK4DVS1);
173 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
174 MAX77686_BUCK3CTRL_ON))
178 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
179 MAX77686_LD02CTRL1_1_5V | EN_LDO))
183 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
184 MAX77686_LD03CTRL1_1_8V | EN_LDO))
188 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
189 MAX77686_LD05CTRL1_1_8V | EN_LDO))
193 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
194 MAX77686_LD10CTRL1_1_8V | EN_LDO))
201 void dram_init_banksize(void)
205 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
206 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
207 size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
208 gd->bd->bi_dram[i].start = addr;
209 gd->bd->bi_dram[i].size = size;
213 int board_eth_init(bd_t *bis)
215 #ifdef CONFIG_SMC911X
216 u32 smc_bw_conf, smc_bc_conf;
217 struct fdt_sromc config;
218 fdt_addr_t base_addr;
220 /* Non-FDT configuration - bank number and timing parameters*/
221 config.bank = CONFIG_ENV_SROM_BANK;
224 config.timing[FDT_SROM_TACS] = 0x01;
225 config.timing[FDT_SROM_TCOS] = 0x01;
226 config.timing[FDT_SROM_TACC] = 0x06;
227 config.timing[FDT_SROM_TCOH] = 0x01;
228 config.timing[FDT_SROM_TAH] = 0x0C;
229 config.timing[FDT_SROM_TACP] = 0x09;
230 config.timing[FDT_SROM_PMC] = 0x01;
231 base_addr = CONFIG_SMC911X_BASE;
233 /* Ethernet needs data bus width of 16 bits */
234 if (config.width != 2) {
235 debug("%s: Unsupported bus width %d\n", __func__,
239 smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
240 | SROMC_BYTE_ENABLE(config.bank);
242 smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |\
243 SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\
244 SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\
245 SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\
246 SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |\
247 SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\
248 SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
250 /* Select and configure the SROMC bank */
251 exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
252 s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
253 return smc911x_initialize(0, base_addr);
258 #ifdef CONFIG_DISPLAY_BOARDINFO
261 printf("\nBoard: SMDK5250\n");
266 #ifdef CONFIG_GENERIC_MMC
267 int board_mmc_init(bd_t *bis)
269 int err, ret = 0, index, bus_width;
272 err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
274 debug("SDMMC0 not configured\n");
277 /*EMMC: dwmmc Channel-0 with 8 bit bus width */
279 base = samsung_get_base_mmc() + (0x10000 * index);
281 err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
283 debug("dwmmc Channel-0 init failed\n");
286 err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
288 debug("SDMMC2 not configured\n");
291 /*SD: dwmmc Channel-2 with 4 bit bus width */
293 base = samsung_get_base_mmc() + (0x10000 * index);
295 err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
297 debug("dwmmc Channel-2 init failed\n");
304 static int board_uart_init(void)
306 int err, uart_id, ret = 0;
308 for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
309 err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
311 debug("UART%d not configured\n",
312 (uart_id - PERIPH_ID_UART0));
319 void board_i2c_init(const void *blob)
323 for (i = 0; i < CONFIG_MAX_I2C_NUM; i++) {
324 exynos_pinmux_config((PERIPH_ID_I2C0 + i),
329 #ifdef CONFIG_BOARD_EARLY_INIT_F
330 int board_early_init_f(void)
333 err = board_uart_init();
335 debug("UART init failed\n");
338 #ifdef CONFIG_SYS_I2C_INIT_BOARD
339 board_i2c_init(NULL);
346 void exynos_cfg_lcd_gpio(void)
348 struct exynos5_gpio_part1 *gpio1 =
349 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
352 s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
353 s5p_gpio_set_value(&gpio1->b2, 0, 1);
356 s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
357 s5p_gpio_set_value(&gpio1->x1, 5, 1);
359 /* Set Hotplug detect for DP */
360 s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
363 void exynos_set_dp_phy(unsigned int onoff)
365 set_dp_phy_ctrl(onoff);
368 vidinfo_t panel_info = {
374 .vl_clkp = CONFIG_SYS_LOW,
375 .vl_hsp = CONFIG_SYS_LOW,
376 .vl_vsp = CONFIG_SYS_LOW,
377 .vl_dp = CONFIG_SYS_LOW,
378 .vl_bpix = 4, /* LCD_BPP = 2^4, for output conosle on LCD */
380 /* wDP panel timing infomation */
388 .vl_cmd_allow_len = 0xf,
391 .dual_lcd_enabled = 0,
396 .interface_mode = FIMD_RGB_INTERFACE,
400 static struct edp_device_info edp_info = {
413 .lt_status = DP_LT_NONE,
417 .bist_mode = DP_DISABLE,
418 .bist_pattern = NO_PATTERN,
419 .h_sync_polarity = 0,
420 .v_sync_polarity = 0,
422 .color_space = COLOR_RGB,
423 .dynamic_range = VESA,
424 .ycbcr_coeff = COLOR_YCBCR601,
425 .color_depth = COLOR_8,
429 static struct exynos_dp_platform_data dp_platform_data = {
430 .edp_dev_info = &edp_info,
433 void init_panel_info(vidinfo_t *vid)
435 vid->rgb_mode = MODE_RGB_P;
436 exynos_set_dp_platform_data(&dp_platform_data);