2 * Copyright (C) 2011 Samsung Electronics
3 * Heungjun Kim <riverful.kim@samsung.com>
4 * Kyungmin Park <kyungmin.park@samsung.com>
5 * Donghwa Lee <dh09.lee@samsung.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/cpu.h>
30 #include <asm/arch/gpio.h>
31 #include <asm/arch/mmc.h>
32 #include <asm/arch/clock.h>
33 #include <asm/arch/clk.h>
34 #include <asm/arch/mipi_dsim.h>
35 #include <asm/arch/watchdog.h>
36 #include <asm/arch/power.h>
37 #include <power/pmic.h>
38 #include <usb/s3c_udc.h>
39 #include <power/max8997_pmic.h>
41 #include <power/max8997_muic.h>
42 #include <power/battery.h>
43 #include <power/max17042_fg.h>
47 DECLARE_GLOBAL_DATA_PTR;
49 unsigned int board_rev;
51 #ifdef CONFIG_REVISION_TAG
52 u32 get_board_rev(void)
58 static void check_hw_revision(void);
60 static int hwrevision(int rev)
62 return (board_rev & 0xf) == rev;
65 struct s3c_plat_otg_data s5pc210_otg_data;
69 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
72 printf("HW Revision:\t0x%x\n", board_rev);
77 void i2c_init_board(void)
79 struct exynos4_gpio_part1 *gpio1 =
80 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
81 struct exynos4_gpio_part2 *gpio2 =
82 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
85 s5p_gpio_direction_output(&gpio1->b, 7, 1);
86 s5p_gpio_direction_output(&gpio1->b, 6, 1);
88 s5p_gpio_direction_output(&gpio2->y4, 0, 1);
89 s5p_gpio_direction_output(&gpio2->y4, 1, 1);
92 static void trats_low_power_mode(void)
94 struct exynos4_clock *clk =
95 (struct exynos4_clock *)samsung_get_base_clock();
96 struct exynos4_power *pwr =
97 (struct exynos4_power *)samsung_get_base_power();
99 /* Power down CORE1 */
100 /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */
101 writel(0x0, &pwr->arm_core1_configuration);
103 /* Change the APLL frequency */
104 /* ENABLE (1 enable) | LOCKED (1 locked) */
106 /* FSEL | MDIV | PDIV | SDIV */
107 /* [27] | [25:16] | [13:8] | [2:0] */
108 writel(0xa0c80604, &clk->apll_con0);
110 /* Change CPU0 clock divider */
111 /* CORE2_RATIO | APLL_RATIO | PCLK_DBG_RATIO | ATB_RATIO */
112 /* [30:28] | [26:24] | [22:20] | [18:16] */
113 /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO | CORE_RATIO */
114 /* [14:12] | [10:8] | [6:4] | [2:0] */
115 writel(0x00000100, &clk->div_cpu0);
117 /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */
118 while (readl(&clk->div_stat_cpu0) & 0x1111111)
121 /* Change clock divider ratio for DMC */
122 /* DMCP_RATIO | DMCD_RATIO */
123 /* [22:20] | [18:16] */
124 /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO | ACP_RATIO */
125 /* [14:12] | [10:8] | [6:4] | [2:0] */
126 writel(0x13113117, &clk->div_dmc0);
128 /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */
129 while (readl(&clk->div_stat_dmc0) & 0x11111111)
132 /* Turn off unnecessary power domains */
133 writel(0x0, &pwr->xxti_configuration); /* XXTI */
134 writel(0x0, &pwr->cam_configuration); /* CAM */
135 writel(0x0, &pwr->tv_configuration); /* TV */
136 writel(0x0, &pwr->mfc_configuration); /* MFC */
137 writel(0x0, &pwr->g3d_configuration); /* G3D */
138 writel(0x0, &pwr->gps_configuration); /* GPS */
139 writel(0x0, &pwr->gps_alive_configuration); /* GPS_ALIVE */
141 /* Turn off unnecessary clocks */
142 writel(0x0, &clk->gate_ip_cam); /* CAM */
143 writel(0x0, &clk->gate_ip_tv); /* TV */
144 writel(0x0, &clk->gate_ip_mfc); /* MFC */
145 writel(0x0, &clk->gate_ip_g3d); /* G3D */
146 writel(0x0, &clk->gate_ip_image); /* IMAGE */
147 writel(0x0, &clk->gate_ip_gps); /* GPS */
150 static int pmic_init_max8997(void)
152 struct pmic *p = pmic_get("MAX8997_PMIC");
159 /* BUCK1 VARM: 1.2V */
160 val = (1200000 - 650000) / 25000;
161 ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val);
162 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
163 ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val);
165 /* BUCK2 VINT: 1.1V */
166 val = (1100000 - 650000) / 25000;
167 ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val);
168 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
169 ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val);
172 /* BUCK3 G3D: 1.1V - OFF */
173 ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val);
175 ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val);
177 val = (1100000 - 750000) / 50000;
178 ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val);
180 /* BUCK4 CAMISP: 1.2V - OFF */
181 ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val);
183 ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val);
185 val = (1200000 - 650000) / 25000;
186 ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val);
188 /* BUCK5 VMEM: 1.2V */
189 val = (1200000 - 650000) / 25000;
190 for (i = 0; i < 8; i++)
191 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val);
193 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
194 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val);
196 /* BUCK6 CAM AF: 2.8V */
197 /* No Voltage Setting Register */
200 ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val);
202 /* BUCK7 VCC_SUB: 2.0V */
203 val = (2000000 - 750000) / 50000;
204 ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val);
206 /* LDO1 VADC: 3.3V */
207 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
208 ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val);
210 /* LDO1 Disable active discharging */
211 ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val);
213 ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val);
215 /* LDO2 VALIVE: 1.1V */
216 val = max8997_reg_ldo(1100000) | EN_LDO;
217 ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val);
219 /* LDO3 VUSB/MIPI: 1.1V */
220 val = max8997_reg_ldo(1100000) | DIS_LDO; /* OFF */
221 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val);
223 /* LDO4 VMIPI: 1.8V */
224 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
225 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val);
227 /* LDO5 VHSIC: 1.2V */
228 val = max8997_reg_ldo(1200000) | DIS_LDO; /* OFF */
229 ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val);
231 /* LDO6 VCC_1.8V_PDA: 1.8V */
232 val = max8997_reg_ldo(1800000) | EN_LDO;
233 ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val);
235 /* LDO7 CAM_ISP: 1.8V */
236 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
237 ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val);
239 /* LDO8 VDAC/VUSB: 3.3V */
240 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
241 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val);
243 /* LDO9 VCC_2.8V_PDA: 2.8V */
244 val = max8997_reg_ldo(2800000) | EN_LDO;
245 ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val);
247 /* LDO10 VPLL: 1.1V */
248 val = max8997_reg_ldo(1100000) | EN_LDO;
249 ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val);
251 /* LDO11 TOUCH: 2.8V */
252 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
253 ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val);
255 /* LDO12 VTCAM: 1.8V */
256 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
257 ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val);
259 /* LDO13 VCC_3.0_LCD: 3.0V */
260 val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */
261 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val);
263 /* LDO14 MOTOR: 3.0V */
264 val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */
265 ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val);
267 /* LDO15 LED_A: 2.8V */
268 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
269 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val);
271 /* LDO16 CAM_SENSOR: 1.8V */
272 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
273 ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val);
275 /* LDO17 VTF: 2.8V */
276 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
277 ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val);
279 /* LDO18 TOUCH_LED 3.3V */
280 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
281 ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val);
283 /* LDO21 VDDQ: 1.2V */
284 val = max8997_reg_ldo(1200000) | EN_LDO;
285 ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val);
287 /* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */
288 val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) |
289 ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2;
290 ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val);
293 puts("MAX8997 PMIC setting error!\n");
299 int power_init_board(void)
303 ret = pmic_init(I2C_5);
304 ret |= pmic_init_max8997();
305 ret |= power_fg_init(I2C_9);
306 ret |= power_muic_init(I2C_5);
307 ret |= power_bat_init(0);
316 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
317 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
322 void dram_init_banksize(void)
324 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
325 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
326 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
327 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
330 static unsigned int get_hw_revision(void)
332 struct exynos4_gpio_part1 *gpio =
333 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
337 /* hw_rev[3:0] == GPE1[3:0] */
338 for (i = 0; i < 4; i++) {
339 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
340 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
345 for (i = 0; i < 4; i++)
346 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
348 debug("hwrev 0x%x\n", hwrev);
353 static void check_hw_revision(void)
357 hwrev = get_hw_revision();
362 #ifdef CONFIG_DISPLAY_BOARDINFO
365 puts("Board:\tTRATS\n");
370 #ifdef CONFIG_GENERIC_MMC
371 int board_mmc_init(bd_t *bis)
373 struct exynos4_gpio_part2 *gpio =
374 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
377 /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
378 s5p_gpio_direction_output(&gpio->k0, 2, 1);
379 s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
383 * SDR 8-bit@48MHz at MMC0
384 * GPK0[0] SD_0_CLK(2)
385 * GPK0[1] SD_0_CMD(2)
386 * GPK0[2] SD_0_CDn -> Not used
387 * GPK0[3:6] SD_0_DATA[0:3](2)
388 * GPK1[3:6] SD_0_DATA[0:3](3)
390 * DDR 4-bit@26MHz at MMC4
391 * GPK0[0] SD_4_CLK(3)
392 * GPK0[1] SD_4_CMD(3)
393 * GPK0[2] SD_4_CDn -> Not used
394 * GPK0[3:6] SD_4_DATA[0:3](3)
395 * GPK1[3:6] SD_4_DATA[4:7](4)
397 for (i = 0; i < 7; i++) {
400 /* GPK0[0:6] special function 2 */
401 s5p_gpio_cfg_pin(&gpio->k0, i, 0x2);
402 /* GPK0[0:6] pull disable */
403 s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE);
404 /* GPK0[0:6] drv 4x */
405 s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X);
408 for (i = 3; i < 7; i++) {
409 /* GPK1[3:6] special function 3 */
410 s5p_gpio_cfg_pin(&gpio->k1, i, 0x3);
411 /* GPK1[3:6] pull disable */
412 s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE);
413 /* GPK1[3:6] drv 4x */
414 s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X);
419 * mmc0 : eMMC (8-bit buswidth)
420 * mmc2 : SD card (4-bit buswidth)
422 err = s5p_mmc_init(0, 8);
425 s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
426 s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
429 * Check the T-flash detect pin
430 * GPX3[4] T-flash detect pin
432 if (!s5p_gpio_get_value(&gpio->x3, 4)) {
435 * GPK2[0] SD_2_CLK(2)
436 * GPK2[1] SD_2_CMD(2)
437 * GPK2[2] SD_2_CDn -> Not used
438 * GPK2[3:6] SD_2_DATA[0:3](2)
440 for (i = 0; i < 7; i++) {
443 /* GPK2[0:6] special function 2 */
444 s5p_gpio_cfg_pin(&gpio->k2, i, 0x2);
445 /* GPK2[0:6] pull disable */
446 s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE);
447 /* GPK2[0:6] drv 4x */
448 s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X);
450 err = s5p_mmc_init(2, 4);
457 #ifdef CONFIG_USB_GADGET
458 static int s5pc210_phy_control(int on)
462 struct pmic *p = pmic_get("MAX8997_PMIC");
470 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
472 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
473 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
475 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
476 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
478 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
479 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
481 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
482 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
483 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
484 ENSAFEOUT1, LDO_OFF);
488 puts("MAX8997 LDO setting error!\n");
495 struct s3c_plat_otg_data s5pc210_otg_data = {
496 .phy_control = s5pc210_phy_control,
497 .regs_phy = EXYNOS4_USBPHY_BASE,
498 .regs_otg = EXYNOS4_USBOTG_BASE,
499 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
500 .usb_flags = PHY0_SLEEP,
503 void board_usb_init(void)
505 debug("USB_udc_probe\n");
506 s3c_udc_probe(&s5pc210_otg_data);
510 static void pmic_reset(void)
512 struct exynos4_gpio_part2 *gpio =
513 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
515 s5p_gpio_direction_output(&gpio->x0, 7, 1);
516 s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
519 static void board_clock_init(void)
521 struct exynos4_clock *clk =
522 (struct exynos4_clock *)samsung_get_base_clock();
524 writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
525 writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
526 writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
527 writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
529 writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
530 writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
531 writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
532 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
533 writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
534 writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
535 writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
536 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
537 writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
538 writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
539 writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
540 writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
542 writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
543 writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
544 writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
545 writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
546 writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
547 writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
548 writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
549 writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
550 writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
551 writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
552 writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
553 writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
555 writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
556 writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
557 writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
558 writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
559 writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
560 writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
561 writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
562 writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
563 writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
564 writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
565 writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
566 writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
569 static void board_power_init(void)
571 struct exynos4_power *pwr =
572 (struct exynos4_power *)samsung_get_base_power();
575 writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
578 writel(0, (unsigned int)&pwr->cam_configuration);
579 writel(0, (unsigned int)&pwr->tv_configuration);
580 writel(0, (unsigned int)&pwr->mfc_configuration);
581 writel(0, (unsigned int)&pwr->g3d_configuration);
582 writel(0, (unsigned int)&pwr->lcd1_configuration);
583 writel(0, (unsigned int)&pwr->gps_configuration);
584 writel(0, (unsigned int)&pwr->gps_alive_configuration);
587 static void board_uart_init(void)
589 struct exynos4_gpio_part1 *gpio1 =
590 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
591 struct exynos4_gpio_part2 *gpio2 =
592 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
597 * GPA1CON[0] = UART_2_RXD(2)
598 * GPA1CON[1] = UART_2_TXD(2)
599 * GPA1CON[2] = I2C_3_SDA (3)
600 * GPA1CON[3] = I2C_3_SCL (3)
603 for (i = 0; i < 4; i++) {
604 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
605 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
608 /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
609 s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
610 s5p_gpio_direction_output(&gpio2->y4, 7, 1);
613 int board_early_init_f(void)
624 static void lcd_reset(void)
626 struct exynos4_gpio_part2 *gpio2 =
627 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
629 s5p_gpio_direction_output(&gpio2->y4, 5, 1);
631 s5p_gpio_direction_output(&gpio2->y4, 5, 0);
633 s5p_gpio_direction_output(&gpio2->y4, 5, 1);
636 static int lcd_power(void)
639 struct pmic *p = pmic_get("MAX8997_PMIC");
646 /* LDO15 voltage: 2.2v */
647 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
648 /* LDO13 voltage: 3.0v */
649 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
652 puts("MAX8997 LDO setting error!\n");
659 static struct mipi_dsim_config dsim_config = {
660 .e_interface = DSIM_VIDEO,
661 .e_virtual_ch = DSIM_VIRTUAL_CH_0,
662 .e_pixel_format = DSIM_24BPP_888,
663 .e_burst_mode = DSIM_BURST_SYNC_EVENT,
664 .e_no_data_lane = DSIM_DATA_LANE_4,
665 .e_byte_clk = DSIM_PLL_OUT_DIV8,
672 /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
673 .pll_stable_time = 500,
675 /* escape clk : 10MHz */
676 .esc_clk = 20 * 1000000,
678 /* stop state holding counter after bta change count 0 ~ 0xfff */
679 .stop_holding_cnt = 0x7ff,
680 /* bta timeout 0 ~ 0xff */
682 /* lp rx timeout 0 ~ 0xffff */
683 .rx_timeout = 0xffff,
686 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = {
687 .lcd_panel_info = NULL,
688 .dsim_config = &dsim_config,
691 static struct mipi_dsim_lcd_device mipi_lcd_device = {
695 .platform_data = (void *)&s6e8ax0_platform_data,
698 static int mipi_power(void)
701 struct pmic *p = pmic_get("MAX8997_PMIC");
708 /* LDO3 voltage: 1.1v */
709 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
710 /* LDO4 voltage: 1.8v */
711 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
714 puts("MAX8997 LDO setting error!\n");
721 vidinfo_t panel_info = {
727 .vl_clkp = CONFIG_SYS_HIGH,
728 .vl_hsp = CONFIG_SYS_LOW,
729 .vl_vsp = CONFIG_SYS_LOW,
730 .vl_dp = CONFIG_SYS_LOW,
731 .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */
733 /* s6e8ax0 Panel infomation */
741 .vl_cmd_allow_len = 0xf,
745 .backlight_on = NULL,
746 .lcd_power_on = NULL, /* lcd_power_on in mipi dsi driver */
747 .reset_lcd = lcd_reset,
748 .dual_lcd_enabled = 0,
753 .interface_mode = FIMD_RGB_INTERFACE,
757 void init_panel_info(vidinfo_t *vid)
760 vid->resolution = HD_RESOLUTION,
761 vid->rgb_mode = MODE_RGB_P,
764 get_tizen_logo_info(vid);
768 mipi_lcd_device.reverse_panel = 1;
770 strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
771 s6e8ax0_platform_data.lcd_power = lcd_power;
772 s6e8ax0_platform_data.mipi_power = mipi_power;
773 s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl;
774 s6e8ax0_platform_data.lcd_panel_info = (void *)vid;
775 exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
777 exynos_set_dsim_platform_data(&s6e8ax0_platform_data);
779 setenv("lcdinfo", "lcd=s6e8ax0");