board/samsung/trats/trats.c

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics
   3  * Heungjun Kim <riverful.kim@samsung.com>
   4  * Kyungmin Park <kyungmin.park@samsung.com>
   5  * Donghwa Lee <dh09.lee@samsung.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <lcd.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/cpu.h>
  30 #include <asm/arch/gpio.h>
  31 #include <asm/arch/mmc.h>
  32 #include <asm/arch/clock.h>
  33 #include <asm/arch/clk.h>
  34 #include <asm/arch/mipi_dsim.h>
  35 #include <asm/arch/watchdog.h>
  36 #include <asm/arch/power.h>
  37 #include <power/pmic.h>
  38 #include <usb/s3c_udc.h>
  39 #include <power/max8997_pmic.h>
  40 #include <libtizen.h>
  41 #include <power/max8997_muic.h>
  42 #include <power/max17042_fg.h>
  43
  44 #include "setup.h"
  45
  46 DECLARE_GLOBAL_DATA_PTR;
  47
  48 unsigned int board_rev;
  49
  50 #ifdef CONFIG_REVISION_TAG
  51 u32 get_board_rev(void)
  52 {
  53         return board_rev;
  54 }
  55 #endif
  56
  57 static void check_hw_revision(void);
  58
  59 static int hwrevision(int rev)
  60 {
  61         return (board_rev & 0xf) == rev;
  62 }
  63
  64 struct s3c_plat_otg_data s5pc210_otg_data;
  65
  66 int board_init(void)
  67 {
  68         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  69
  70         check_hw_revision();
  71         printf("HW Revision:\t0x%x\n", board_rev);
  72
  73         return 0;
  74 }
  75
  76 void i2c_init_board(void)
  77 {
  78         struct exynos4_gpio_part1 *gpio1 =
  79                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
  80         struct exynos4_gpio_part2 *gpio2 =
  81                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
  82
  83         /* I2C_5 -> PMIC */
  84         s5p_gpio_direction_output(&gpio1->b, 7, 1);
  85         s5p_gpio_direction_output(&gpio1->b, 6, 1);
  86         /* I2C_9 -> FG */
  87         s5p_gpio_direction_output(&gpio2->y4, 0, 1);
  88         s5p_gpio_direction_output(&gpio2->y4, 1, 1);
  89 }
  90
  91 static int pmic_init_max8997(void)
  92 {
  93         struct pmic *p = pmic_get("MAX8997_PMIC");
  94         int i = 0, ret = 0;
  95         u32 val;
  96
  97         if (pmic_probe(p))
  98                 return -1;
  99
 100         /* BUCK1 VARM: 1.2V */
 101         val = (1200000 - 650000) / 25000;
 102         ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val);
 103         val = ENBUCK | ACTIVE_DISCHARGE;                /* DVS OFF */
 104         ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val);
 105
 106         /* BUCK2 VINT: 1.1V */
 107         val = (1100000 - 650000) / 25000;
 108         ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val);
 109         val = ENBUCK | ACTIVE_DISCHARGE;                /* DVS OFF */
 110         ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val);
 111
 112
 113         /* BUCK3 G3D: 1.1V - OFF */
 114         ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val);
 115         val &= ~ENBUCK;
 116         ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val);
 117
 118         val = (1100000 - 750000) / 50000;
 119         ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val);
 120
 121         /* BUCK4 CAMISP: 1.2V - OFF */
 122         ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val);
 123         val &= ~ENBUCK;
 124         ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val);
 125
 126         val = (1200000 - 650000) / 25000;
 127         ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val);
 128
 129         /* BUCK5 VMEM: 1.2V */
 130         val = (1200000 - 650000) / 25000;
 131         for (i = 0; i < 8; i++)
 132                 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val);
 133
 134         val = ENBUCK | ACTIVE_DISCHARGE;                /* DVS OFF */
 135         ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val);
 136
 137         /* BUCK6 CAM AF: 2.8V */
 138         /* No Voltage Setting Register */
 139         /* GNSLCT 3.0X */
 140         val = GNSLCT;
 141         ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val);
 142
 143         /* BUCK7 VCC_SUB: 2.0V */
 144         val = (2000000 - 750000) / 50000;
 145         ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val);
 146
 147         /* LDO1 VADC: 3.3V */
 148         val = max8997_reg_ldo(3300000) | DIS_LDO;       /* OFF */
 149         ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val);
 150
 151         /* LDO1 Disable active discharging */
 152         ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val);
 153         val &= ~LDO_ADE;
 154         ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val);
 155
 156         /* LDO2 VALIVE: 1.1V */
 157         val = max8997_reg_ldo(1100000) | EN_LDO;
 158         ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val);
 159
 160         /* LDO3 VUSB/MIPI: 1.1V */
 161         val = max8997_reg_ldo(1100000) | DIS_LDO;       /* OFF */
 162         ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val);
 163
 164         /* LDO4 VMIPI: 1.8V */
 165         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 166         ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val);
 167
 168         /* LDO5 VHSIC: 1.2V */
 169         val = max8997_reg_ldo(1200000) | DIS_LDO;       /* OFF */
 170         ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val);
 171
 172         /* LDO6 VCC_1.8V_PDA: 1.8V */
 173         val = max8997_reg_ldo(1800000) | EN_LDO;
 174         ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val);
 175
 176         /* LDO7 CAM_ISP: 1.8V */
 177         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 178         ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val);
 179
 180         /* LDO8 VDAC/VUSB: 3.3V */
 181         val = max8997_reg_ldo(3300000) | DIS_LDO;       /* OFF */
 182         ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val);
 183
 184         /* LDO9 VCC_2.8V_PDA: 2.8V */
 185         val = max8997_reg_ldo(2800000) | EN_LDO;
 186         ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val);
 187
 188         /* LDO10 VPLL: 1.1V */
 189         val = max8997_reg_ldo(1100000) | EN_LDO;
 190         ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val);
 191
 192         /* LDO11 TOUCH: 2.8V */
 193         val = max8997_reg_ldo(2800000) | DIS_LDO;       /* OFF */
 194         ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val);
 195
 196         /* LDO12 VTCAM: 1.8V */
 197         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 198         ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val);
 199
 200         /* LDO13 VCC_3.0_LCD: 3.0V */
 201         val = max8997_reg_ldo(3000000) | DIS_LDO;       /* OFF */
 202         ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val);
 203
 204         /* LDO14 MOTOR: 3.0V */
 205         val = max8997_reg_ldo(3000000) | DIS_LDO;       /* OFF */
 206         ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val);
 207
 208         /* LDO15 LED_A: 2.8V */
 209         val = max8997_reg_ldo(2800000) | DIS_LDO;       /* OFF */
 210         ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val);
 211
 212         /* LDO16 CAM_SENSOR: 1.8V */
 213         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 214         ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val);
 215
 216         /* LDO17 VTF: 2.8V */
 217         val = max8997_reg_ldo(2800000) | DIS_LDO;       /* OFF */
 218         ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val);
 219
 220         /* LDO18 TOUCH_LED 3.3V */
 221         val = max8997_reg_ldo(3300000) | DIS_LDO;       /* OFF */
 222         ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val);
 223
 224         /* LDO21 VDDQ: 1.2V */
 225         val = max8997_reg_ldo(1200000) | EN_LDO;
 226         ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val);
 227
 228         /* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */
 229         val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) |
 230                 ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2;
 231         ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val);
 232
 233         if (ret) {
 234                 puts("MAX8997 PMIC setting error!\n");
 235                 return -1;
 236         }
 237         return 0;
 238 }
 239
 240 int power_init_board(void)
 241 {
 242         int ret;
 243
 244         ret = pmic_init(I2C_5);
 245         ret |= pmic_init_max8997();
 246         ret |= power_fg_init(I2C_9);
 247         ret |= power_muic_init(I2C_5);
 248         if (ret)
 249                 return ret;
 250
 251         return 0;
 252 }
 253
 254 int dram_init(void)
 255 {
 256         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
 257                 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
 258
 259         return 0;
 260 }
 261
 262 void dram_init_banksize(void)
 263 {
 264         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 265         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 266         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 267         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 268 }
 269
 270 static unsigned int get_hw_revision(void)
 271 {
 272         struct exynos4_gpio_part1 *gpio =
 273                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
 274         int hwrev = 0;
 275         int i;
 276
 277         /* hw_rev[3:0] == GPE1[3:0] */
 278         for (i = 0; i < 4; i++) {
 279                 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
 280                 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
 281         }
 282
 283         udelay(1);
 284
 285         for (i = 0; i < 4; i++)
 286                 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
 287
 288         debug("hwrev 0x%x\n", hwrev);
 289
 290         return hwrev;
 291 }
 292
 293 static void check_hw_revision(void)
 294 {
 295         int hwrev;
 296
 297         hwrev = get_hw_revision();
 298
 299         board_rev |= hwrev;
 300 }
 301
 302 #ifdef CONFIG_DISPLAY_BOARDINFO
 303 int checkboard(void)
 304 {
 305         puts("Board:\tTRATS\n");
 306         return 0;
 307 }
 308 #endif
 309
 310 #ifdef CONFIG_GENERIC_MMC
 311 int board_mmc_init(bd_t *bis)
 312 {
 313         struct exynos4_gpio_part2 *gpio =
 314                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 315         int i, err;
 316
 317         /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
 318         s5p_gpio_direction_output(&gpio->k0, 2, 1);
 319         s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
 320
 321         /*
 322          * eMMC GPIO:
 323          * SDR 8-bit@48MHz at MMC0
 324          * GPK0[0]      SD_0_CLK(2)
 325          * GPK0[1]      SD_0_CMD(2)
 326          * GPK0[2]      SD_0_CDn        -> Not used
 327          * GPK0[3:6]    SD_0_DATA[0:3](2)
 328          * GPK1[3:6]    SD_0_DATA[0:3](3)
 329          *
 330          * DDR 4-bit@26MHz at MMC4
 331          * GPK0[0]      SD_4_CLK(3)
 332          * GPK0[1]      SD_4_CMD(3)
 333          * GPK0[2]      SD_4_CDn        -> Not used
 334          * GPK0[3:6]    SD_4_DATA[0:3](3)
 335          * GPK1[3:6]    SD_4_DATA[4:7](4)
 336          */
 337         for (i = 0; i < 7; i++) {
 338                 if (i == 2)
 339                         continue;
 340                 /* GPK0[0:6] special function 2 */
 341                 s5p_gpio_cfg_pin(&gpio->k0, i, 0x2);
 342                 /* GPK0[0:6] pull disable */
 343                 s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE);
 344                 /* GPK0[0:6] drv 4x */
 345                 s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X);
 346         }
 347
 348         for (i = 3; i < 7; i++) {
 349                 /* GPK1[3:6] special function 3 */
 350                 s5p_gpio_cfg_pin(&gpio->k1, i, 0x3);
 351                 /* GPK1[3:6] pull disable */
 352                 s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE);
 353                 /* GPK1[3:6] drv 4x */
 354                 s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X);
 355         }
 356
 357         /*
 358          * MMC device init
 359          * mmc0  : eMMC (8-bit buswidth)
 360          * mmc2  : SD card (4-bit buswidth)
 361          */
 362         err = s5p_mmc_init(0, 8);
 363
 364         /* T-flash detect */
 365         s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
 366         s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
 367
 368         /*
 369          * Check the T-flash  detect pin
 370          * GPX3[4] T-flash detect pin
 371          */
 372         if (!s5p_gpio_get_value(&gpio->x3, 4)) {
 373                 /*
 374                  * SD card GPIO:
 375                  * GPK2[0]      SD_2_CLK(2)
 376                  * GPK2[1]      SD_2_CMD(2)
 377                  * GPK2[2]      SD_2_CDn        -> Not used
 378                  * GPK2[3:6]    SD_2_DATA[0:3](2)
 379                  */
 380                 for (i = 0; i < 7; i++) {
 381                         if (i == 2)
 382                                 continue;
 383                         /* GPK2[0:6] special function 2 */
 384                         s5p_gpio_cfg_pin(&gpio->k2, i, 0x2);
 385                         /* GPK2[0:6] pull disable */
 386                         s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE);
 387                         /* GPK2[0:6] drv 4x */
 388                         s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X);
 389                 }
 390                 err = s5p_mmc_init(2, 4);
 391         }
 392
 393         return err;
 394 }
 395 #endif
 396
 397 #ifdef CONFIG_USB_GADGET
 398 static int s5pc210_phy_control(int on)
 399 {
 400         int ret = 0;
 401         u32 val = 0;
 402         struct pmic *p = pmic_get("MAX8997_PMIC");
 403         if (!p)
 404                 return -ENODEV;
 405
 406         if (pmic_probe(p))
 407                 return -1;
 408
 409         if (on) {
 410                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
 411                                       ENSAFEOUT1, LDO_ON);
 412                 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
 413                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
 414
 415                 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
 416                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
 417         } else {
 418                 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
 419                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
 420
 421                 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
 422                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
 423                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
 424                                       ENSAFEOUT1, LDO_OFF);
 425         }
 426
 427         if (ret) {
 428                 puts("MAX8997 LDO setting error!\n");
 429                 return -1;
 430         }
 431
 432         return 0;
 433 }
 434
 435 struct s3c_plat_otg_data s5pc210_otg_data = {
 436         .phy_control    = s5pc210_phy_control,
 437         .regs_phy       = EXYNOS4_USBPHY_BASE,
 438         .regs_otg       = EXYNOS4_USBOTG_BASE,
 439         .usb_phy_ctrl   = EXYNOS4_USBPHY_CONTROL,
 440         .usb_flags      = PHY0_SLEEP,
 441 };
 442
 443 void board_usb_init(void)
 444 {
 445         debug("USB_udc_probe\n");
 446         s3c_udc_probe(&s5pc210_otg_data);
 447 }
 448 #endif
 449
 450 static void pmic_reset(void)
 451 {
 452         struct exynos4_gpio_part2 *gpio =
 453                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 454
 455         s5p_gpio_direction_output(&gpio->x0, 7, 1);
 456         s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
 457 }
 458
 459 static void board_clock_init(void)
 460 {
 461         struct exynos4_clock *clk =
 462                 (struct exynos4_clock *)samsung_get_base_clock();
 463
 464         writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
 465         writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
 466         writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
 467         writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
 468
 469         writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
 470         writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
 471         writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
 472         writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
 473         writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
 474         writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
 475         writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
 476         writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
 477         writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
 478         writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
 479         writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
 480         writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
 481
 482         writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
 483         writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
 484         writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
 485         writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
 486         writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
 487         writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
 488         writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
 489         writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
 490         writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
 491         writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
 492         writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
 493         writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
 494
 495         writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
 496         writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
 497         writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
 498         writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
 499         writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
 500         writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
 501         writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
 502         writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
 503         writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
 504         writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
 505         writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
 506         writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
 507 }
 508
 509 static void board_power_init(void)
 510 {
 511         struct exynos4_power *pwr =
 512                 (struct exynos4_power *)samsung_get_base_power();
 513
 514         /* PS HOLD */
 515         writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
 516
 517         /* Set power down */
 518         writel(0, (unsigned int)&pwr->cam_configuration);
 519         writel(0, (unsigned int)&pwr->tv_configuration);
 520         writel(0, (unsigned int)&pwr->mfc_configuration);
 521         writel(0, (unsigned int)&pwr->g3d_configuration);
 522         writel(0, (unsigned int)&pwr->lcd1_configuration);
 523         writel(0, (unsigned int)&pwr->gps_configuration);
 524         writel(0, (unsigned int)&pwr->gps_alive_configuration);
 525 }
 526
 527 static void board_uart_init(void)
 528 {
 529         struct exynos4_gpio_part1 *gpio1 =
 530                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
 531         struct exynos4_gpio_part2 *gpio2 =
 532                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 533         int i;
 534
 535         /*
 536          * UART2 GPIOs
 537          * GPA1CON[0] = UART_2_RXD(2)
 538          * GPA1CON[1] = UART_2_TXD(2)
 539          * GPA1CON[2] = I2C_3_SDA (3)
 540          * GPA1CON[3] = I2C_3_SCL (3)
 541          */
 542
 543         for (i = 0; i < 4; i++) {
 544                 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
 545                 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
 546         }
 547
 548         /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
 549         s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
 550         s5p_gpio_direction_output(&gpio2->y4, 7, 1);
 551 }
 552
 553 int board_early_init_f(void)
 554 {
 555         wdt_stop();
 556         pmic_reset();
 557         board_clock_init();
 558         board_uart_init();
 559         board_power_init();
 560
 561         return 0;
 562 }
 563
 564 static void lcd_reset(void)
 565 {
 566         struct exynos4_gpio_part2 *gpio2 =
 567                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 568
 569         s5p_gpio_direction_output(&gpio2->y4, 5, 1);
 570         udelay(10000);
 571         s5p_gpio_direction_output(&gpio2->y4, 5, 0);
 572         udelay(10000);
 573         s5p_gpio_direction_output(&gpio2->y4, 5, 1);
 574 }
 575
 576 static int lcd_power(void)
 577 {
 578         int ret = 0;
 579         struct pmic *p = pmic_get("MAX8997_PMIC");
 580         if (!p)
 581                 return -ENODEV;
 582
 583         if (pmic_probe(p))
 584                 return 0;
 585
 586         /* LDO15 voltage: 2.2v */
 587         ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
 588         /* LDO13 voltage: 3.0v */
 589         ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
 590
 591         if (ret) {
 592                 puts("MAX8997 LDO setting error!\n");
 593                 return -1;
 594         }
 595
 596         return 0;
 597 }
 598
 599 static struct mipi_dsim_config dsim_config = {
 600         .e_interface            = DSIM_VIDEO,
 601         .e_virtual_ch           = DSIM_VIRTUAL_CH_0,
 602         .e_pixel_format         = DSIM_24BPP_888,
 603         .e_burst_mode           = DSIM_BURST_SYNC_EVENT,
 604         .e_no_data_lane         = DSIM_DATA_LANE_4,
 605         .e_byte_clk             = DSIM_PLL_OUT_DIV8,
 606         .hfp                    = 1,
 607
 608         .p                      = 3,
 609         .m                      = 120,
 610         .s                      = 1,
 611
 612         /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
 613         .pll_stable_time        = 500,
 614
 615         /* escape clk : 10MHz */
 616         .esc_clk                = 20 * 1000000,
 617
 618         /* stop state holding counter after bta change count 0 ~ 0xfff */
 619         .stop_holding_cnt       = 0x7ff,
 620         /* bta timeout 0 ~ 0xff */
 621         .bta_timeout            = 0xff,
 622         /* lp rx timeout 0 ~ 0xffff */
 623         .rx_timeout             = 0xffff,
 624 };
 625
 626 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = {
 627         .lcd_panel_info = NULL,
 628         .dsim_config = &dsim_config,
 629 };
 630
 631 static struct mipi_dsim_lcd_device mipi_lcd_device = {
 632         .name   = "s6e8ax0",
 633         .id     = -1,
 634         .bus_id = 0,
 635         .platform_data  = (void *)&s6e8ax0_platform_data,
 636 };
 637
 638 static int mipi_power(void)
 639 {
 640         int ret = 0;
 641         struct pmic *p = pmic_get("MAX8997_PMIC");
 642         if (!p)
 643                 return -ENODEV;
 644
 645         if (pmic_probe(p))
 646                 return 0;
 647
 648         /* LDO3 voltage: 1.1v */
 649         ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
 650         /* LDO4 voltage: 1.8v */
 651         ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
 652
 653         if (ret) {
 654                 puts("MAX8997 LDO setting error!\n");
 655                 return -1;
 656         }
 657
 658         return 0;
 659 }
 660
 661 vidinfo_t panel_info = {
 662         .vl_freq        = 60,
 663         .vl_col         = 720,
 664         .vl_row         = 1280,
 665         .vl_width       = 720,
 666         .vl_height      = 1280,
 667         .vl_clkp        = CONFIG_SYS_HIGH,
 668         .vl_hsp         = CONFIG_SYS_LOW,
 669         .vl_vsp         = CONFIG_SYS_LOW,
 670         .vl_dp          = CONFIG_SYS_LOW,
 671         .vl_bpix        = 5,    /* Bits per pixel, 2^5 = 32 */
 672
 673         /* s6e8ax0 Panel infomation */
 674         .vl_hspw        = 5,
 675         .vl_hbpd        = 10,
 676         .vl_hfpd        = 10,
 677
 678         .vl_vspw        = 2,
 679         .vl_vbpd        = 1,
 680         .vl_vfpd        = 13,
 681         .vl_cmd_allow_len = 0xf,
 682
 683         .win_id         = 3,
 684         .cfg_gpio       = NULL,
 685         .backlight_on   = NULL,
 686         .lcd_power_on   = NULL, /* lcd_power_on in mipi dsi driver */
 687         .reset_lcd      = lcd_reset,
 688         .dual_lcd_enabled = 0,
 689
 690         .init_delay     = 0,
 691         .power_on_delay = 0,
 692         .reset_delay    = 0,
 693         .interface_mode = FIMD_RGB_INTERFACE,
 694         .mipi_enabled   = 1,
 695 };
 696
 697 void init_panel_info(vidinfo_t *vid)
 698 {
 699         vid->logo_on    = 1,
 700         vid->resolution = HD_RESOLUTION,
 701         vid->rgb_mode   = MODE_RGB_P,
 702
 703 #ifdef CONFIG_TIZEN
 704         get_tizen_logo_info(vid);
 705 #endif
 706
 707         if (hwrevision(2))
 708                 mipi_lcd_device.reverse_panel = 1;
 709
 710         strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
 711         s6e8ax0_platform_data.lcd_power = lcd_power;
 712         s6e8ax0_platform_data.mipi_power = mipi_power;
 713         s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl;
 714         s6e8ax0_platform_data.lcd_panel_info = (void *)vid;
 715         exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
 716         s6e8ax0_init();
 717         exynos_set_dsim_platform_data(&s6e8ax0_platform_data);
 718
 719         setenv("lcdinfo", "lcd=s6e8ax0");
 720 }