board/samsung/trats/trats.c

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics
   3  * Heungjun Kim <riverful.kim@samsung.com>
   4  * Kyungmin Park <kyungmin.park@samsung.com>
   5  * Donghwa Lee <dh09.lee@samsung.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <lcd.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/cpu.h>
  30 #include <asm/arch/gpio.h>
  31 #include <asm/arch/mmc.h>
  32 #include <asm/arch/clock.h>
  33 #include <asm/arch/clk.h>
  34 #include <asm/arch/mipi_dsim.h>
  35 #include <asm/arch/watchdog.h>
  36 #include <asm/arch/power.h>
  37 #include <power/pmic.h>
  38 #include <usb/s3c_udc.h>
  39 #include <power/max8997_pmic.h>
  40 #include <libtizen.h>
  41 #include <power/max8997_muic.h>
  42 #include <power/battery.h>
  43 #include <power/max17042_fg.h>
  44
  45 #include "setup.h"
  46
  47 DECLARE_GLOBAL_DATA_PTR;
  48
  49 unsigned int board_rev;
  50
  51 #ifdef CONFIG_REVISION_TAG
  52 u32 get_board_rev(void)
  53 {
  54         return board_rev;
  55 }
  56 #endif
  57
  58 static void check_hw_revision(void);
  59
  60 static int hwrevision(int rev)
  61 {
  62         return (board_rev & 0xf) == rev;
  63 }
  64
  65 struct s3c_plat_otg_data s5pc210_otg_data;
  66
  67 int board_init(void)
  68 {
  69         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  70
  71         check_hw_revision();
  72         printf("HW Revision:\t0x%x\n", board_rev);
  73
  74         return 0;
  75 }
  76
  77 void i2c_init_board(void)
  78 {
  79         struct exynos4_gpio_part1 *gpio1 =
  80                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
  81         struct exynos4_gpio_part2 *gpio2 =
  82                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
  83
  84         /* I2C_5 -> PMIC */
  85         s5p_gpio_direction_output(&gpio1->b, 7, 1);
  86         s5p_gpio_direction_output(&gpio1->b, 6, 1);
  87         /* I2C_9 -> FG */
  88         s5p_gpio_direction_output(&gpio2->y4, 0, 1);
  89         s5p_gpio_direction_output(&gpio2->y4, 1, 1);
  90 }
  91
  92 static int pmic_init_max8997(void)
  93 {
  94         struct pmic *p = pmic_get("MAX8997_PMIC");
  95         int i = 0, ret = 0;
  96         u32 val;
  97
  98         if (pmic_probe(p))
  99                 return -1;
 100
 101         /* BUCK1 VARM: 1.2V */
 102         val = (1200000 - 650000) / 25000;
 103         ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val);
 104         val = ENBUCK | ACTIVE_DISCHARGE;                /* DVS OFF */
 105         ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val);
 106
 107         /* BUCK2 VINT: 1.1V */
 108         val = (1100000 - 650000) / 25000;
 109         ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val);
 110         val = ENBUCK | ACTIVE_DISCHARGE;                /* DVS OFF */
 111         ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val);
 112
 113
 114         /* BUCK3 G3D: 1.1V - OFF */
 115         ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val);
 116         val &= ~ENBUCK;
 117         ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val);
 118
 119         val = (1100000 - 750000) / 50000;
 120         ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val);
 121
 122         /* BUCK4 CAMISP: 1.2V - OFF */
 123         ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val);
 124         val &= ~ENBUCK;
 125         ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val);
 126
 127         val = (1200000 - 650000) / 25000;
 128         ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val);
 129
 130         /* BUCK5 VMEM: 1.2V */
 131         val = (1200000 - 650000) / 25000;
 132         for (i = 0; i < 8; i++)
 133                 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val);
 134
 135         val = ENBUCK | ACTIVE_DISCHARGE;                /* DVS OFF */
 136         ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val);
 137
 138         /* BUCK6 CAM AF: 2.8V */
 139         /* No Voltage Setting Register */
 140         /* GNSLCT 3.0X */
 141         val = GNSLCT;
 142         ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val);
 143
 144         /* BUCK7 VCC_SUB: 2.0V */
 145         val = (2000000 - 750000) / 50000;
 146         ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val);
 147
 148         /* LDO1 VADC: 3.3V */
 149         val = max8997_reg_ldo(3300000) | DIS_LDO;       /* OFF */
 150         ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val);
 151
 152         /* LDO1 Disable active discharging */
 153         ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val);
 154         val &= ~LDO_ADE;
 155         ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val);
 156
 157         /* LDO2 VALIVE: 1.1V */
 158         val = max8997_reg_ldo(1100000) | EN_LDO;
 159         ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val);
 160
 161         /* LDO3 VUSB/MIPI: 1.1V */
 162         val = max8997_reg_ldo(1100000) | DIS_LDO;       /* OFF */
 163         ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val);
 164
 165         /* LDO4 VMIPI: 1.8V */
 166         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 167         ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val);
 168
 169         /* LDO5 VHSIC: 1.2V */
 170         val = max8997_reg_ldo(1200000) | DIS_LDO;       /* OFF */
 171         ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val);
 172
 173         /* LDO6 VCC_1.8V_PDA: 1.8V */
 174         val = max8997_reg_ldo(1800000) | EN_LDO;
 175         ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val);
 176
 177         /* LDO7 CAM_ISP: 1.8V */
 178         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 179         ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val);
 180
 181         /* LDO8 VDAC/VUSB: 3.3V */
 182         val = max8997_reg_ldo(3300000) | DIS_LDO;       /* OFF */
 183         ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val);
 184
 185         /* LDO9 VCC_2.8V_PDA: 2.8V */
 186         val = max8997_reg_ldo(2800000) | EN_LDO;
 187         ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val);
 188
 189         /* LDO10 VPLL: 1.1V */
 190         val = max8997_reg_ldo(1100000) | EN_LDO;
 191         ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val);
 192
 193         /* LDO11 TOUCH: 2.8V */
 194         val = max8997_reg_ldo(2800000) | DIS_LDO;       /* OFF */
 195         ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val);
 196
 197         /* LDO12 VTCAM: 1.8V */
 198         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 199         ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val);
 200
 201         /* LDO13 VCC_3.0_LCD: 3.0V */
 202         val = max8997_reg_ldo(3000000) | DIS_LDO;       /* OFF */
 203         ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val);
 204
 205         /* LDO14 MOTOR: 3.0V */
 206         val = max8997_reg_ldo(3000000) | DIS_LDO;       /* OFF */
 207         ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val);
 208
 209         /* LDO15 LED_A: 2.8V */
 210         val = max8997_reg_ldo(2800000) | DIS_LDO;       /* OFF */
 211         ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val);
 212
 213         /* LDO16 CAM_SENSOR: 1.8V */
 214         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 215         ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val);
 216
 217         /* LDO17 VTF: 2.8V */
 218         val = max8997_reg_ldo(2800000) | DIS_LDO;       /* OFF */
 219         ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val);
 220
 221         /* LDO18 TOUCH_LED 3.3V */
 222         val = max8997_reg_ldo(3300000) | DIS_LDO;       /* OFF */
 223         ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val);
 224
 225         /* LDO21 VDDQ: 1.2V */
 226         val = max8997_reg_ldo(1200000) | EN_LDO;
 227         ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val);
 228
 229         /* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */
 230         val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) |
 231                 ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2;
 232         ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val);
 233
 234         if (ret) {
 235                 puts("MAX8997 PMIC setting error!\n");
 236                 return -1;
 237         }
 238         return 0;
 239 }
 240
 241 int power_init_board(void)
 242 {
 243         int ret;
 244
 245         ret = pmic_init(I2C_5);
 246         ret |= pmic_init_max8997();
 247         ret |= power_fg_init(I2C_9);
 248         ret |= power_muic_init(I2C_5);
 249         ret |= power_bat_init(0);
 250         if (ret)
 251                 return ret;
 252
 253         return 0;
 254 }
 255
 256 int dram_init(void)
 257 {
 258         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
 259                 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
 260
 261         return 0;
 262 }
 263
 264 void dram_init_banksize(void)
 265 {
 266         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 267         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 268         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 269         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 270 }
 271
 272 static unsigned int get_hw_revision(void)
 273 {
 274         struct exynos4_gpio_part1 *gpio =
 275                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
 276         int hwrev = 0;
 277         int i;
 278
 279         /* hw_rev[3:0] == GPE1[3:0] */
 280         for (i = 0; i < 4; i++) {
 281                 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
 282                 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
 283         }
 284
 285         udelay(1);
 286
 287         for (i = 0; i < 4; i++)
 288                 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
 289
 290         debug("hwrev 0x%x\n", hwrev);
 291
 292         return hwrev;
 293 }
 294
 295 static void check_hw_revision(void)
 296 {
 297         int hwrev;
 298
 299         hwrev = get_hw_revision();
 300
 301         board_rev |= hwrev;
 302 }
 303
 304 #ifdef CONFIG_DISPLAY_BOARDINFO
 305 int checkboard(void)
 306 {
 307         puts("Board:\tTRATS\n");
 308         return 0;
 309 }
 310 #endif
 311
 312 #ifdef CONFIG_GENERIC_MMC
 313 int board_mmc_init(bd_t *bis)
 314 {
 315         struct exynos4_gpio_part2 *gpio =
 316                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 317         int i, err;
 318
 319         /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
 320         s5p_gpio_direction_output(&gpio->k0, 2, 1);
 321         s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
 322
 323         /*
 324          * eMMC GPIO:
 325          * SDR 8-bit@48MHz at MMC0
 326          * GPK0[0]      SD_0_CLK(2)
 327          * GPK0[1]      SD_0_CMD(2)
 328          * GPK0[2]      SD_0_CDn        -> Not used
 329          * GPK0[3:6]    SD_0_DATA[0:3](2)
 330          * GPK1[3:6]    SD_0_DATA[0:3](3)
 331          *
 332          * DDR 4-bit@26MHz at MMC4
 333          * GPK0[0]      SD_4_CLK(3)
 334          * GPK0[1]      SD_4_CMD(3)
 335          * GPK0[2]      SD_4_CDn        -> Not used
 336          * GPK0[3:6]    SD_4_DATA[0:3](3)
 337          * GPK1[3:6]    SD_4_DATA[4:7](4)
 338          */
 339         for (i = 0; i < 7; i++) {
 340                 if (i == 2)
 341                         continue;
 342                 /* GPK0[0:6] special function 2 */
 343                 s5p_gpio_cfg_pin(&gpio->k0, i, 0x2);
 344                 /* GPK0[0:6] pull disable */
 345                 s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE);
 346                 /* GPK0[0:6] drv 4x */
 347                 s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X);
 348         }
 349
 350         for (i = 3; i < 7; i++) {
 351                 /* GPK1[3:6] special function 3 */
 352                 s5p_gpio_cfg_pin(&gpio->k1, i, 0x3);
 353                 /* GPK1[3:6] pull disable */
 354                 s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE);
 355                 /* GPK1[3:6] drv 4x */
 356                 s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X);
 357         }
 358
 359         /*
 360          * MMC device init
 361          * mmc0  : eMMC (8-bit buswidth)
 362          * mmc2  : SD card (4-bit buswidth)
 363          */
 364         err = s5p_mmc_init(0, 8);
 365
 366         /* T-flash detect */
 367         s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
 368         s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
 369
 370         /*
 371          * Check the T-flash  detect pin
 372          * GPX3[4] T-flash detect pin
 373          */
 374         if (!s5p_gpio_get_value(&gpio->x3, 4)) {
 375                 /*
 376                  * SD card GPIO:
 377                  * GPK2[0]      SD_2_CLK(2)
 378                  * GPK2[1]      SD_2_CMD(2)
 379                  * GPK2[2]      SD_2_CDn        -> Not used
 380                  * GPK2[3:6]    SD_2_DATA[0:3](2)
 381                  */
 382                 for (i = 0; i < 7; i++) {
 383                         if (i == 2)
 384                                 continue;
 385                         /* GPK2[0:6] special function 2 */
 386                         s5p_gpio_cfg_pin(&gpio->k2, i, 0x2);
 387                         /* GPK2[0:6] pull disable */
 388                         s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE);
 389                         /* GPK2[0:6] drv 4x */
 390                         s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X);
 391                 }
 392                 err = s5p_mmc_init(2, 4);
 393         }
 394
 395         return err;
 396 }
 397 #endif
 398
 399 #ifdef CONFIG_USB_GADGET
 400 static int s5pc210_phy_control(int on)
 401 {
 402         int ret = 0;
 403         u32 val = 0;
 404         struct pmic *p = pmic_get("MAX8997_PMIC");
 405         if (!p)
 406                 return -ENODEV;
 407
 408         if (pmic_probe(p))
 409                 return -1;
 410
 411         if (on) {
 412                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
 413                                       ENSAFEOUT1, LDO_ON);
 414                 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
 415                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
 416
 417                 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
 418                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
 419         } else {
 420                 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
 421                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
 422
 423                 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
 424                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
 425                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
 426                                       ENSAFEOUT1, LDO_OFF);
 427         }
 428
 429         if (ret) {
 430                 puts("MAX8997 LDO setting error!\n");
 431                 return -1;
 432         }
 433
 434         return 0;
 435 }
 436
 437 struct s3c_plat_otg_data s5pc210_otg_data = {
 438         .phy_control    = s5pc210_phy_control,
 439         .regs_phy       = EXYNOS4_USBPHY_BASE,
 440         .regs_otg       = EXYNOS4_USBOTG_BASE,
 441         .usb_phy_ctrl   = EXYNOS4_USBPHY_CONTROL,
 442         .usb_flags      = PHY0_SLEEP,
 443 };
 444
 445 void board_usb_init(void)
 446 {
 447         debug("USB_udc_probe\n");
 448         s3c_udc_probe(&s5pc210_otg_data);
 449 }
 450 #endif
 451
 452 static void pmic_reset(void)
 453 {
 454         struct exynos4_gpio_part2 *gpio =
 455                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 456
 457         s5p_gpio_direction_output(&gpio->x0, 7, 1);
 458         s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
 459 }
 460
 461 static void board_clock_init(void)
 462 {
 463         struct exynos4_clock *clk =
 464                 (struct exynos4_clock *)samsung_get_base_clock();
 465
 466         writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
 467         writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
 468         writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
 469         writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
 470
 471         writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
 472         writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
 473         writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
 474         writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
 475         writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
 476         writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
 477         writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
 478         writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
 479         writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
 480         writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
 481         writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
 482         writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
 483
 484         writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
 485         writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
 486         writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
 487         writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
 488         writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
 489         writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
 490         writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
 491         writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
 492         writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
 493         writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
 494         writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
 495         writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
 496
 497         writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
 498         writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
 499         writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
 500         writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
 501         writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
 502         writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
 503         writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
 504         writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
 505         writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
 506         writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
 507         writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
 508         writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
 509 }
 510
 511 static void board_power_init(void)
 512 {
 513         struct exynos4_power *pwr =
 514                 (struct exynos4_power *)samsung_get_base_power();
 515
 516         /* PS HOLD */
 517         writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
 518
 519         /* Set power down */
 520         writel(0, (unsigned int)&pwr->cam_configuration);
 521         writel(0, (unsigned int)&pwr->tv_configuration);
 522         writel(0, (unsigned int)&pwr->mfc_configuration);
 523         writel(0, (unsigned int)&pwr->g3d_configuration);
 524         writel(0, (unsigned int)&pwr->lcd1_configuration);
 525         writel(0, (unsigned int)&pwr->gps_configuration);
 526         writel(0, (unsigned int)&pwr->gps_alive_configuration);
 527 }
 528
 529 static void board_uart_init(void)
 530 {
 531         struct exynos4_gpio_part1 *gpio1 =
 532                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
 533         struct exynos4_gpio_part2 *gpio2 =
 534                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 535         int i;
 536
 537         /*
 538          * UART2 GPIOs
 539          * GPA1CON[0] = UART_2_RXD(2)
 540          * GPA1CON[1] = UART_2_TXD(2)
 541          * GPA1CON[2] = I2C_3_SDA (3)
 542          * GPA1CON[3] = I2C_3_SCL (3)
 543          */
 544
 545         for (i = 0; i < 4; i++) {
 546                 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
 547                 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
 548         }
 549
 550         /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
 551         s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
 552         s5p_gpio_direction_output(&gpio2->y4, 7, 1);
 553 }
 554
 555 int board_early_init_f(void)
 556 {
 557         wdt_stop();
 558         pmic_reset();
 559         board_clock_init();
 560         board_uart_init();
 561         board_power_init();
 562
 563         return 0;
 564 }
 565
 566 static void lcd_reset(void)
 567 {
 568         struct exynos4_gpio_part2 *gpio2 =
 569                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 570
 571         s5p_gpio_direction_output(&gpio2->y4, 5, 1);
 572         udelay(10000);
 573         s5p_gpio_direction_output(&gpio2->y4, 5, 0);
 574         udelay(10000);
 575         s5p_gpio_direction_output(&gpio2->y4, 5, 1);
 576 }
 577
 578 static int lcd_power(void)
 579 {
 580         int ret = 0;
 581         struct pmic *p = pmic_get("MAX8997_PMIC");
 582         if (!p)
 583                 return -ENODEV;
 584
 585         if (pmic_probe(p))
 586                 return 0;
 587
 588         /* LDO15 voltage: 2.2v */
 589         ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
 590         /* LDO13 voltage: 3.0v */
 591         ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
 592
 593         if (ret) {
 594                 puts("MAX8997 LDO setting error!\n");
 595                 return -1;
 596         }
 597
 598         return 0;
 599 }
 600
 601 static struct mipi_dsim_config dsim_config = {
 602         .e_interface            = DSIM_VIDEO,
 603         .e_virtual_ch           = DSIM_VIRTUAL_CH_0,
 604         .e_pixel_format         = DSIM_24BPP_888,
 605         .e_burst_mode           = DSIM_BURST_SYNC_EVENT,
 606         .e_no_data_lane         = DSIM_DATA_LANE_4,
 607         .e_byte_clk             = DSIM_PLL_OUT_DIV8,
 608         .hfp                    = 1,
 609
 610         .p                      = 3,
 611         .m                      = 120,
 612         .s                      = 1,
 613
 614         /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
 615         .pll_stable_time        = 500,
 616
 617         /* escape clk : 10MHz */
 618         .esc_clk                = 20 * 1000000,
 619
 620         /* stop state holding counter after bta change count 0 ~ 0xfff */
 621         .stop_holding_cnt       = 0x7ff,
 622         /* bta timeout 0 ~ 0xff */
 623         .bta_timeout            = 0xff,
 624         /* lp rx timeout 0 ~ 0xffff */
 625         .rx_timeout             = 0xffff,
 626 };
 627
 628 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = {
 629         .lcd_panel_info = NULL,
 630         .dsim_config = &dsim_config,
 631 };
 632
 633 static struct mipi_dsim_lcd_device mipi_lcd_device = {
 634         .name   = "s6e8ax0",
 635         .id     = -1,
 636         .bus_id = 0,
 637         .platform_data  = (void *)&s6e8ax0_platform_data,
 638 };
 639
 640 static int mipi_power(void)
 641 {
 642         int ret = 0;
 643         struct pmic *p = pmic_get("MAX8997_PMIC");
 644         if (!p)
 645                 return -ENODEV;
 646
 647         if (pmic_probe(p))
 648                 return 0;
 649
 650         /* LDO3 voltage: 1.1v */
 651         ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
 652         /* LDO4 voltage: 1.8v */
 653         ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
 654
 655         if (ret) {
 656                 puts("MAX8997 LDO setting error!\n");
 657                 return -1;
 658         }
 659
 660         return 0;
 661 }
 662
 663 vidinfo_t panel_info = {
 664         .vl_freq        = 60,
 665         .vl_col         = 720,
 666         .vl_row         = 1280,
 667         .vl_width       = 720,
 668         .vl_height      = 1280,
 669         .vl_clkp        = CONFIG_SYS_HIGH,
 670         .vl_hsp         = CONFIG_SYS_LOW,
 671         .vl_vsp         = CONFIG_SYS_LOW,
 672         .vl_dp          = CONFIG_SYS_LOW,
 673         .vl_bpix        = 5,    /* Bits per pixel, 2^5 = 32 */
 674
 675         /* s6e8ax0 Panel infomation */
 676         .vl_hspw        = 5,
 677         .vl_hbpd        = 10,
 678         .vl_hfpd        = 10,
 679
 680         .vl_vspw        = 2,
 681         .vl_vbpd        = 1,
 682         .vl_vfpd        = 13,
 683         .vl_cmd_allow_len = 0xf,
 684
 685         .win_id         = 3,
 686         .cfg_gpio       = NULL,
 687         .backlight_on   = NULL,
 688         .lcd_power_on   = NULL, /* lcd_power_on in mipi dsi driver */
 689         .reset_lcd      = lcd_reset,
 690         .dual_lcd_enabled = 0,
 691
 692         .init_delay     = 0,
 693         .power_on_delay = 0,
 694         .reset_delay    = 0,
 695         .interface_mode = FIMD_RGB_INTERFACE,
 696         .mipi_enabled   = 1,
 697 };
 698
 699 void init_panel_info(vidinfo_t *vid)
 700 {
 701         vid->logo_on    = 1,
 702         vid->resolution = HD_RESOLUTION,
 703         vid->rgb_mode   = MODE_RGB_P,
 704
 705 #ifdef CONFIG_TIZEN
 706         get_tizen_logo_info(vid);
 707 #endif
 708
 709         if (hwrevision(2))
 710                 mipi_lcd_device.reverse_panel = 1;
 711
 712         strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
 713         s6e8ax0_platform_data.lcd_power = lcd_power;
 714         s6e8ax0_platform_data.mipi_power = mipi_power;
 715         s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl;
 716         s6e8ax0_platform_data.lcd_panel_info = (void *)vid;
 717         exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
 718         s6e8ax0_init();
 719         exynos_set_dsim_platform_data(&s6e8ax0_platform_data);
 720
 721         setenv("lcdinfo", "lcd=s6e8ax0");
 722 }