board/samsung/trats/trats.c

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics
   3  * Heungjun Kim <riverful.kim@samsung.com>
   4  * Kyungmin Park <kyungmin.park@samsung.com>
   5  * Donghwa Lee <dh09.lee@samsung.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <lcd.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/cpu.h>
  30 #include <asm/arch/gpio.h>
  31 #include <asm/arch/mmc.h>
  32 #include <asm/arch/clock.h>
  33 #include <asm/arch/clk.h>
  34 #include <asm/arch/mipi_dsim.h>
  35 #include <asm/arch/watchdog.h>
  36 #include <asm/arch/power.h>
  37 #include <power/pmic.h>
  38 #include <usb/s3c_udc.h>
  39 #include <power/max8997_pmic.h>
  40 #include <libtizen.h>
  41
  42 #include "setup.h"
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 unsigned int board_rev;
  47
  48 #ifdef CONFIG_REVISION_TAG
  49 u32 get_board_rev(void)
  50 {
  51         return board_rev;
  52 }
  53 #endif
  54
  55 static void check_hw_revision(void);
  56
  57 static int hwrevision(int rev)
  58 {
  59         return (board_rev & 0xf) == rev;
  60 }
  61
  62 struct s3c_plat_otg_data s5pc210_otg_data;
  63
  64 int board_init(void)
  65 {
  66         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  67
  68         check_hw_revision();
  69         printf("HW Revision:\t0x%x\n", board_rev);
  70
  71         return 0;
  72 }
  73
  74 void i2c_init_board(void)
  75 {
  76         struct exynos4_gpio_part1 *gpio1 =
  77                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
  78         struct exynos4_gpio_part2 *gpio2 =
  79                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
  80
  81         /* I2C_5 -> PMIC */
  82         s5p_gpio_direction_output(&gpio1->b, 7, 1);
  83         s5p_gpio_direction_output(&gpio1->b, 6, 1);
  84         /* I2C_9 -> FG */
  85         s5p_gpio_direction_output(&gpio2->y4, 0, 1);
  86         s5p_gpio_direction_output(&gpio2->y4, 1, 1);
  87 }
  88
  89 int power_init_board(void)
  90 {
  91         int ret;
  92
  93         ret = pmic_init(I2C_5);
  94         if (ret)
  95                 return ret;
  96
  97         return 0;
  98 }
  99
 100 int dram_init(void)
 101 {
 102         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
 103                 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
 104
 105         return 0;
 106 }
 107
 108 void dram_init_banksize(void)
 109 {
 110         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 111         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 112         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 113         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 114 }
 115
 116 static unsigned int get_hw_revision(void)
 117 {
 118         struct exynos4_gpio_part1 *gpio =
 119                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
 120         int hwrev = 0;
 121         int i;
 122
 123         /* hw_rev[3:0] == GPE1[3:0] */
 124         for (i = 0; i < 4; i++) {
 125                 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
 126                 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
 127         }
 128
 129         udelay(1);
 130
 131         for (i = 0; i < 4; i++)
 132                 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
 133
 134         debug("hwrev 0x%x\n", hwrev);
 135
 136         return hwrev;
 137 }
 138
 139 static void check_hw_revision(void)
 140 {
 141         int hwrev;
 142
 143         hwrev = get_hw_revision();
 144
 145         board_rev |= hwrev;
 146 }
 147
 148 #ifdef CONFIG_DISPLAY_BOARDINFO
 149 int checkboard(void)
 150 {
 151         puts("Board:\tTRATS\n");
 152         return 0;
 153 }
 154 #endif
 155
 156 #ifdef CONFIG_GENERIC_MMC
 157 int board_mmc_init(bd_t *bis)
 158 {
 159         struct exynos4_gpio_part2 *gpio =
 160                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 161         int i, err;
 162
 163         /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
 164         s5p_gpio_direction_output(&gpio->k0, 2, 1);
 165         s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
 166
 167         /*
 168          * eMMC GPIO:
 169          * SDR 8-bit@48MHz at MMC0
 170          * GPK0[0]      SD_0_CLK(2)
 171          * GPK0[1]      SD_0_CMD(2)
 172          * GPK0[2]      SD_0_CDn        -> Not used
 173          * GPK0[3:6]    SD_0_DATA[0:3](2)
 174          * GPK1[3:6]    SD_0_DATA[0:3](3)
 175          *
 176          * DDR 4-bit@26MHz at MMC4
 177          * GPK0[0]      SD_4_CLK(3)
 178          * GPK0[1]      SD_4_CMD(3)
 179          * GPK0[2]      SD_4_CDn        -> Not used
 180          * GPK0[3:6]    SD_4_DATA[0:3](3)
 181          * GPK1[3:6]    SD_4_DATA[4:7](4)
 182          */
 183         for (i = 0; i < 7; i++) {
 184                 if (i == 2)
 185                         continue;
 186                 /* GPK0[0:6] special function 2 */
 187                 s5p_gpio_cfg_pin(&gpio->k0, i, 0x2);
 188                 /* GPK0[0:6] pull disable */
 189                 s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE);
 190                 /* GPK0[0:6] drv 4x */
 191                 s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X);
 192         }
 193
 194         for (i = 3; i < 7; i++) {
 195                 /* GPK1[3:6] special function 3 */
 196                 s5p_gpio_cfg_pin(&gpio->k1, i, 0x3);
 197                 /* GPK1[3:6] pull disable */
 198                 s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE);
 199                 /* GPK1[3:6] drv 4x */
 200                 s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X);
 201         }
 202
 203         /*
 204          * MMC device init
 205          * mmc0  : eMMC (8-bit buswidth)
 206          * mmc2  : SD card (4-bit buswidth)
 207          */
 208         err = s5p_mmc_init(0, 8);
 209
 210         /* T-flash detect */
 211         s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
 212         s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
 213
 214         /*
 215          * Check the T-flash  detect pin
 216          * GPX3[4] T-flash detect pin
 217          */
 218         if (!s5p_gpio_get_value(&gpio->x3, 4)) {
 219                 /*
 220                  * SD card GPIO:
 221                  * GPK2[0]      SD_2_CLK(2)
 222                  * GPK2[1]      SD_2_CMD(2)
 223                  * GPK2[2]      SD_2_CDn        -> Not used
 224                  * GPK2[3:6]    SD_2_DATA[0:3](2)
 225                  */
 226                 for (i = 0; i < 7; i++) {
 227                         if (i == 2)
 228                                 continue;
 229                         /* GPK2[0:6] special function 2 */
 230                         s5p_gpio_cfg_pin(&gpio->k2, i, 0x2);
 231                         /* GPK2[0:6] pull disable */
 232                         s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE);
 233                         /* GPK2[0:6] drv 4x */
 234                         s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X);
 235                 }
 236                 err = s5p_mmc_init(2, 4);
 237         }
 238
 239         return err;
 240 }
 241 #endif
 242
 243 #ifdef CONFIG_USB_GADGET
 244 static int s5pc210_phy_control(int on)
 245 {
 246         int ret = 0;
 247         u32 val = 0;
 248         struct pmic *p = pmic_get("MAX8997_PMIC");
 249         if (!p)
 250                 return -ENODEV;
 251
 252         if (pmic_probe(p))
 253                 return -1;
 254
 255         if (on) {
 256                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
 257                                       ENSAFEOUT1, LDO_ON);
 258                 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
 259                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
 260
 261                 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
 262                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
 263         } else {
 264                 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
 265                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
 266
 267                 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
 268                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
 269                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
 270                                       ENSAFEOUT1, LDO_OFF);
 271         }
 272
 273         if (ret) {
 274                 puts("MAX8997 LDO setting error!\n");
 275                 return -1;
 276         }
 277
 278         return 0;
 279 }
 280
 281 struct s3c_plat_otg_data s5pc210_otg_data = {
 282         .phy_control    = s5pc210_phy_control,
 283         .regs_phy       = EXYNOS4_USBPHY_BASE,
 284         .regs_otg       = EXYNOS4_USBOTG_BASE,
 285         .usb_phy_ctrl   = EXYNOS4_USBPHY_CONTROL,
 286         .usb_flags      = PHY0_SLEEP,
 287 };
 288
 289 void board_usb_init(void)
 290 {
 291         debug("USB_udc_probe\n");
 292         s3c_udc_probe(&s5pc210_otg_data);
 293 }
 294 #endif
 295
 296 static void pmic_reset(void)
 297 {
 298         struct exynos4_gpio_part2 *gpio =
 299                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 300
 301         s5p_gpio_direction_output(&gpio->x0, 7, 1);
 302         s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
 303 }
 304
 305 static void board_clock_init(void)
 306 {
 307         struct exynos4_clock *clk =
 308                 (struct exynos4_clock *)samsung_get_base_clock();
 309
 310         writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
 311         writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
 312         writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
 313         writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
 314
 315         writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
 316         writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
 317         writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
 318         writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
 319         writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
 320         writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
 321         writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
 322         writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
 323         writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
 324         writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
 325         writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
 326         writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
 327
 328         writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
 329         writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
 330         writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
 331         writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
 332         writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
 333         writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
 334         writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
 335         writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
 336         writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
 337         writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
 338         writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
 339         writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
 340
 341         writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
 342         writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
 343         writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
 344         writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
 345         writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
 346         writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
 347         writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
 348         writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
 349         writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
 350         writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
 351         writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
 352         writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
 353 }
 354
 355 static void board_power_init(void)
 356 {
 357         struct exynos4_power *pwr =
 358                 (struct exynos4_power *)samsung_get_base_power();
 359
 360         /* PS HOLD */
 361         writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
 362
 363         /* Set power down */
 364         writel(0, (unsigned int)&pwr->cam_configuration);
 365         writel(0, (unsigned int)&pwr->tv_configuration);
 366         writel(0, (unsigned int)&pwr->mfc_configuration);
 367         writel(0, (unsigned int)&pwr->g3d_configuration);
 368         writel(0, (unsigned int)&pwr->lcd1_configuration);
 369         writel(0, (unsigned int)&pwr->gps_configuration);
 370         writel(0, (unsigned int)&pwr->gps_alive_configuration);
 371 }
 372
 373 static void board_uart_init(void)
 374 {
 375         struct exynos4_gpio_part1 *gpio1 =
 376                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
 377         struct exynos4_gpio_part2 *gpio2 =
 378                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 379         int i;
 380
 381         /*
 382          * UART2 GPIOs
 383          * GPA1CON[0] = UART_2_RXD(2)
 384          * GPA1CON[1] = UART_2_TXD(2)
 385          * GPA1CON[2] = I2C_3_SDA (3)
 386          * GPA1CON[3] = I2C_3_SCL (3)
 387          */
 388
 389         for (i = 0; i < 4; i++) {
 390                 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
 391                 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
 392         }
 393
 394         /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
 395         s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
 396         s5p_gpio_direction_output(&gpio2->y4, 7, 1);
 397 }
 398
 399 int board_early_init_f(void)
 400 {
 401         wdt_stop();
 402         pmic_reset();
 403         board_clock_init();
 404         board_uart_init();
 405         board_power_init();
 406
 407         return 0;
 408 }
 409
 410 static void lcd_reset(void)
 411 {
 412         struct exynos4_gpio_part2 *gpio2 =
 413                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 414
 415         s5p_gpio_direction_output(&gpio2->y4, 5, 1);
 416         udelay(10000);
 417         s5p_gpio_direction_output(&gpio2->y4, 5, 0);
 418         udelay(10000);
 419         s5p_gpio_direction_output(&gpio2->y4, 5, 1);
 420 }
 421
 422 static int lcd_power(void)
 423 {
 424         int ret = 0;
 425         struct pmic *p = pmic_get("MAX8997_PMIC");
 426         if (!p)
 427                 return -ENODEV;
 428
 429         if (pmic_probe(p))
 430                 return 0;
 431
 432         /* LDO15 voltage: 2.2v */
 433         ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
 434         /* LDO13 voltage: 3.0v */
 435         ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
 436
 437         if (ret) {
 438                 puts("MAX8997 LDO setting error!\n");
 439                 return -1;
 440         }
 441
 442         return 0;
 443 }
 444
 445 static struct mipi_dsim_config dsim_config = {
 446         .e_interface            = DSIM_VIDEO,
 447         .e_virtual_ch           = DSIM_VIRTUAL_CH_0,
 448         .e_pixel_format         = DSIM_24BPP_888,
 449         .e_burst_mode           = DSIM_BURST_SYNC_EVENT,
 450         .e_no_data_lane         = DSIM_DATA_LANE_4,
 451         .e_byte_clk             = DSIM_PLL_OUT_DIV8,
 452         .hfp                    = 1,
 453
 454         .p                      = 3,
 455         .m                      = 120,
 456         .s                      = 1,
 457
 458         /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
 459         .pll_stable_time        = 500,
 460
 461         /* escape clk : 10MHz */
 462         .esc_clk                = 20 * 1000000,
 463
 464         /* stop state holding counter after bta change count 0 ~ 0xfff */
 465         .stop_holding_cnt       = 0x7ff,
 466         /* bta timeout 0 ~ 0xff */
 467         .bta_timeout            = 0xff,
 468         /* lp rx timeout 0 ~ 0xffff */
 469         .rx_timeout             = 0xffff,
 470 };
 471
 472 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = {
 473         .lcd_panel_info = NULL,
 474         .dsim_config = &dsim_config,
 475 };
 476
 477 static struct mipi_dsim_lcd_device mipi_lcd_device = {
 478         .name   = "s6e8ax0",
 479         .id     = -1,
 480         .bus_id = 0,
 481         .platform_data  = (void *)&s6e8ax0_platform_data,
 482 };
 483
 484 static int mipi_power(void)
 485 {
 486         int ret = 0;
 487         struct pmic *p = pmic_get("MAX8997_PMIC");
 488         if (!p)
 489                 return -ENODEV;
 490
 491         if (pmic_probe(p))
 492                 return 0;
 493
 494         /* LDO3 voltage: 1.1v */
 495         ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
 496         /* LDO4 voltage: 1.8v */
 497         ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
 498
 499         if (ret) {
 500                 puts("MAX8997 LDO setting error!\n");
 501                 return -1;
 502         }
 503
 504         return 0;
 505 }
 506
 507 vidinfo_t panel_info = {
 508         .vl_freq        = 60,
 509         .vl_col         = 720,
 510         .vl_row         = 1280,
 511         .vl_width       = 720,
 512         .vl_height      = 1280,
 513         .vl_clkp        = CONFIG_SYS_HIGH,
 514         .vl_hsp         = CONFIG_SYS_LOW,
 515         .vl_vsp         = CONFIG_SYS_LOW,
 516         .vl_dp          = CONFIG_SYS_LOW,
 517         .vl_bpix        = 5,    /* Bits per pixel, 2^5 = 32 */
 518
 519         /* s6e8ax0 Panel infomation */
 520         .vl_hspw        = 5,
 521         .vl_hbpd        = 10,
 522         .vl_hfpd        = 10,
 523
 524         .vl_vspw        = 2,
 525         .vl_vbpd        = 1,
 526         .vl_vfpd        = 13,
 527         .vl_cmd_allow_len = 0xf,
 528
 529         .win_id         = 3,
 530         .cfg_gpio       = NULL,
 531         .backlight_on   = NULL,
 532         .lcd_power_on   = NULL, /* lcd_power_on in mipi dsi driver */
 533         .reset_lcd      = lcd_reset,
 534         .dual_lcd_enabled = 0,
 535
 536         .init_delay     = 0,
 537         .power_on_delay = 0,
 538         .reset_delay    = 0,
 539         .interface_mode = FIMD_RGB_INTERFACE,
 540         .mipi_enabled   = 1,
 541 };
 542
 543 void init_panel_info(vidinfo_t *vid)
 544 {
 545         vid->logo_on    = 1,
 546         vid->resolution = HD_RESOLUTION,
 547         vid->rgb_mode   = MODE_RGB_P,
 548
 549 #ifdef CONFIG_TIZEN
 550         get_tizen_logo_info(vid);
 551 #endif
 552
 553         if (hwrevision(2))
 554                 mipi_lcd_device.reverse_panel = 1;
 555
 556         strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
 557         s6e8ax0_platform_data.lcd_power = lcd_power;
 558         s6e8ax0_platform_data.mipi_power = mipi_power;
 559         s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl;
 560         s6e8ax0_platform_data.lcd_panel_info = (void *)vid;
 561         exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
 562         s6e8ax0_init();
 563         exynos_set_dsim_platform_data(&s6e8ax0_platform_data);
 564
 565         setenv("lcdinfo", "lcd=s6e8ax0");
 566 }