board/sbc8548/tlb.c

   1 /*
   2  * Copyright 2008 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2000
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <asm/mmu.h>
  28
  29 struct fsl_e_tlb_entry tlb_table[] = {
  30         /* TLB 0 - for temp stack in cache */
  31         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  32                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  33                       0, 0, BOOKE_PAGESZ_4K, 0),
  34         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  35                       CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  36                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  37                       0, 0, BOOKE_PAGESZ_4K, 0),
  38         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  39                       CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  40                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  41                       0, 0, BOOKE_PAGESZ_4K, 0),
  42         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  43                       CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  44                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  45                       0, 0, BOOKE_PAGESZ_4K, 0),
  46
  47         /*
  48          * TLB 0:       64M     Non-cacheable, guarded
  49          * 0xfc000000   56M     unused
  50          * 0xff800000   8M      boot FLASH
  51          *      .... or ....
  52          * 0xfc000000   64M     user flash
  53          *
  54          * Out of reset this entry is only 4K.
  55          */
  56         SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000,
  57                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  58                       0, 0, BOOKE_PAGESZ_64M, 1),
  59
  60         /*
  61          * TLB 1:       1G      Non-cacheable, guarded
  62          * 0x80000000   512M    PCI1 MEM
  63          * 0xa0000000   512M    PCIe MEM
  64          */
  65         SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
  66                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  67                       0, 1, BOOKE_PAGESZ_1G, 1),
  68
  69         /*
  70          * TLB 2:       64M     Non-cacheable, guarded
  71          * 0xe0000000   1M      CCSRBAR
  72          * 0xe2000000   8M      PCI1 IO
  73          * 0xe2800000   8M      PCIe IO
  74          */
  75         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  76                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  77                       0, 2, BOOKE_PAGESZ_64M, 1),
  78
  79 #ifdef CONFIG_SYS_LBC_SDRAM_BASE
  80         /*
  81          * TLB 3:       64M     Cacheable, non-guarded
  82          * 0xf0000000   64M     LBC SDRAM First half
  83          */
  84         SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
  85                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  86                       0, 3, BOOKE_PAGESZ_64M, 1),
  87
  88         /*
  89          * TLB 4:       64M     Cacheable, non-guarded
  90          * 0xf4000000   64M     LBC SDRAM Second half
  91          */
  92         SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
  93                       CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
  94                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  95                       0, 4, BOOKE_PAGESZ_64M, 1),
  96 #endif
  97
  98         /*
  99          * TLB 5:       16M     Cacheable, non-guarded
 100          * 0xf8000000   1M      7-segment LED display
 101          * 0xf8100000   1M      User switches
 102          * 0xf8300000   1M      Board revision
 103          * 0xf8b00000   1M      EEPROM
 104          */
 105         SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
 106                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 107                       0, 5, BOOKE_PAGESZ_16M, 1),
 108
 109 #ifndef CONFIG_SYS_ALT_BOOT
 110         /*
 111          * TLB 6:       64M     Non-cacheable, guarded
 112          * 0xec000000   64M     64MB user FLASH
 113          */
 114         SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
 115                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 116                       0, 6, BOOKE_PAGESZ_64M, 1),
 117 #else
 118         /*
 119          * TLB 6:       4M      Non-cacheable, guarded
 120          * 0xef800000   4M      1st 1/2 8MB soldered FLASH
 121          */
 122         SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
 123                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 124                       0, 6, BOOKE_PAGESZ_4M, 1),
 125
 126         /*
 127          * TLB 7:       4M      Non-cacheable, guarded
 128          * 0xefc00000   4M      2nd half 8MB soldered FLASH
 129          */
 130         SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
 131                       CONFIG_SYS_ALT_FLASH + 0x400000,
 132                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 133                       0, 7, BOOKE_PAGESZ_4M, 1),
 134 #endif
 135
 136 };
 137
 138 int num_tlb_entries = ARRAY_SIZE(tlb_table);