board/sbc8548/tlb.c

   1 /*
   2  * Copyright 2008 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2000
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <asm/mmu.h>
  28
  29 struct fsl_e_tlb_entry tlb_table[] = {
  30         /* TLB 0 - for temp stack in cache */
  31         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  32                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  33                       0, 0, BOOKE_PAGESZ_4K, 0),
  34         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  35                       CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  36                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  37                       0, 0, BOOKE_PAGESZ_4K, 0),
  38         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  39                       CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  40                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  41                       0, 0, BOOKE_PAGESZ_4K, 0),
  42         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  43                       CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  44                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  45                       0, 0, BOOKE_PAGESZ_4K, 0),
  46
  47         /*
  48          * TLB 0:       64M     Non-cacheable, guarded
  49          * 0xfc000000   56M     8MB -> 64MB of user flash
  50          * 0xff800000   8M      boot FLASH
  51          * Out of reset this entry is only 4K.
  52          */
  53         SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x800000,
  54                       CONFIG_SYS_ALT_FLASH + 0x800000,
  55                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  56                       0, 0, BOOKE_PAGESZ_64M, 1),
  57
  58         /*
  59          * TLB 1:       256M    Non-cacheable, guarded
  60          * 0x80000000   256M    PCI1 MEM First half
  61          */
  62         SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
  63                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  64                       0, 1, BOOKE_PAGESZ_256M, 1),
  65
  66         /*
  67          * TLB 2:       256M    Non-cacheable, guarded
  68          * 0x90000000   256M    PCI1 MEM Second half
  69          */
  70         SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
  71                       CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
  72                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  73                       0, 2, BOOKE_PAGESZ_256M, 1),
  74
  75         /*
  76          * TLB 3:       256M Cacheable, non-guarded
  77          * 0x0          256M DDR SDRAM
  78          */
  79         #if !defined(CONFIG_SPD_EEPROM)
  80         SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
  81                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  82                       0, 3, BOOKE_PAGESZ_256M, 1),
  83         #endif
  84
  85         /*
  86          * TLB 4:       64M     Non-cacheable, guarded
  87          * 0xe0000000   1M      CCSRBAR
  88          * 0xe2000000   16M     PCI1 IO
  89          */
  90         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  91                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  92                       0, 4, BOOKE_PAGESZ_64M, 1),
  93
  94         /*
  95          * TLB 5:       64M     Cacheable, non-guarded
  96          * 0xf0000000   64M     LBC SDRAM
  97          */
  98         SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
  99                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
 100                       0, 5, BOOKE_PAGESZ_64M, 1),
 101
 102         /*
 103          * TLB 6:       16M     Cacheable, non-guarded
 104          * 0xf8000000   1M      7-segment LED display
 105          * 0xf8100000   1M      User switches
 106          * 0xf8300000   1M      Board revision
 107          * 0xf8b00000   1M      EEPROM
 108          */
 109         SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
 110                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 111                       0, 6, BOOKE_PAGESZ_16M, 1),
 112
 113         /*
 114          * TLB 7:       4M      Non-cacheable, guarded
 115          * 0xfb800000   4M      1st 4MB block of 64MB user FLASH
 116          */
 117         SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
 118                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 119                       0, 7, BOOKE_PAGESZ_4M, 1),
 120
 121         /*
 122          * TLB 8:       4M      Non-cacheable, guarded
 123          * 0xfbc00000   4M      2nd 4MB block of 64MB user FLASH
 124          */
 125         SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
 126                       CONFIG_SYS_ALT_FLASH + 0x400000,
 127                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 128                       0, 8, BOOKE_PAGESZ_4M, 1),
 129
 130 };
 131
 132 int num_tlb_entries = ARRAY_SIZE(tlb_table);