2 * Board functions for Siemens CORVUS (AT91SAM9G45) based board
3 * (C) Copyright 2013 Siemens AG
6 * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
7 * (C) Copyright 2007-2008
8 * Stelian Pop <stelian@popies.net>
9 * Lead Tech Design <www.leadtechdesign.com>
11 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/at91sam9g45_matrix.h>
18 #include <asm/arch/at91sam9_smc.h>
19 #include <asm/arch/at91_common.h>
20 #include <asm/arch/at91_pmc.h>
21 #include <asm/arch/at91_rstc.h>
22 #include <asm/arch/gpio.h>
23 #include <asm/arch/clk.h>
25 #include <atmel_lcdc.h>
26 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
32 DECLARE_GLOBAL_DATA_PTR;
34 static void corvus_nand_hw_init(void)
36 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
37 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
41 csa = readl(&matrix->ebicsa);
42 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
43 writel(csa, &matrix->ebicsa);
45 /* Configure SMC CS3 for NAND/SmartMedia */
46 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
47 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
49 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
50 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
52 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
54 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
55 AT91_SMC_MODE_EXNW_DISABLE |
56 #ifdef CONFIG_SYS_NAND_DBW_16
57 AT91_SMC_MODE_DBW_16 |
58 #else /* CONFIG_SYS_NAND_DBW_8 */
61 AT91_SMC_MODE_TDF_CYCLE(3),
64 at91_periph_clk_enable(ATMEL_ID_PIOC);
66 /* Enable NandFlash */
67 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
70 #if defined(CONFIG_SPL_BUILD)
74 void at91_spl_board_init(void)
77 * For on the sam9m10g45ek board, the chip wm9711 stay in the test
78 * mode, so it need do some action to exit mode.
80 at91_set_gpio_output(AT91_PIN_PD7, 0);
81 at91_set_gpio_output(AT91_PIN_PD8, 0);
82 at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
83 at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
84 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
85 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
86 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
88 corvus_nand_hw_init();
90 /* Configure recovery button PINs */
91 at91_set_gpio_input(AT91_PIN_PB7, 1);
93 /* check if button is pressed */
94 if (at91_get_gpio_value(AT91_PIN_PB7) == 0) {
97 debug("Recovery button pressed\n");
98 boot_device = spl_boot_device();
99 switch (boot_device) {
100 #ifdef CONFIG_SPL_NAND_SUPPORT
101 case BOOT_DEVICE_NAND:
103 spl_nand_erase_one(0, 0);
110 #include <asm/arch/atmel_mpddrc.h>
111 static void ddr2_conf(struct atmel_mpddr *ddr2)
113 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
115 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
116 ATMEL_MPDDRC_CR_NR_ROW_14 |
117 ATMEL_MPDDRC_CR_DIC_DS |
118 ATMEL_MPDDRC_CR_DQMS_SHARED |
119 ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
122 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
123 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
124 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
125 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 75 ns */
126 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
127 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
128 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
129 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
131 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
132 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
133 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
134 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
136 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
137 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
138 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
139 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
144 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
145 struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
146 struct atmel_mpddr ddr2;
151 /* enable DDR2 clock */
152 writel(0x4, &pmc->scer);
154 /* Chip select 1 is for DDR2/SDRAM */
155 csa = readl(&mat->ebicsa);
156 csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
157 csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
158 writel(csa, &mat->ebicsa);
160 /* DDRAM2 Controller initialize */
161 ddr2_init(ATMEL_BASE_CS6, &ddr2);
165 #ifdef CONFIG_CMD_USB
166 static void taurus_usb_hw_init(void)
168 at91_periph_clk_enable(ATMEL_ID_PIODE);
170 at91_set_gpio_output(AT91_PIN_PD1, 0);
171 at91_set_gpio_output(AT91_PIN_PD3, 0);
176 static void corvus_macb_hw_init(void)
179 at91_periph_clk_enable(ATMEL_ID_EMAC);
182 * Disable pull-up on:
183 * RXDV (PA15) => PHY normal mode (not Test mode)
184 * ERX0 (PA12) => PHY ADDR0
185 * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
187 * PHY has internal pull-down
189 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
190 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0);
191 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0);
195 /* Re-enable pull-up */
196 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
197 at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
198 at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
205 int board_early_init_f(void)
207 at91_seriald_hw_init();
213 /* address of boot parameters */
214 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
216 #ifdef CONFIG_CMD_NAND
217 corvus_nand_hw_init();
219 #ifdef CONFIG_ATMEL_SPI
220 at91_spi0_hw_init(1 << 4);
222 #ifdef CONFIG_HAS_DATAFLASH
223 at91_spi0_hw_init(1 << 0);
226 corvus_macb_hw_init();
228 #ifdef CONFIG_CMD_USB
229 taurus_usb_hw_init();
236 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
237 CONFIG_SYS_SDRAM_SIZE);
241 int board_eth_init(bd_t *bis)
245 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
250 /* SPI chip select control */
251 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
253 return bus == 0 && cs < 2;
256 void spi_cs_activate(struct spi_slave *slave)
260 at91_set_gpio_output(AT91_PIN_PB18, 0);
264 at91_set_gpio_output(AT91_PIN_PB3, 0);
269 void spi_cs_deactivate(struct spi_slave *slave)
273 at91_set_gpio_output(AT91_PIN_PB18, 1);
277 at91_set_gpio_output(AT91_PIN_PB3, 1);