2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * Achim Ehrlich <aehrlich@taskit.de>
7 * taskit GmbH <www.taskit.de>
10 * Markus Hubig <mhubig@imko.de>
11 * IMKO GmbH <www.imko.de>
13 * Heiko Schocher <hs@denx.de>
14 * DENX Software Engineering GmbH
16 * SPDX-License-Identifier: GPL-2.0+
21 #include <asm/arch/at91sam9_sdramc.h>
22 #include <asm/arch/at91sam9260_matrix.h>
23 #include <asm/arch/at91sam9_smc.h>
24 #include <asm/arch/at91_common.h>
25 #include <asm/arch/at91_pmc.h>
26 #include <asm/arch/at91_spi.h>
28 #include <asm/arch/gpio.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 static void smartweb_nand_hw_init(void)
39 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
40 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
43 /* Assign CS3 to NAND/SmartMedia Interface */
44 csa = readl(&matrix->ebicsa);
45 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
46 writel(csa, &matrix->ebicsa);
48 /* Configure SMC CS3 for NAND/SmartMedia */
49 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
50 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
52 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
53 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
55 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
57 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
58 AT91_SMC_MODE_TDF_CYCLE(2),
61 /* Configure RDY/BSY */
62 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
64 /* Enable NandFlash */
65 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
69 static void smartweb_macb_hw_init(void)
71 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
73 /* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */
74 at91_set_gpio_output(AT91_PIN_PA26, 0);
78 * RXDV (PA17) => PHY normal mode (not Test mode)
79 * ERX0 (PA14) => PHY ADDR0
80 * ERX1 (PA15) => PHY ADDR1
81 * ERX2 (PA25) => PHY ADDR2
82 * ERX3 (PA26) => PHY ADDR3
83 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
85 * PHY has internal pull-down
87 writel(pin_to_mask(AT91_PIN_PA14) |
88 pin_to_mask(AT91_PIN_PA15) |
89 pin_to_mask(AT91_PIN_PA17) |
90 pin_to_mask(AT91_PIN_PA25) |
91 pin_to_mask(AT91_PIN_PA26) |
92 pin_to_mask(AT91_PIN_PA28),
97 /* Re-enable pull-up */
98 writel(pin_to_mask(AT91_PIN_PA14) |
99 pin_to_mask(AT91_PIN_PA15) |
100 pin_to_mask(AT91_PIN_PA17) |
101 pin_to_mask(AT91_PIN_PA25) |
102 pin_to_mask(AT91_PIN_PA26) |
103 pin_to_mask(AT91_PIN_PA28),
106 /* Initialize EMAC=MACB hardware */
109 #endif /* CONFIG_MACB */
111 int board_early_init_f(void)
113 /* enable this here, as we have SPL without serial support */
114 at91_seriald_hw_init();
120 /* Adress of boot parameters */
121 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
123 smartweb_nand_hw_init();
125 smartweb_macb_hw_init();
128 at91_set_gpio_output(AT91_PIN_PC6, 0);
129 at91_set_gpio_output(AT91_PIN_PC7, 1);
131 at91_set_gpio_output(AT91_PIN_PC8, 0);
132 at91_set_gpio_output(AT91_PIN_PC9, 0);
134 at91_set_gpio_output(AT91_PIN_PC10, 0);
135 at91_set_gpio_output(AT91_PIN_PC11, 1);
142 gd->ram_size = get_ram_size(
143 (void *)CONFIG_SYS_SDRAM_BASE,
144 CONFIG_SYS_SDRAM_SIZE);
149 int board_eth_init(bd_t *bis)
151 return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
153 #endif /* CONFIG_MACB */
155 #if defined(CONFIG_SPL_BUILD)
158 #include <spi_flash.h>
160 void matrix_init(void)
162 struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
164 writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE))
165 | AT91_MATRIX_SLOT_CYCLE_(0x40),
169 void spl_board_init(void)
171 at91_set_gpio_output(AT91_PIN_PC6, 1);
172 at91_set_gpio_output(AT91_PIN_PC7, 1);
173 /* alarm LED orange */
174 at91_set_gpio_output(AT91_PIN_PC8, 1);
175 at91_set_gpio_output(AT91_PIN_PC9, 1);
177 at91_set_gpio_output(AT91_PIN_PC10, 0);
178 at91_set_gpio_output(AT91_PIN_PC11, 1);
180 smartweb_nand_hw_init();
181 at91_set_gpio_input(AT91_PIN_PA28, 1);
182 at91_set_gpio_input(AT91_PIN_PA29, 1);
184 /* check if both button are pressed */
185 if (at91_get_gpio_value(AT91_PIN_PA28) == 0 &&
186 at91_get_gpio_value(AT91_PIN_PA29) == 0) {
187 debug("Recovery button pressed\n");
189 spl_nand_erase_one(0, 0);
193 #define SDRAM_BASE_CONF (AT91_SDRAMC_NC_9 | AT91_SDRAMC_NR_13 \
194 | AT91_SDRAMC_CAS_2 \
195 | AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \
196 | AT91_SDRAMC_TWR_VAL(2) | AT91_SDRAMC_TRC_VAL(7) \
197 | AT91_SDRAMC_TRP_VAL(2) | AT91_SDRAMC_TRCD_VAL(2) \
198 | AT91_SDRAMC_TRAS_VAL(5) | AT91_SDRAMC_TXSR_VAL(8))
202 struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX;
203 struct at91_port *port = (struct at91_port *)ATMEL_BASE_PIOC;
204 struct sdramc_reg setting;
206 setting.cr = SDRAM_BASE_CONF;
207 setting.mdr = AT91_SDRAMC_MD_SDRAM;
208 setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000;
211 * I write here directly in this register, because this
212 * approach is smaller than calling at91_set_a_periph() in a
213 * for loop. This saved me 96 bytes.
215 writel(0xffff0000, &port->pdr);
217 writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC, &ma->ebicsa);
218 sdramc_initialize(ATMEL_BASE_CS1, &setting);