board/silica/pengwyn/board.c

   1 /*
   2  * board.c
   3  *
   4  * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/arch/cpu.h>
  11 #include <asm/arch/hardware.h>
  12 #include <asm/arch/ddr_defs.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <i2c.h>
  16 #include <phy.h>
  17 #include <cpsw.h>
  18 #include "board.h"
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  23
  24 #if defined(CONFIG_SPL_BUILD)
  25
  26 /* DDR3 RAM timings */
  27 static const struct ddr_data ddr3_data = {
  28         .datardsratio0 = MT41K128MJT187E_RD_DQS,
  29         .datawdsratio0 = MT41K128MJT187E_WR_DQS,
  30         .datafwsratio0 = MT41K128MJT187E_PHY_FIFO_WE,
  31         .datawrsratio0 = MT41K128MJT187E_PHY_WR_DATA,
  32 };
  33
  34 static const struct cmd_control ddr3_cmd_ctrl_data = {
  35         .cmd0csratio = MT41K128MJT187E_RATIO,
  36         .cmd0iclkout = MT41K128MJT187E_INVERT_CLKOUT,
  37         .cmd1csratio = MT41K128MJT187E_RATIO,
  38         .cmd1iclkout = MT41K128MJT187E_INVERT_CLKOUT,
  39         .cmd2csratio = MT41K128MJT187E_RATIO,
  40         .cmd2iclkout = MT41K128MJT187E_INVERT_CLKOUT,
  41 };
  42
  43 static struct emif_regs ddr3_emif_reg_data = {
  44         .sdram_config = MT41K128MJT187E_EMIF_SDCFG,
  45         .ref_ctrl = MT41K128MJT187E_EMIF_SDREF,
  46         .sdram_tim1 = MT41K128MJT187E_EMIF_TIM1,
  47         .sdram_tim2 = MT41K128MJT187E_EMIF_TIM2,
  48         .sdram_tim3 = MT41K128MJT187E_EMIF_TIM3,
  49         .zq_config = MT41K128MJT187E_ZQ_CFG,
  50         .emif_ddr_phy_ctlr_1 = MT41K128MJT187E_EMIF_READ_LATENCY |
  51                                 PHY_EN_DYN_PWRDN,
  52 };
  53
  54 const struct ctrl_ioregs ddr3_ioregs = {
  55         .cm0ioctl               = MT41K128MJT187E_IOCTRL_VALUE,
  56         .cm1ioctl               = MT41K128MJT187E_IOCTRL_VALUE,
  57         .cm2ioctl               = MT41K128MJT187E_IOCTRL_VALUE,
  58         .dt0ioctl               = MT41K128MJT187E_IOCTRL_VALUE,
  59         .dt1ioctl               = MT41K128MJT187E_IOCTRL_VALUE,
  60 };
  61
  62 #ifdef CONFIG_SPL_OS_BOOT
  63 int spl_start_uboot(void)
  64 {
  65         /* break into full u-boot on 'c' */
  66         return serial_tstc() && serial_getc() == 'c';
  67 }
  68 #endif
  69
  70 #define OSC     (V_OSCK/1000000)
  71 const struct dpll_params dpll_ddr_266 = {
  72                 266, OSC-1, 1, -1, -1, -1, -1};
  73 const struct dpll_params dpll_ddr_303 = {
  74                 303, OSC-1, 1, -1, -1, -1, -1};
  75 const struct dpll_params dpll_ddr_400 = {
  76                 400, OSC-1, 1, -1, -1, -1, -1};
  77
  78 void am33xx_spl_board_init(void)
  79 {
  80         /*
  81          * The pengwyn board uses the TPS650250 PMIC  without I2C
  82          * interface and will output the following fixed voltages:
  83          * DCDC1=3V3 (IO) DCDC2=1V5 (DDR) DCDC3=1V26 (Vmpu)
  84          * VLDO1=1V8 (IO) VLDO2=1V8(IO)
  85          * Vcore=1V1 is fixed, generated by TPS62231
  86          */
  87
  88         /* Get the frequency */
  89         dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  90
  91         /* Set CORE Frequencies to OPP100 */
  92         do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  93
  94         /* 720MHz cpu, this might change on newer board revisions */
  95         dpll_mpu_opp100.m = MPUPLL_M_720;
  96         do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
  97 }
  98
  99 const struct dpll_params *get_dpll_ddr_params(void)
 100 {
 101         /* future configs can return other clock settings */
 102         return &dpll_ddr_303;
 103 }
 104
 105 void set_uart_mux_conf(void)
 106 {
 107         enable_uart0_pin_mux();
 108 }
 109
 110 void set_mux_conf_regs(void)
 111 {
 112         enable_board_pin_mux();
 113 }
 114
 115 void sdram_init(void)
 116 {
 117         config_ddr(303, &ddr3_ioregs, &ddr3_data,
 118                    &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 119 }
 120 #endif /* if CONFIG_SPL_BUILD */
 121
 122 /*
 123  * Basic board specific setup.  Pinmux has been handled already.
 124  */
 125 int board_init(void)
 126 {
 127         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 128         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 129         gpmc_init();
 130         return 0;
 131 }
 132
 133 #ifdef CONFIG_DRIVER_TI_CPSW
 134 static void cpsw_control(int enabled)
 135 {
 136         /* VTP can be added here */
 137         return;
 138 }
 139
 140 static struct cpsw_slave_data cpsw_slaves[] = {
 141         {
 142                 .slave_reg_ofs  = 0x208,
 143                 .sliver_reg_ofs = 0xd80,
 144                 .phy_addr       = 0,
 145                 .phy_if         = PHY_INTERFACE_MODE_MII,
 146         },
 147         {
 148                 .slave_reg_ofs  = 0x308,
 149                 .sliver_reg_ofs = 0xdc0,
 150                 .phy_addr       = 1,
 151                 .phy_if         = PHY_INTERFACE_MODE_MII,
 152         },
 153 };
 154
 155 static struct cpsw_platform_data cpsw_data = {
 156         .mdio_base              = CPSW_MDIO_BASE,
 157         .cpsw_base              = CPSW_BASE,
 158         .mdio_div               = 0xff,
 159         .channels               = 8,
 160         .cpdma_reg_ofs          = 0x800,
 161         .slaves                 = 1,
 162         .slave_data             = cpsw_slaves,
 163         .ale_reg_ofs            = 0xd00,
 164         .ale_entries            = 1024,
 165         .host_port_reg_ofs      = 0x108,
 166         .hw_stats_reg_ofs       = 0x900,
 167         .bd_ram_ofs             = 0x2000,
 168         .mac_control            = (1 << 5),
 169         .control                = cpsw_control,
 170         .host_port_num          = 0,
 171         .version                = CPSW_CTRL_VERSION_2,
 172 };
 173
 174 int board_eth_init(bd_t *bis)
 175 {
 176         int rv, n = 0;
 177         uint8_t mac_addr[6];
 178         uint32_t mac_hi, mac_lo;
 179
 180         if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
 181                 printf("<ethaddr> not set. Reading from E-fuse\n");
 182                 /* try reading mac address from efuse */
 183                 mac_lo = readl(&cdev->macid0l);
 184                 mac_hi = readl(&cdev->macid0h);
 185                 mac_addr[0] = mac_hi & 0xFF;
 186                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 187                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 188                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 189                 mac_addr[4] = mac_lo & 0xFF;
 190                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 191
 192                 if (is_valid_ether_addr(mac_addr))
 193                         eth_setenv_enetaddr("ethaddr", mac_addr);
 194                 else
 195                         return n;
 196         }
 197
 198         writel(MII_MODE_ENABLE, &cdev->miisel);
 199
 200         rv = cpsw_register(&cpsw_data);
 201         if (rv < 0)
 202                 printf("Error %d registering CPSW switch\n", rv);
 203         else
 204                 n += rv;
 205         return n;
 206 }
 207 #endif /* if CONFIG_DRIVER_TI_CPSW */