board/syteco/jadecpu/lowlevel_init.S

   1 /*
   2  * Board specific setup info
   3  *
   4  * (C) Copyright 2007, mycable GmbH
   5  * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
   6  *
   7  * (C) Copyright 2003, ARM Ltd.
   8  * Philippe Robin, <philippe.robin@arm.com>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <config.h>
  30 #include <version.h>
  31 #include <asm/macro.h>
  32 #include <asm/arch/mb86r0x.h>
  33 #include <generated/asm-offsets.h>
  34
  35 /* Set up the platform, once the cpu has been initialized */
  36 .globl lowlevel_init
  37 lowlevel_init:
  38 /*
  39  * Initialize Clock Reset Generator (CRG)
  40  */
  41
  42         ldr             r0, =MB86R0x_CRG_BASE
  43
  44         /* Not change the initial value that is set by external pin.*/
  45 WAIT_PLL:
  46         ldr             r2, [r0, #CRG_CRPR]     /* Wait for PLLREADY */
  47         tst             r2, #MB86R0x_CRG_CRPR_PLLRDY
  48         beq             WAIT_PLL
  49
  50         /* Set clock gate control */
  51         ldr             r1, =CONFIG_SYS_CRG_CRHA_INIT
  52         str             r1, [r0, #CRG_CRHA]
  53         ldr             r1, =CONFIG_SYS_CRG_CRPA_INIT
  54         str             r1, [r0, #CRG_CRPA]
  55         ldr             r1, =CONFIG_SYS_CRG_CRPB_INIT
  56         str             r1, [r0, #CRG_CRPB]
  57         ldr             r1, =CONFIG_SYS_CRG_CRHB_INIT
  58         str             r1, [r0, #CRG_CRHB]
  59         ldr             r1, =CONFIG_SYS_CRG_CRAM_INIT
  60         str             r1, [r0, #CRG_CRAM]
  61
  62 /*
  63  * Initialize External Bus Interface
  64  */
  65         ldr             r0, =MB86R0x_MEMC_BASE
  66
  67         ldr             r1, =CONFIG_SYS_MEMC_MCFMODE0_INIT
  68         str             r1, [r0, #MEMC_MCFMODE0]
  69         ldr             r1, =CONFIG_SYS_MEMC_MCFMODE2_INIT
  70         str             r1, [r0, #MEMC_MCFMODE2]
  71         ldr             r1, =CONFIG_SYS_MEMC_MCFMODE4_INIT
  72         str             r1, [r0, #MEMC_MCFMODE4]
  73
  74         ldr             r1, =CONFIG_SYS_MEMC_MCFTIM0_INIT
  75         str             r1, [r0, #MEMC_MCFTIM0]
  76         ldr             r1, =CONFIG_SYS_MEMC_MCFTIM2_INIT
  77         str             r1, [r0, #MEMC_MCFTIM2]
  78         ldr             r1, =CONFIG_SYS_MEMC_MCFTIM4_INIT
  79         str             r1, [r0, #MEMC_MCFTIM4]
  80
  81         ldr             r1, =CONFIG_SYS_MEMC_MCFAREA0_INIT
  82         str             r1, [r0, #MEMC_MCFAREA0]
  83         ldr             r1, =CONFIG_SYS_MEMC_MCFAREA2_INIT
  84         str             r1, [r0, #MEMC_MCFAREA2]
  85         ldr             r1, =CONFIG_SYS_MEMC_MCFAREA4_INIT
  86         str             r1, [r0, #MEMC_MCFAREA4]
  87
  88 /*
  89  * Initialize DDR2 Controller
  90  */
  91
  92         /* Wait for PLL LOCK up time or more */
  93         wait_timer      20
  94
  95         /*
  96          * (2) Initialize DDRIF
  97          */
  98         ldr     r0, =MB86R0x_DDR2_BASE
  99         ldr     r1, =CONFIG_SYS_DDR2_DRIMS_INIT
 100         strh    r1, [r0, #DDR2_DRIMS]
 101
 102         /*
 103          * (3) Wait for 20MCKPs(120nsec) or more
 104          */
 105         wait_timer      20
 106
 107         /*
 108          * (4) IRESET/IUSRRST release
 109          */
 110         ldr     r0, =MB86R0x_CCNT_BASE
 111         ldr     r1, =CONFIG_SYS_CCNT_CDCRC_INIT_1
 112         str     r1, [r0, #CCNT_CDCRC]
 113
 114         /*
 115          * (5) Wait for 20MCKPs(120nsec) or more
 116          */
 117         wait_timer      20
 118
 119         /*
 120          * (6) IDLLRST release
 121          */
 122         ldr     r0, =MB86R0x_CCNT_BASE
 123         ldr     r1, =CONFIG_SYS_CCNT_CDCRC_INIT_2
 124         str     r1, [r0, #CCNT_CDCRC]
 125
 126         /*
 127          * (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec)
 128          */
 129         wait_timer      33536
 130
 131         /*
 132          * (9) MCKE ON
 133          */
 134         ldr     r0, =MB86R0x_DDR2_BASE
 135         ldr     r1, =CONFIG_SYS_DDR2_DRIC1_INIT
 136         strh    r1, [r0, #DDR2_DRIC1]
 137         ldr     r1, =CONFIG_SYS_DDR2_DRIC2_INIT
 138         strh    r1, [r0, #DDR2_DRIC2]
 139         ldr     r1, =CONFIG_SYS_DDR2_DRCA_INIT
 140         strh    r1, [r0, #DDR2_DRCA]
 141         ldr     r1, =MB86R0x_DDR2_DRCI_INIT
 142         strh    r1, [r0, #DDR2_DRIC]
 143
 144         /*
 145          * (10) Initialize SDRAM
 146          */
 147
 148         ldr     r1, =MB86R0x_DDR2_DRCI_CMD
 149         strh    r1, [r0, #DDR2_DRIC]
 150
 151         wait_timer      67                      /* 400ns wait */
 152
 153         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_1
 154         strh    r1, [r0, #DDR2_DRIC1]
 155         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_1
 156         strh    r1, [r0, #DDR2_DRIC2]
 157         ldr     r1, =MB86R0x_DDR2_DRCI_CMD
 158         strh    r1, [r0, #DDR2_DRIC]
 159
 160         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_2
 161         strh    r1, [r0, #DDR2_DRIC1]
 162         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_2
 163         strh    r1, [r0, #DDR2_DRIC2]
 164         ldr     r1, =MB86R0x_DDR2_DRCI_CMD
 165         strh    r1, [r0, #DDR2_DRIC]
 166
 167         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_3
 168         strh    r1, [r0, #DDR2_DRIC1]
 169         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_3
 170         strh    r1, [r0, #DDR2_DRIC2]
 171         ldr     r1, =MB86R0x_DDR2_DRCI_CMD
 172         strh    r1, [r0, #DDR2_DRIC]
 173
 174         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_4
 175         strh    r1, [r0, #DDR2_DRIC1]
 176         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_4
 177         strh    r1, [r0, #DDR2_DRIC2]
 178         ldr     r1, =MB86R0x_DDR2_DRCI_CMD
 179         strh    r1, [r0, #DDR2_DRIC]
 180
 181         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_5
 182         strh    r1, [r0, #DDR2_DRIC1]
 183         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_5
 184         strh    r1, [r0, #DDR2_DRIC2]
 185         ldr     r1, =MB86R0x_DDR2_DRCI_CMD
 186         strh    r1, [r0, #DDR2_DRIC]
 187
 188         wait_timer 200
 189
 190         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_6
 191         strh    r1, [r0, #DDR2_DRIC1]
 192         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_6
 193         strh    r1, [r0, #DDR2_DRIC2]
 194         ldr     r1, =MB86R0x_DDR2_DRCI_CMD
 195         strh    r1, [r0, #DDR2_DRIC]
 196
 197         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_7
 198         strh    r1, [r0, #DDR2_DRIC1]
 199         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_7
 200         strh    r1, [r0, #DDR2_DRIC2]
 201         ldr     r1, =MB86R0x_DDR2_DRCI_CMD
 202         strh    r1, [r0, #DDR2_DRIC]
 203
 204         wait_timer      18                      /* 105ns wait */
 205
 206         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_8
 207         strh    r1, [r0, #DDR2_DRIC1]
 208         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_8
 209         strh    r1, [r0, #DDR2_DRIC2]
 210         ldr     r1, =MB86R0x_DDR2_DRCI_CMD
 211         strh    r1, [r0, #DDR2_DRIC]
 212
 213         wait_timer      200                     /* MRS to OCD: 200clock */
 214
 215         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_9
 216         strh    r1, [r0, #DDR2_DRIC1]
 217         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_9
 218         strh    r1, [r0, #DDR2_DRIC2]
 219         ldr     r1, =MB86R0x_DDR2_DRCI_CMD
 220         strh    r1, [r0, #DDR2_DRIC]
 221
 222         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_10
 223         strh    r1, [r0, #DDR2_DRIC1]
 224         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_10
 225         strh    r1, [r0, #DDR2_DRIC2]
 226         ldr     r1, =MB86R0x_DDR2_DRCI_CMD
 227         strh    r1, [r0, #DDR2_DRIC]
 228
 229         ldr     r1, =CONFIG_SYS_DDR2_DRCM_INIT
 230         strh    r1, [r0, #DDR2_DRCM]
 231
 232         ldr     r1, =CONFIG_SYS_DDR2_DRCST1_INIT
 233         strh    r1, [r0, #DDR2_DRCST1]
 234
 235         ldr     r1, =CONFIG_SYS_DDR2_DRCST2_INIT
 236         strh    r1, [r0, #DDR2_DRCST2]
 237
 238         ldr     r1, =CONFIG_SYS_DDR2_DRCR_INIT
 239         strh    r1, [r0, #DDR2_DRCR]
 240
 241         ldr     r1, =CONFIG_SYS_DDR2_DRCF_INIT
 242         strh    r1, [r0, #DDR2_DRCF]
 243
 244         ldr     r1, =CONFIG_SYS_DDR2_DRASR_INIT
 245         strh    r1, [r0, #DDR2_DRASR]
 246
 247         /*
 248          * (11) ODT setting
 249          */
 250         ldr     r1, =CONFIG_SYS_DDR2_DROBS_INIT
 251         strh    r1, [r0, #DDR2_DROBS]
 252         ldr     r1, =CONFIG_SYS_DDR2_DROABA_INIT
 253         strh    r1, [r0, #DDR2_DROABA]
 254         ldr     r1, =CONFIG_SYS_DDR2_DRIBSODT1_INIT
 255         strh    r1, [r0, #DDR2_DRIBSODT1]
 256
 257         /*
 258          * (12) Shift to ODTCONT ON (SDRAM side) and DDR2 usual operation mode
 259          */
 260         ldr     r1, =CONFIG_SYS_DDR2_DROS_INIT
 261         strh    r1, [r0, #DDR2_DROS]
 262         ldr     r1, =MB86R0x_DDR2_DRCI_NORMAL
 263         strh    r1, [r0, #DDR2_DRIC]
 264
 265         mov pc, lr