board/taskit/stamp9g20/stamp9g20.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * Achim Ehrlich <aehrlich@taskit.de>
   7  * taskit GmbH <www.taskit.de>
   8  *
   9  * (C) Copyright 2012-
  10  * Markus Hubig <mhubig@imko.de>
  11  * IMKO GmbH <www.imko.de>
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #include <common.h>
  17 #include <asm/io.h>
  18 #include <asm/arch/at91sam9260_matrix.h>
  19 #include <asm/arch/at91sam9_smc.h>
  20 #include <asm/arch/at91_common.h>
  21 #include <asm/arch/at91_pmc.h>
  22 #include <asm/arch/at91_rstc.h>
  23 #include <asm/arch/gpio.h>
  24 #include <watchdog.h>
  25
  26 #ifdef CONFIG_MACB
  27 # include <net.h>
  28 # include <netdev.h>
  29 #endif
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 static void stamp9G20_nand_hw_init(void)
  34 {
  35         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  36         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  37         unsigned long csa;
  38
  39         /* Assign CS3 to NAND/SmartMedia Interface */
  40         csa = readl(&matrix->ebicsa);
  41         csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
  42         writel(csa, &matrix->ebicsa);
  43
  44         /* Configure SMC CS3 for NAND/SmartMedia */
  45         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  46                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  47                 &smc->cs[3].setup);
  48         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  49                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  50                 &smc->cs[3].pulse);
  51         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  52                 &smc->cs[3].cycle);
  53         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  54                 AT91_SMC_MODE_EXNW_DISABLE |
  55                 AT91_SMC_MODE_DBW_8 |
  56                 AT91_SMC_MODE_TDF_CYCLE(2),
  57                 &smc->cs[3].mode);
  58
  59         /* Configure RDY/BSY */
  60         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  61
  62         /* Enable NandFlash */
  63         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  64 }
  65
  66 #ifdef CONFIG_MACB
  67 static void stamp9G20_macb_hw_init(void)
  68 {
  69         struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
  70         struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
  71         unsigned long erstl;
  72
  73         /* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */
  74         at91_set_gpio_output(AT91_PIN_PA26, 0);
  75
  76         /*
  77          * Disable pull-up on:
  78          *      RXDV (PA17) => PHY normal mode (not Test mode)
  79          *      ERX0 (PA14) => PHY ADDR0
  80          *      ERX1 (PA15) => PHY ADDR1
  81          *      ERX2 (PA25) => PHY ADDR2
  82          *      ERX3 (PA26) => PHY ADDR3
  83          *      ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
  84          *
  85          * PHY has internal pull-down
  86          */
  87         writel(pin_to_mask(AT91_PIN_PA14) |
  88                 pin_to_mask(AT91_PIN_PA15) |
  89                 pin_to_mask(AT91_PIN_PA17) |
  90                 pin_to_mask(AT91_PIN_PA18) |
  91                 pin_to_mask(AT91_PIN_PA28),
  92                 &pioa->pudr);
  93
  94         erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
  95
  96         /* Need to reset PHY -> 500ms reset */
  97         writel(AT91_RSTC_KEY | (AT91_RSTC_MR_ERSTL(13) &
  98                                 ~AT91_RSTC_MR_URSTEN), &rstc->mr);
  99         writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
 100
 101         /* Wait for end of hardware reset */
 102         unsigned long start = get_timer(0);
 103         unsigned long timeout = 1000; /* 1000ms */
 104
 105         while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) {
 106
 107                 /* avoid shutdown by watchdog */
 108                 WATCHDOG_RESET();
 109                 mdelay(10);
 110
 111                 /* timeout for not getting stuck in an endless loop */
 112                 if (get_timer(start) >= timeout) {
 113                         puts("*** ERROR: Timeout waiting for PHY reset!\n");
 114                         break;
 115                 };
 116         };
 117
 118         /* Restore NRST value */
 119         writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
 120                 &rstc->mr);
 121
 122         /* Re-enable pull-up */
 123         writel(pin_to_mask(AT91_PIN_PA14) |
 124                 pin_to_mask(AT91_PIN_PA15) |
 125                 pin_to_mask(AT91_PIN_PA17) |
 126                 pin_to_mask(AT91_PIN_PA18) |
 127                 pin_to_mask(AT91_PIN_PA28),
 128                 &pioa->puer);
 129
 130         /* Initialize EMAC=MACB hardware */
 131         at91_macb_hw_init();
 132 }
 133 #endif /* CONFIG_MACB */
 134
 135 int board_early_init_f(void)
 136 {
 137         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 138
 139         /* Enable clocks for all PIOs */
 140         writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
 141                 (1 << ATMEL_ID_PIOC), &pmc->pcer);
 142
 143         return 0;
 144 }
 145
 146 int board_postclk_init(void)
 147 {
 148         /*
 149          * Initialize the serial interface here, because be need a running
 150          * timer to set PC9 to high and wait for some time to enable the
 151          * level converter of the RS232 interface on the PortuxG20 board.
 152          */
 153
 154 #ifdef CONFIG_PORTUXG20
 155         at91_set_gpio_output(AT91_PIN_PC9, 1);
 156         mdelay(1);
 157 #endif
 158         at91_seriald_hw_init();
 159
 160         return 0;
 161 }
 162
 163 int board_init(void)
 164 {
 165         /* Adress of boot parameters */
 166         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 167
 168         stamp9G20_nand_hw_init();
 169 #ifdef CONFIG_MACB
 170         stamp9G20_macb_hw_init();
 171 #endif
 172         return 0;
 173 }
 174
 175 int dram_init(void)
 176 {
 177         gd->ram_size = get_ram_size(
 178                 (void *)CONFIG_SYS_SDRAM_BASE,
 179                 CONFIG_SYS_SDRAM_SIZE);
 180         return 0;
 181 }
 182
 183 #ifdef CONFIG_MACB
 184 int board_eth_init(bd_t *bis)
 185 {
 186         return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
 187 }
 188 #endif /* CONFIG_MACB */