board/ti/beagle_x15/board.c

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   3  *
   4  * Author: Felipe Balbi <balbi@ti.com>
   5  *
   6  * Based on board/ti/dra7xx/evm.c
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <palmas.h>
  13 #include <sata.h>
  14 #include <usb.h>
  15 #include <asm/omap_common.h>
  16 #include <asm/emif.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/arch/mmc_host_def.h>
  20 #include <asm/arch/sata.h>
  21 #include <asm/arch/gpio.h>
  22 #include <environment.h>
  23
  24 #include "mux_data.h"
  25
  26 #ifdef CONFIG_DRIVER_TI_CPSW
  27 #include <cpsw.h>
  28 #endif
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 const struct omap_sysinfo sysinfo = {
  33         "Board: BeagleBoard x15\n"
  34 };
  35
  36 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  37         .dmm_lisa_map_3 = 0x80740300,
  38         .is_ma_present  = 0x1
  39 };
  40
  41 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  42 {
  43         *dmm_lisa_regs = &beagle_x15_lisa_regs;
  44 }
  45
  46 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
  47         .sdram_config_init      = 0x61851b32,
  48         .sdram_config           = 0x61851b32,
  49         .sdram_config2          = 0x00000000,
  50         .ref_ctrl               = 0x000040F1,
  51         .ref_ctrl_final         = 0x00001035,
  52         .sdram_tim1             = 0xceef266b,
  53         .sdram_tim2             = 0x328f7fda,
  54         .sdram_tim3             = 0x027f88a8,
  55         .read_idle_ctrl         = 0x00050000,
  56         .zq_config              = 0x0007190b,
  57         .temp_alert_config      = 0x00000000,
  58         .emif_ddr_phy_ctlr_1_init = 0x0024400b,
  59         .emif_ddr_phy_ctlr_1    = 0x0e24400b,
  60         .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  61         .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
  62         .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
  63         .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
  64         .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
  65         .emif_rd_wr_lvl_rmp_win = 0x00000000,
  66         .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  67         .emif_rd_wr_lvl_ctl     = 0x00000000,
  68         .emif_rd_wr_exec_thresh = 0x00000305
  69 };
  70
  71 /* Ext phy ctrl regs 1-35 */
  72 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
  73         0x10040100,
  74         0x00740074,
  75         0x00780078,
  76         0x007c007c,
  77         0x007b007b,
  78         0x00800080,
  79         0x00360036,
  80         0x00340034,
  81         0x00360036,
  82         0x00350035,
  83         0x00350035,
  84
  85         0x01ff01ff,
  86         0x01ff01ff,
  87         0x01ff01ff,
  88         0x01ff01ff,
  89         0x01ff01ff,
  90
  91         0x00430043,
  92         0x003e003e,
  93         0x004a004a,
  94         0x00470047,
  95         0x00400040,
  96
  97         0x00000000,
  98         0x00600020,
  99         0x40011080,
 100         0x08102040,
 101
 102         0x00400040,
 103         0x00400040,
 104         0x00400040,
 105         0x00400040,
 106         0x00400040,
 107         0x0,
 108         0x0,
 109         0x0,
 110         0x0,
 111         0x0
 112 };
 113
 114 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 115         .sdram_config_init      = 0x61851b32,
 116         .sdram_config           = 0x61851b32,
 117         .sdram_config2          = 0x00000000,
 118         .ref_ctrl               = 0x000040F1,
 119         .ref_ctrl_final         = 0x00001035,
 120         .sdram_tim1             = 0xceef266b,
 121         .sdram_tim2             = 0x328f7fda,
 122         .sdram_tim3             = 0x027f88a8,
 123         .read_idle_ctrl         = 0x00050000,
 124         .zq_config              = 0x0007190b,
 125         .temp_alert_config      = 0x00000000,
 126         .emif_ddr_phy_ctlr_1_init = 0x0024400b,
 127         .emif_ddr_phy_ctlr_1    = 0x0e24400b,
 128         .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
 129         .emif_ddr_ext_phy_ctrl_2 = 0x00820082,
 130         .emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
 131         .emif_ddr_ext_phy_ctrl_4 = 0x00800080,
 132         .emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
 133         .emif_rd_wr_lvl_rmp_win = 0x00000000,
 134         .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
 135         .emif_rd_wr_lvl_ctl     = 0x00000000,
 136         .emif_rd_wr_exec_thresh = 0x00000305
 137 };
 138
 139 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 140         0x10040100,
 141         0x00820082,
 142         0x008b008b,
 143         0x00800080,
 144         0x007e007e,
 145         0x00800080,
 146         0x00370037,
 147         0x00390039,
 148         0x00360036,
 149         0x00370037,
 150         0x00350035,
 151         0x01ff01ff,
 152         0x01ff01ff,
 153         0x01ff01ff,
 154         0x01ff01ff,
 155         0x01ff01ff,
 156         0x00540054,
 157         0x00540054,
 158         0x004e004e,
 159         0x004c004c,
 160         0x00400040,
 161
 162         0x00000000,
 163         0x00600020,
 164         0x40011080,
 165         0x08102040,
 166
 167         0x00400040,
 168         0x00400040,
 169         0x00400040,
 170         0x00400040,
 171         0x00400040,
 172         0x0,
 173         0x0,
 174         0x0,
 175         0x0,
 176         0x0
 177 };
 178
 179 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 180 {
 181         switch (emif_nr) {
 182         case 1:
 183                 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 184                 break;
 185         case 2:
 186                 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 187                 break;
 188         }
 189 }
 190
 191 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 192 {
 193         switch (emif_nr) {
 194         case 1:
 195                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 196                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 197                 break;
 198         case 2:
 199                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 200                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 201                 break;
 202         }
 203 }
 204
 205 struct vcores_data beagle_x15_volts = {
 206         .mpu.value              = VDD_MPU_DRA752,
 207         .mpu.efuse.reg          = STD_FUSE_OPP_VMIN_MPU_NOM,
 208         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 209         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 210         .mpu.pmic               = &tps659038,
 211
 212         .eve.value              = VDD_EVE_DRA752,
 213         .eve.efuse.reg          = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 214         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 215         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 216         .eve.pmic               = &tps659038,
 217
 218         .gpu.value              = VDD_GPU_DRA752,
 219         .gpu.efuse.reg          = STD_FUSE_OPP_VMIN_GPU_NOM,
 220         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 221         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 222         .gpu.pmic               = &tps659038,
 223
 224         .core.value             = VDD_CORE_DRA752,
 225         .core.efuse.reg         = STD_FUSE_OPP_VMIN_CORE_NOM,
 226         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 227         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 228         .core.pmic              = &tps659038,
 229
 230         .iva.value              = VDD_IVA_DRA752,
 231         .iva.efuse.reg          = STD_FUSE_OPP_VMIN_IVA_NOM,
 232         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 233         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 234         .iva.pmic               = &tps659038,
 235 };
 236
 237 void hw_data_init(void)
 238 {
 239         *prcm = &dra7xx_prcm;
 240         *dplls_data = &dra7xx_dplls;
 241         *omap_vcores = &beagle_x15_volts;
 242         *ctrl = &dra7xx_ctrl;
 243 }
 244
 245 int board_init(void)
 246 {
 247         gpmc_init();
 248         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 249
 250         return 0;
 251 }
 252
 253 int board_late_init(void)
 254 {
 255         init_sata(0);
 256         /*
 257          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 258          * This is the POWERHOLD-in-Low behavior.
 259          */
 260         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 261         return 0;
 262 }
 263
 264 void set_muxconf_regs_essential(void)
 265 {
 266         do_set_mux32((*ctrl)->control_padconf_core_base,
 267                      core_padconf_array_essential,
 268                      sizeof(core_padconf_array_essential) /
 269                      sizeof(struct pad_conf_entry));
 270 }
 271
 272 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 273 int board_mmc_init(bd_t *bis)
 274 {
 275         omap_mmc_init(0, 0, 0, -1, -1);
 276         omap_mmc_init(1, 0, 0, -1, -1);
 277         return 0;
 278 }
 279 #endif
 280
 281 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 282 int spl_start_uboot(void)
 283 {
 284         /* break into full u-boot on 'c' */
 285         if (serial_tstc() && serial_getc() == 'c')
 286                 return 1;
 287
 288 #ifdef CONFIG_SPL_ENV_SUPPORT
 289         env_init();
 290         env_relocate_spec();
 291         if (getenv_yesno("boot_os") != 1)
 292                 return 1;
 293 #endif
 294
 295         return 0;
 296 }
 297 #endif
 298
 299 #ifdef CONFIG_DRIVER_TI_CPSW
 300
 301 /* Delay value to add to calibrated value */
 302 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 303 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 304 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 305 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 306 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 307 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 308 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 309 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 310 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 311 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 312
 313 static void cpsw_control(int enabled)
 314 {
 315         /* VTP can be added here */
 316 }
 317
 318 static struct cpsw_slave_data cpsw_slaves[] = {
 319         {
 320                 .slave_reg_ofs  = 0x208,
 321                 .sliver_reg_ofs = 0xd80,
 322                 .phy_addr       = 1,
 323         },
 324         {
 325                 .slave_reg_ofs  = 0x308,
 326                 .sliver_reg_ofs = 0xdc0,
 327                 .phy_addr       = 2,
 328         },
 329 };
 330
 331 static struct cpsw_platform_data cpsw_data = {
 332         .mdio_base              = CPSW_MDIO_BASE,
 333         .cpsw_base              = CPSW_BASE,
 334         .mdio_div               = 0xff,
 335         .channels               = 8,
 336         .cpdma_reg_ofs          = 0x800,
 337         .slaves                 = 1,
 338         .slave_data             = cpsw_slaves,
 339         .ale_reg_ofs            = 0xd00,
 340         .ale_entries            = 1024,
 341         .host_port_reg_ofs      = 0x108,
 342         .hw_stats_reg_ofs       = 0x900,
 343         .bd_ram_ofs             = 0x2000,
 344         .mac_control            = (1 << 5),
 345         .control                = cpsw_control,
 346         .host_port_num          = 0,
 347         .version                = CPSW_CTRL_VERSION_2,
 348 };
 349
 350 int board_eth_init(bd_t *bis)
 351 {
 352         int ret;
 353         uint8_t mac_addr[6];
 354         uint32_t mac_hi, mac_lo;
 355         uint32_t ctrl_val;
 356
 357         /* try reading mac address from efuse */
 358         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 359         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 360         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 361         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 362         mac_addr[2] = mac_hi & 0xFF;
 363         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 364         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 365         mac_addr[5] = mac_lo & 0xFF;
 366
 367         if (!getenv("ethaddr")) {
 368                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 369
 370                 if (is_valid_ethaddr(mac_addr))
 371                         eth_setenv_enetaddr("ethaddr", mac_addr);
 372         }
 373
 374         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 375         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 376         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 377         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 378         mac_addr[2] = mac_hi & 0xFF;
 379         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 380         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 381         mac_addr[5] = mac_lo & 0xFF;
 382
 383         if (!getenv("eth1addr")) {
 384                 if (is_valid_ethaddr(mac_addr))
 385                         eth_setenv_enetaddr("eth1addr", mac_addr);
 386         }
 387
 388         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 389         ctrl_val |= 0x22;
 390         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 391
 392         ret = cpsw_register(&cpsw_data);
 393         if (ret < 0)
 394                 printf("Error %d registering CPSW switch\n", ret);
 395
 396         return ret;
 397 }
 398 #endif