board/ti/beagle_x15/board.c

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   3  *
   4  * Author: Felipe Balbi <balbi@ti.com>
   5  *
   6  * Based on board/ti/dra7xx/evm.c
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <palmas.h>
  13 #include <sata.h>
  14 #include <usb.h>
  15 #include <asm/omap_common.h>
  16 #include <asm/emif.h>
  17 #include <asm/gpio.h>
  18 #include <asm/arch/gpio.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/dra7xx_iodelay.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/arch/mmc_host_def.h>
  23 #include <asm/arch/sata.h>
  24 #include <asm/arch/gpio.h>
  25 #include <environment.h>
  26
  27 #include "mux_data.h"
  28
  29 #ifdef CONFIG_DRIVER_TI_CPSW
  30 #include <cpsw.h>
  31 #endif
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 /* GPIO 7_11 */
  36 #define GPIO_DDR_VTT_EN 203
  37
  38 const struct omap_sysinfo sysinfo = {
  39         "Board: BeagleBoard x15\n"
  40 };
  41
  42 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  43         .dmm_lisa_map_3 = 0x80740300,
  44         .is_ma_present  = 0x1
  45 };
  46
  47 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  48 {
  49         *dmm_lisa_regs = &beagle_x15_lisa_regs;
  50 }
  51
  52 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
  53         .sdram_config_init      = 0x61851b32,
  54         .sdram_config           = 0x61851b32,
  55         .sdram_config2          = 0x00000000,
  56         .ref_ctrl               = 0x000040F1,
  57         .ref_ctrl_final         = 0x00001035,
  58         .sdram_tim1             = 0xceef266b,
  59         .sdram_tim2             = 0x328f7fda,
  60         .sdram_tim3             = 0x027f88a8,
  61         .read_idle_ctrl         = 0x00050000,
  62         .zq_config              = 0x0007190b,
  63         .temp_alert_config      = 0x00000000,
  64         .emif_ddr_phy_ctlr_1_init = 0x0024400b,
  65         .emif_ddr_phy_ctlr_1    = 0x0e24400b,
  66         .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  67         .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
  68         .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
  69         .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
  70         .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
  71         .emif_rd_wr_lvl_rmp_win = 0x00000000,
  72         .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  73         .emif_rd_wr_lvl_ctl     = 0x00000000,
  74         .emif_rd_wr_exec_thresh = 0x00000305
  75 };
  76
  77 /* Ext phy ctrl regs 1-35 */
  78 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
  79         0x10040100,
  80         0x00740074,
  81         0x00780078,
  82         0x007c007c,
  83         0x007b007b,
  84         0x00800080,
  85         0x00360036,
  86         0x00340034,
  87         0x00360036,
  88         0x00350035,
  89         0x00350035,
  90
  91         0x01ff01ff,
  92         0x01ff01ff,
  93         0x01ff01ff,
  94         0x01ff01ff,
  95         0x01ff01ff,
  96
  97         0x00430043,
  98         0x003e003e,
  99         0x004a004a,
 100         0x00470047,
 101         0x00400040,
 102
 103         0x00000000,
 104         0x00600020,
 105         0x40011080,
 106         0x08102040,
 107
 108         0x00400040,
 109         0x00400040,
 110         0x00400040,
 111         0x00400040,
 112         0x00400040,
 113         0x0,
 114         0x0,
 115         0x0,
 116         0x0,
 117         0x0
 118 };
 119
 120 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 121         .sdram_config_init      = 0x61851b32,
 122         .sdram_config           = 0x61851b32,
 123         .sdram_config2          = 0x00000000,
 124         .ref_ctrl               = 0x000040F1,
 125         .ref_ctrl_final         = 0x00001035,
 126         .sdram_tim1             = 0xceef266b,
 127         .sdram_tim2             = 0x328f7fda,
 128         .sdram_tim3             = 0x027f88a8,
 129         .read_idle_ctrl         = 0x00050000,
 130         .zq_config              = 0x0007190b,
 131         .temp_alert_config      = 0x00000000,
 132         .emif_ddr_phy_ctlr_1_init = 0x0024400b,
 133         .emif_ddr_phy_ctlr_1    = 0x0e24400b,
 134         .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
 135         .emif_ddr_ext_phy_ctrl_2 = 0x00820082,
 136         .emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
 137         .emif_ddr_ext_phy_ctrl_4 = 0x00800080,
 138         .emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
 139         .emif_rd_wr_lvl_rmp_win = 0x00000000,
 140         .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
 141         .emif_rd_wr_lvl_ctl     = 0x00000000,
 142         .emif_rd_wr_exec_thresh = 0x00000305
 143 };
 144
 145 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 146         0x10040100,
 147         0x00820082,
 148         0x008b008b,
 149         0x00800080,
 150         0x007e007e,
 151         0x00800080,
 152         0x00370037,
 153         0x00390039,
 154         0x00360036,
 155         0x00370037,
 156         0x00350035,
 157         0x01ff01ff,
 158         0x01ff01ff,
 159         0x01ff01ff,
 160         0x01ff01ff,
 161         0x01ff01ff,
 162         0x00540054,
 163         0x00540054,
 164         0x004e004e,
 165         0x004c004c,
 166         0x00400040,
 167
 168         0x00000000,
 169         0x00600020,
 170         0x40011080,
 171         0x08102040,
 172
 173         0x00400040,
 174         0x00400040,
 175         0x00400040,
 176         0x00400040,
 177         0x00400040,
 178         0x0,
 179         0x0,
 180         0x0,
 181         0x0,
 182         0x0
 183 };
 184
 185 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 186 {
 187         switch (emif_nr) {
 188         case 1:
 189                 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 190                 break;
 191         case 2:
 192                 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 193                 break;
 194         }
 195 }
 196
 197 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 198 {
 199         switch (emif_nr) {
 200         case 1:
 201                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 202                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 203                 break;
 204         case 2:
 205                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 206                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 207                 break;
 208         }
 209 }
 210
 211 struct vcores_data beagle_x15_volts = {
 212         .mpu.value              = VDD_MPU_DRA752,
 213         .mpu.efuse.reg          = STD_FUSE_OPP_VMIN_MPU_NOM,
 214         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 215         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 216         .mpu.pmic               = &tps659038,
 217
 218         .eve.value              = VDD_EVE_DRA752,
 219         .eve.efuse.reg          = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 220         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 221         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 222         .eve.pmic               = &tps659038,
 223
 224         .gpu.value              = VDD_GPU_DRA752,
 225         .gpu.efuse.reg          = STD_FUSE_OPP_VMIN_GPU_NOM,
 226         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 227         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 228         .gpu.pmic               = &tps659038,
 229
 230         .core.value             = VDD_CORE_DRA752,
 231         .core.efuse.reg         = STD_FUSE_OPP_VMIN_CORE_NOM,
 232         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 233         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 234         .core.pmic              = &tps659038,
 235
 236         .iva.value              = VDD_IVA_DRA752,
 237         .iva.efuse.reg          = STD_FUSE_OPP_VMIN_IVA_NOM,
 238         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 239         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 240         .iva.pmic               = &tps659038,
 241 };
 242
 243 void hw_data_init(void)
 244 {
 245         *prcm = &dra7xx_prcm;
 246         *dplls_data = &dra7xx_dplls;
 247         *omap_vcores = &beagle_x15_volts;
 248         *ctrl = &dra7xx_ctrl;
 249 }
 250
 251 int board_init(void)
 252 {
 253         gpmc_init();
 254         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 255
 256         return 0;
 257 }
 258
 259 int board_late_init(void)
 260 {
 261         init_sata(0);
 262         /*
 263          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 264          * This is the POWERHOLD-in-Low behavior.
 265          */
 266         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 267         return 0;
 268 }
 269
 270 void set_muxconf_regs_essential(void)
 271 {
 272         do_set_mux32((*ctrl)->control_padconf_core_base,
 273                      early_padconf, ARRAY_SIZE(early_padconf));
 274 }
 275
 276 #ifdef CONFIG_IODELAY_RECALIBRATION
 277 void recalibrate_iodelay(void)
 278 {
 279         __recalibrate_iodelay(core_padconf_array_essential,
 280                               ARRAY_SIZE(core_padconf_array_essential),
 281                               iodelay_cfg_array, ARRAY_SIZE(iodelay_cfg_array));
 282 }
 283 #endif
 284
 285 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 286 int board_mmc_init(bd_t *bis)
 287 {
 288         omap_mmc_init(0, 0, 0, -1, -1);
 289         omap_mmc_init(1, 0, 0, -1, -1);
 290         return 0;
 291 }
 292 #endif
 293
 294 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 295 int spl_start_uboot(void)
 296 {
 297         /* break into full u-boot on 'c' */
 298         if (serial_tstc() && serial_getc() == 'c')
 299                 return 1;
 300
 301 #ifdef CONFIG_SPL_ENV_SUPPORT
 302         env_init();
 303         env_relocate_spec();
 304         if (getenv_yesno("boot_os") != 1)
 305                 return 1;
 306 #endif
 307
 308         return 0;
 309 }
 310 #endif
 311
 312 #ifdef CONFIG_DRIVER_TI_CPSW
 313
 314 /* Delay value to add to calibrated value */
 315 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 316 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 317 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 318 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 319 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 320 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 321 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 322 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 323 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 324 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 325
 326 static void cpsw_control(int enabled)
 327 {
 328         /* VTP can be added here */
 329 }
 330
 331 static struct cpsw_slave_data cpsw_slaves[] = {
 332         {
 333                 .slave_reg_ofs  = 0x208,
 334                 .sliver_reg_ofs = 0xd80,
 335                 .phy_addr       = 1,
 336         },
 337         {
 338                 .slave_reg_ofs  = 0x308,
 339                 .sliver_reg_ofs = 0xdc0,
 340                 .phy_addr       = 2,
 341         },
 342 };
 343
 344 static struct cpsw_platform_data cpsw_data = {
 345         .mdio_base              = CPSW_MDIO_BASE,
 346         .cpsw_base              = CPSW_BASE,
 347         .mdio_div               = 0xff,
 348         .channels               = 8,
 349         .cpdma_reg_ofs          = 0x800,
 350         .slaves                 = 1,
 351         .slave_data             = cpsw_slaves,
 352         .ale_reg_ofs            = 0xd00,
 353         .ale_entries            = 1024,
 354         .host_port_reg_ofs      = 0x108,
 355         .hw_stats_reg_ofs       = 0x900,
 356         .bd_ram_ofs             = 0x2000,
 357         .mac_control            = (1 << 5),
 358         .control                = cpsw_control,
 359         .host_port_num          = 0,
 360         .version                = CPSW_CTRL_VERSION_2,
 361 };
 362
 363 int board_eth_init(bd_t *bis)
 364 {
 365         int ret;
 366         uint8_t mac_addr[6];
 367         uint32_t mac_hi, mac_lo;
 368         uint32_t ctrl_val;
 369
 370         /* try reading mac address from efuse */
 371         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 372         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 373         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 374         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 375         mac_addr[2] = mac_hi & 0xFF;
 376         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 377         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 378         mac_addr[5] = mac_lo & 0xFF;
 379
 380         if (!getenv("ethaddr")) {
 381                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 382
 383                 if (is_valid_ethaddr(mac_addr))
 384                         eth_setenv_enetaddr("ethaddr", mac_addr);
 385         }
 386
 387         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 388         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 389         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 390         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 391         mac_addr[2] = mac_hi & 0xFF;
 392         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 393         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 394         mac_addr[5] = mac_lo & 0xFF;
 395
 396         if (!getenv("eth1addr")) {
 397                 if (is_valid_ethaddr(mac_addr))
 398                         eth_setenv_enetaddr("eth1addr", mac_addr);
 399         }
 400
 401         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 402         ctrl_val |= 0x22;
 403         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 404
 405         ret = cpsw_register(&cpsw_data);
 406         if (ret < 0)
 407                 printf("Error %d registering CPSW switch\n", ret);
 408
 409         return ret;
 410 }
 411 #endif
 412
 413 #ifdef CONFIG_BOARD_EARLY_INIT_F
 414 /* VTT regulator enable */
 415 static inline void vtt_regulator_enable(void)
 416 {
 417         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
 418                 return;
 419
 420         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 421         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 422 }
 423
 424 int board_early_init_f(void)
 425 {
 426         vtt_regulator_enable();
 427         return 0;
 428 }
 429 #endif