board/ti/ti814x/evm.c

   1 /*
   2  * evm.c
   3  *
   4  * Board functions for TI814x EVM
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <cpsw.h>
  13 #include <errno.h>
  14 #include <spl.h>
  15 #include <asm/arch/cpu.h>
  16 #include <asm/arch/hardware.h>
  17 #include <asm/arch/omap.h>
  18 #include <asm/arch/ddr_defs.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/gpio.h>
  21 #include <asm/arch/mmc_host_def.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/io.h>
  24 #include <asm/emif.h>
  25 #include <asm/gpio.h>
  26 #include "evm.h"
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 #ifdef CONFIG_SPL_BUILD
  31 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
  32 #endif
  33
  34 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  35
  36 /* UART Defines */
  37 #ifdef CONFIG_SPL_BUILD
  38 static void uart_enable(void)
  39 {
  40         /* UART softreset */
  41         uart_soft_reset();
  42 }
  43
  44 static void wdt_disable(void)
  45 {
  46         writel(0xAAAA, &wdtimer->wdtwspr);
  47         while (readl(&wdtimer->wdtwwps) != 0x0)
  48                 ;
  49         writel(0x5555, &wdtimer->wdtwspr);
  50         while (readl(&wdtimer->wdtwwps) != 0x0)
  51                 ;
  52 }
  53
  54 static const struct cmd_control evm_ddr2_cctrl_data = {
  55         .cmd0csratio    = 0x80,
  56         .cmd0dldiff     = 0x04,
  57         .cmd0iclkout    = 0x00,
  58
  59         .cmd1csratio    = 0x80,
  60         .cmd1dldiff     = 0x04,
  61         .cmd1iclkout    = 0x00,
  62
  63         .cmd2csratio    = 0x80,
  64         .cmd2dldiff     = 0x04,
  65         .cmd2iclkout    = 0x00,
  66 };
  67
  68 static const struct emif_regs evm_ddr2_emif0_regs = {
  69         .sdram_config                   = 0x40801ab2,
  70         .ref_ctrl                       = 0x10000c30,
  71         .sdram_tim1                     = 0x0aaaf552,
  72         .sdram_tim2                     = 0x043631d2,
  73         .sdram_tim3                     = 0x00000327,
  74         .emif_ddr_phy_ctlr_1            = 0x00000007
  75 };
  76
  77 static const struct emif_regs evm_ddr2_emif1_regs = {
  78         .sdram_config                   = 0x40801ab2,
  79         .ref_ctrl                       = 0x10000c30,
  80         .sdram_tim1                     = 0x0aaaf552,
  81         .sdram_tim2                     = 0x043631d2,
  82         .sdram_tim3                     = 0x00000327,
  83         .emif_ddr_phy_ctlr_1            = 0x00000007
  84 };
  85
  86 const struct dmm_lisa_map_regs evm_lisa_map_regs = {
  87         .dmm_lisa_map_0                 = 0x00000000,
  88         .dmm_lisa_map_1                 = 0x00000000,
  89         .dmm_lisa_map_2                 = 0x806c0300,
  90         .dmm_lisa_map_3                 = 0x806c0300,
  91 };
  92
  93 static const struct ddr_data evm_ddr2_data = {
  94         .datardsratio0          = ((0x35<<10) | (0x35<<0)),
  95         .datawdsratio0          = ((0x20<<10) | (0x20<<0)),
  96         .datawiratio0           = ((0<<10) | (0<<0)),
  97         .datagiratio0           = ((0<<10) | (0<<0)),
  98         .datafwsratio0          = ((0x90<<10) | (0x90<<0)),
  99         .datawrsratio0          = ((0x50<<10) | (0x50<<0)),
 100         .datauserank0delay      = 1,
 101         .datadldiff0            = 0x4,
 102 };
 103 #endif
 104
 105 /*
 106  * early system init of muxing and clocks.
 107  */
 108 void s_init(void)
 109 {
 110 #ifdef CONFIG_SPL_BUILD
 111         /*
 112          * Save the boot parameters passed from romcode.
 113          * We cannot delay the saving further than this,
 114          * to prevent overwrites.
 115          */
 116 #ifdef CONFIG_SPL_BUILD
 117         save_omap_boot_params();
 118 #endif
 119
 120         /* WDT1 is already running when the bootloader gets control
 121          * Disable it to avoid "random" resets
 122          */
 123         wdt_disable();
 124
 125         /* Enable timer */
 126         timer_init();
 127
 128         setup_clocks_for_console();
 129
 130         /* Set UART pins */
 131         enable_uart0_pin_mux();
 132
 133         /* Set MMC pins */
 134         enable_mmc1_pin_mux();
 135
 136         /* Set Ethernet pins */
 137         enable_enet_pin_mux();
 138
 139         /* Enable UART */
 140         uart_enable();
 141
 142         gd = &gdata;
 143
 144         preloader_console_init();
 145
 146         /* Setup the PLLs and the clocks for the peripherals */
 147         prcm_init();
 148
 149         /* Enable RTC32K clock */
 150         rtc32k_enable();
 151
 152         config_dmm(&evm_lisa_map_regs);
 153
 154         config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
 155                    &evm_ddr2_emif0_regs, 0);
 156         config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
 157                    &evm_ddr2_emif1_regs, 1);
 158 #endif
 159 }
 160
 161 /*
 162  * Basic board specific setup.  Pinmux has been handled already.
 163  */
 164 int board_init(void)
 165 {
 166         gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
 167         return 0;
 168 }
 169
 170 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 171 int board_mmc_init(bd_t *bis)
 172 {
 173         omap_mmc_init(1, 0, 0, -1, -1);
 174
 175         return 0;
 176 }
 177 #endif
 178
 179 #ifdef CONFIG_DRIVER_TI_CPSW
 180 static void cpsw_control(int enabled)
 181 {
 182         /* VTP can be added here */
 183
 184         return;
 185 }
 186
 187 static struct cpsw_slave_data cpsw_slaves[] = {
 188         {
 189                 .slave_reg_ofs  = 0x50,
 190                 .sliver_reg_ofs = 0x700,
 191                 .phy_id         = 1,
 192         },
 193         {
 194                 .slave_reg_ofs  = 0x90,
 195                 .sliver_reg_ofs = 0x740,
 196                 .phy_id         = 0,
 197         },
 198 };
 199
 200 static struct cpsw_platform_data cpsw_data = {
 201         .mdio_base              = CPSW_MDIO_BASE,
 202         .cpsw_base              = CPSW_BASE,
 203         .mdio_div               = 0xff,
 204         .channels               = 8,
 205         .cpdma_reg_ofs          = 0x100,
 206         .slaves                 = 1,
 207         .slave_data             = cpsw_slaves,
 208         .ale_reg_ofs            = 0x600,
 209         .ale_entries            = 1024,
 210         .host_port_reg_ofs      = 0x28,
 211         .hw_stats_reg_ofs       = 0x400,
 212         .bd_ram_ofs             = 0x2000,
 213         .mac_control            = (1 << 5),
 214         .control                = cpsw_control,
 215         .host_port_num          = 0,
 216         .version                = CPSW_CTRL_VERSION_1,
 217 };
 218 #endif
 219
 220 int board_eth_init(bd_t *bis)
 221 {
 222         uint8_t mac_addr[6];
 223         uint32_t mac_hi, mac_lo;
 224
 225         if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
 226                 printf("<ethaddr> not set. Reading from E-fuse\n");
 227                 /* try reading mac address from efuse */
 228                 mac_lo = readl(&cdev->macid0l);
 229                 mac_hi = readl(&cdev->macid0h);
 230                 mac_addr[0] = mac_hi & 0xFF;
 231                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 232                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 233                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 234                 mac_addr[4] = mac_lo & 0xFF;
 235                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 236
 237                 if (is_valid_ether_addr(mac_addr))
 238                         eth_setenv_enetaddr("ethaddr", mac_addr);
 239                 else
 240                         printf("Unable to read MAC address. Set <ethaddr>\n");
 241         }
 242
 243         return cpsw_register(&cpsw_data);
 244 }