board/ti/ti816x/evm.c

   1 /*
   2  * evm.c
   3  *
   4  * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
   5  * Antoine Tenart, <atenart@adeneo-embedded.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <spl.h>
  12 #include <asm/cache.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/cpu.h>
  16 #include <asm/arch/ddr_defs.h>
  17 #include <asm/arch/hardware.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/arch/mmc_host_def.h>
  20 #include <asm/arch/mem.h>
  21 #include <asm/arch/mux.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 int board_init(void)
  26 {
  27         gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
  28         return 0;
  29 }
  30
  31 #ifdef CONFIG_SPL_BUILD
  32
  33 static struct module_pin_mux mmc_pin_mux[] = {
  34         { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
  35         { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
  36         { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  37         { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  38         { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  39         { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  40         { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  41         { -1 },
  42 };
  43
  44 const struct dmm_lisa_map_regs evm_lisa_map_regs = {
  45         .dmm_lisa_map_0 = 0x00000000,
  46         .dmm_lisa_map_1 = 0x00000000,
  47         .dmm_lisa_map_2 = 0x80640300,
  48         .dmm_lisa_map_3 = 0xC0640320,
  49 };
  50
  51 /*
  52  * DDR2 related definitions
  53  */
  54 #ifdef CONFIG_TI816X_EVM_DDR2
  55 static struct ddr_data ddr2_data = {
  56         .datardsratio0          = ((0x40<<10) | (0x40<<0)),
  57         .datawdsratio0          = ((0x4A<<10) | (0x4A<<0)),
  58         .datawiratio0           = ((0x0<<10) | (0x0<<0)),
  59         .datagiratio0           = ((0x0<<10) | (0x0<<0)),
  60         .datafwsratio0          = ((0x13A<<10) | (0x13A<<0)),
  61         .datawrsratio0          = ((0x8A<<10) | (0x8A<<0)),
  62         .datauserank0delay      = 0x1,
  63         .datadldiff0            = 0x0, /* depend on cpu rev, set later */
  64 };
  65
  66 static struct cmd_control ddr2_ctrl = {
  67         .cmd0csratio    = 0x80,
  68         .cmd0dldiff     = 0x04, /* reset value is 0x4 */
  69         .cmd0iclkout    = 0x00,
  70
  71         .cmd1csratio    = 0x80,
  72         .cmd1dldiff     = 0x04, /* reset value is 0x4 */
  73         .cmd1iclkout    = 0x00,
  74
  75         .cmd2csratio    = 0x80,
  76         .cmd2dldiff     = 0x04, /* reset value is 0x4 */
  77         .cmd2iclkout    = 0x00,
  78
  79 };
  80
  81 static struct emif_regs ddr2_emif0_regs = {
  82         .sdram_config           = 0x43801A3A,
  83         .ref_ctrl               = 0x10000C30,
  84         .sdram_tim1             = 0x0AAB15E2,
  85         .sdram_tim2             = 0x423631D2,
  86         .sdram_tim3             = 0x0080032F,
  87         .emif_ddr_phy_ctlr_1    = 0x0, /* depend on cpu rev, set later */
  88 };
  89
  90 static struct emif_regs ddr2_emif1_regs = {
  91         .sdram_config           = 0x43801A3A,
  92         .ref_ctrl               = 0x10000C30,
  93         .sdram_tim1             = 0x0AAB15E2,
  94         .sdram_tim2             = 0x423631D2,
  95         .sdram_tim3             = 0x0080032F,
  96         .emif_ddr_phy_ctlr_1    = 0x0, /* depend on cpu rev, set later */
  97 };
  98 #endif
  99
 100 /*
 101  * DDR3 related definitions
 102  */
 103
 104 #if defined(CONFIG_TI816X_DDR_PLL_400)
 105 #define RD_DQS          0x03B
 106 #define WR_DQS          0x0A6
 107 #define RD_DQS_GATE     0x12A
 108 #define EMIF_SDCFG      0x62A41032
 109 #define EMIF_SDREF      0x10000C30
 110 #define EMIF_TIM1       0x0CCCE524
 111 #define EMIF_TIM2       0x30308023
 112 #define EMIF_TIM3       0x009F82CF
 113 #define EMIF_PHYCFG     0x0000010B
 114 #elif defined(CONFIG_TI816X_DDR_PLL_531)
 115 #define RD_DQS          0x039
 116 #define WR_DQS          0x0B4
 117 #define RD_DQS_GATE     0x13D
 118 #define EMIF_SDCFG      0x62A51832
 119 #define EMIF_SDREF      0x1000102E
 120 #define EMIF_TIM1       0x0EF136AC
 121 #define EMIF_TIM2       0x30408063
 122 #define EMIF_TIM3       0x009F83AF
 123 #define EMIF_PHYCFG     0x0000010C
 124 #elif defined(CONFIG_TI816X_DDR_PLL_675)
 125 #define RD_DQS          0x039
 126 #define WR_DQS          0x091
 127 #define RD_DQS_GATE     0x196
 128 #define EMIF_SDCFG      0x62A63032
 129 #define EMIF_SDREF      0x10001491
 130 #define EMIF_TIM1       0x13358875
 131 #define EMIF_TIM2       0x5051806C
 132 #define EMIF_TIM3       0x009F84AF
 133 #define EMIF_PHYCFG     0x0000010F
 134 #elif defined(CONFIG_TI816X_DDR_PLL_796)
 135 #define RD_DQS          0x035
 136 #define WR_DQS          0x093
 137 #define RD_DQS_GATE     0x1B3
 138 #define EMIF_SDCFG      0x62A73832
 139 #define EMIF_SDREF      0x10001841
 140 #define EMIF_TIM1       0x1779C9FE
 141 #define EMIF_TIM2       0x50608074
 142 #define EMIF_TIM3       0x009F857F
 143 #define EMIF_PHYCFG     0x00000110
 144 #endif
 145
 146 static struct ddr_data ddr3_data = {
 147         .datardsratio0          = ((RD_DQS<<10) | (RD_DQS<<0)),
 148         .datawdsratio0          = ((WR_DQS<<10) | (WR_DQS<<0)),
 149         .datawiratio0           = ((0x20<<10) | 0x20<<0),
 150         .datagiratio0           = ((0x20<<10) | 0x20<<0),
 151         .datafwsratio0          = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
 152         .datawrsratio0          = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
 153         .datauserank0delay      = 0x1,
 154         .datadldiff0            = 0x0, /* depend on cpu rev, set later */
 155 };
 156
 157 static const struct cmd_control ddr3_ctrl = {
 158         .cmd0csratio    = 0x100,
 159         .cmd0dldiff     = 0x004, /* reset value is 0x4 */
 160         .cmd0iclkout    = 0x001,
 161
 162         .cmd1csratio    = 0x100,
 163         .cmd1dldiff     = 0x004, /* reset value is 0x4 */
 164         .cmd1iclkout    = 0x001,
 165
 166         .cmd2csratio    = 0x100,
 167         .cmd2dldiff     = 0x004, /* reset value is 0x4 */
 168         .cmd2iclkout    = 0x001,
 169 };
 170
 171 static const struct emif_regs ddr3_emif0_regs = {
 172         .sdram_config           = EMIF_SDCFG,
 173         .ref_ctrl               = EMIF_SDREF,
 174         .sdram_tim1             = EMIF_TIM1,
 175         .sdram_tim2             = EMIF_TIM2,
 176         .sdram_tim3             = EMIF_TIM3,
 177         .emif_ddr_phy_ctlr_1    = EMIF_PHYCFG,
 178 };
 179
 180 static const struct emif_regs ddr3_emif1_regs = {
 181         .sdram_config           = EMIF_SDCFG,
 182         .ref_ctrl               = EMIF_SDREF,
 183         .sdram_tim1             = EMIF_TIM1,
 184         .sdram_tim2             = EMIF_TIM2,
 185         .sdram_tim3             = EMIF_TIM3,
 186         .emif_ddr_phy_ctlr_1    = EMIF_PHYCFG,
 187 };
 188
 189 void set_uart_mux_conf(void) {}
 190
 191 void set_mux_conf_regs(void)
 192 {
 193         configure_module_pin_mux(mmc_pin_mux);
 194 }
 195
 196 void sdram_init(void)
 197 {
 198         config_dmm(&evm_lisa_map_regs);
 199
 200 #ifdef CONFIG_TI816X_EVM_DDR2
 201         ddr2_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
 202         ddr2_ctrl.cmd0dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
 203         ddr2_ctrl.cmd1dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
 204         ddr2_ctrl.cmd2dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
 205
 206         if (CONFIG_TI816X_USE_EMIF0) {
 207                 ddr2_emif0_regs.emif_ddr_phy_ctlr_1 =
 208                         (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
 209                 config_ddr(0, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs, 0);
 210         }
 211
 212         if (CONFIG_TI816X_USE_EMIF1) {
 213                 ddr2_emif1_regs.emif_ddr_phy_ctlr_1 =
 214                         (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
 215                 config_ddr(1, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs, 1);
 216         }
 217 #endif
 218
 219 #ifdef CONFIG_TI816X_EVM_DDR3
 220         ddr3_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
 221
 222         if (CONFIG_TI816X_USE_EMIF0)
 223                 config_ddr(0, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, 0);
 224
 225         if (CONFIG_TI816X_USE_EMIF1)
 226                 config_ddr(1, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs, 1);
 227 #endif
 228 }
 229 #endif /* CONFIG_SPL_BUILD */