board/ttcontrol/vision2/vision2.c

   1 /*
   2  * (C) Copyright 2010
   3  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
   4  *
   5  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <asm/io.h>
  28 #include <asm/arch/imx-regs.h>
  29 #include <asm/arch/mx5x_pins.h>
  30 #include <asm/arch/crm_regs.h>
  31 #include <asm/arch/clock.h>
  32 #include <asm/arch/iomux.h>
  33 #include <asm/gpio.h>
  34 #include <asm/arch/sys_proto.h>
  35 #include <i2c.h>
  36 #include <mmc.h>
  37 #include <power/pmic.h>
  38 #include <fsl_esdhc.h>
  39 #include <fsl_pmic.h>
  40 #include <mc13892.h>
  41 #include <linux/fb.h>
  42
  43 #include <ipu_pixfmt.h>
  44
  45 DECLARE_GLOBAL_DATA_PTR;
  46
  47 static struct fb_videomode const nec_nl6448bc26_09c = {
  48         "NEC_NL6448BC26-09C",
  49         60,     /* Refresh */
  50         640,    /* xres */
  51         480,    /* yres */
  52         37650,  /* pixclock = 26.56Mhz */
  53         48,     /* left margin */
  54         16,     /* right margin */
  55         31,     /* upper margin */
  56         12,     /* lower margin */
  57         96,     /* hsync-len */
  58         2,      /* vsync-len */
  59         0,      /* sync */
  60         FB_VMODE_NONINTERLACED, /* vmode */
  61         0,      /* flag */
  62 };
  63
  64 #ifdef CONFIG_HW_WATCHDOG
  65 #include <watchdog.h>
  66 void hw_watchdog_reset(void)
  67 {
  68         int val;
  69
  70         /* toggle watchdog trigger pin */
  71         val = gpio_get_value(66);
  72         val = val ? 0 : 1;
  73         gpio_set_value(66, val);
  74 }
  75 #endif
  76
  77 static void init_drive_strength(void)
  78 {
  79         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
  80         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
  81         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
  82         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
  83         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
  84         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
  85         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
  86         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
  87                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
  88         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
  89                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
  90         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
  91         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
  92         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
  93         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
  94         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
  95         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
  96         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
  97         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
  98         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
  99         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
 100         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
 101         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
 102         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
 103         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
 104         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
 105         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
 106
 107         /* Setting pad options */
 108         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
 109                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 110                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 111         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
 112                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 113                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 114         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
 115                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 116                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 117         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
 118                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 119                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 120         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
 121                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 122                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 123         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
 124                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 125                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 126         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
 127                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 128                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 129         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
 130                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 131                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 132         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
 133                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 134                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 135         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
 136                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 137                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 138         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
 139                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 140                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 141         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
 142                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 143                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 144         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
 145                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 146                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 147         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
 148                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 149                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 150 }
 151
 152 int dram_init(void)
 153 {
 154         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
 155                 PHYS_SDRAM_1_SIZE);
 156
 157         return 0;
 158 }
 159
 160 static void setup_weim(void)
 161 {
 162         struct weim  *pweim = (struct weim *)WEIM_BASE_ADDR;
 163
 164         pweim->cs0gcr1 = 0x004100b9;
 165         pweim->cs0gcr2 = 0x00000001;
 166         pweim->cs0rcr1 = 0x0a018000;
 167         pweim->cs0rcr2 = 0;
 168         pweim->cs0wcr1 = 0x0704a240;
 169 }
 170
 171 static void setup_uart(void)
 172 {
 173         unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
 174                          PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST;
 175         /* console RX on Pin EIM_D25 */
 176         mxc_request_iomux(MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT3);
 177         mxc_iomux_set_pad(MX51_PIN_EIM_D25, pad);
 178         /* console TX on Pin EIM_D26 */
 179         mxc_request_iomux(MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT3);
 180         mxc_iomux_set_pad(MX51_PIN_EIM_D26, pad);
 181 }
 182
 183 #ifdef CONFIG_MXC_SPI
 184 void spi_io_init(void)
 185 {
 186         /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
 187         mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
 188         mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
 189                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 190
 191         /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
 192         mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
 193         mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
 194                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 195
 196         /* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */
 197         mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
 198         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0,
 199                 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
 200                 PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 201
 202         /*
 203          * SS1 will be used as GPIO because of uninterrupted
 204          * long SPI transmissions (GPIO4_25)
 205          */
 206         mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
 207         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1,
 208                 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
 209                 PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 210
 211         /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
 212         mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT7);
 213         mxc_iomux_set_pad(MX51_PIN_DI1_PIN11,
 214                 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
 215                 PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 216
 217         /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
 218         mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
 219         mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
 220                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 221 }
 222
 223 static void reset_peripherals(int reset)
 224 {
 225         if (reset) {
 226
 227                 /* reset_n is on NANDF_D15 */
 228                 gpio_direction_output(89, 0);
 229
 230 #ifdef CONFIG_VISION2_HW_1_0
 231                 /*
 232                  * set FEC Configuration lines
 233                  * set levels of FEC config lines
 234                  */
 235                 gpio_direction_output(75, 0);
 236                 gpio_direction_output(74, 1);
 237                 gpio_direction_output(95, 1);
 238
 239                 /* set direction of FEC config lines */
 240                 gpio_direction_output(59, 0);
 241                 gpio_direction_output(60, 0);
 242                 gpio_direction_output(61, 0);
 243                 gpio_direction_output(55, 1);
 244
 245                 /* FEC_RXD1 - sel GPIO (2-23) for configuration -> 1 */
 246                 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
 247                 /* FEC_RXD2 - sel GPIO (2-27) for configuration -> 0 */
 248                 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT1);
 249                 /* FEC_RXD3 - sel GPIO (2-28) for configuration -> 0 */
 250                 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT1);
 251                 /* FEC_RXER - sel GPIO (2-29) for configuration -> 0 */
 252                 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT1);
 253                 /* FEC_COL  - sel GPIO (3-10) for configuration -> 1 */
 254                 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT3);
 255                 /* FEC_RCLK - sel GPIO (3-11) for configuration -> 0 */
 256                 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT3);
 257                 /* FEC_RXD0 - sel GPIO (3-31) for configuration -> 1 */
 258                 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT3);
 259 #endif
 260
 261                 /*
 262                  * activate reset_n pin
 263                  * Select mux mode: ALT3 mux port: NAND D15
 264                  */
 265                 mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT3);
 266                 mxc_iomux_set_pad(MX51_PIN_NANDF_D15,
 267                         PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DRV_MAX);
 268         } else {
 269                 /* set FEC Control lines */
 270                 gpio_direction_input(89);
 271                 udelay(500);
 272
 273 #ifdef CONFIG_VISION2_HW_1_0
 274                 /* FEC RDATA[3] */
 275                 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
 276                 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
 277
 278                 /* FEC RDATA[2] */
 279                 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
 280                 mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
 281
 282                 /* FEC RDATA[1] */
 283                 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
 284                 mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
 285
 286                 /* FEC RDATA[0] */
 287                 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
 288                 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
 289
 290                 /* FEC RX_CLK */
 291                 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
 292                 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
 293
 294                 /* FEC RX_ER */
 295                 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
 296                 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
 297
 298                 /* FEC COL */
 299                 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
 300                 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
 301 #endif
 302         }
 303 }
 304
 305 static void power_init_mx51(void)
 306 {
 307         unsigned int val;
 308         struct pmic *p;
 309         int ret;
 310
 311         ret = pmic_init(I2C_PMIC);
 312         if (ret)
 313                 return;
 314
 315         p = pmic_get("FSL_PMIC");
 316         if (!p)
 317                 return;
 318
 319         /* Write needed to Power Gate 2 register */
 320         pmic_reg_read(p, REG_POWER_MISC, &val);
 321
 322         /* enable VCAM with 2.775V to enable read from PMIC */
 323         val = VCAMCONFIG | VCAMEN;
 324         pmic_reg_write(p, REG_MODE_1, val);
 325
 326         /*
 327          * Set switchers in Auto in NORMAL mode & STANDBY mode
 328          * Setup the switcher mode for SW1 & SW2
 329          */
 330         pmic_reg_read(p, REG_SW_4, &val);
 331         val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
 332                 (SWMODE_MASK << SWMODE2_SHIFT)));
 333         val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
 334                 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
 335         pmic_reg_write(p, REG_SW_4, val);
 336
 337         /* Setup the switcher mode for SW3 & SW4 */
 338         pmic_reg_read(p, REG_SW_5, &val);
 339         val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
 340                 (SWMODE_MASK << SWMODE3_SHIFT));
 341         val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
 342                 (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
 343         pmic_reg_write(p, REG_SW_5, val);
 344
 345
 346         /* Set VGEN3 to 1.8V, VCAM to 3.0V */
 347         pmic_reg_read(p, REG_SETTING_0, &val);
 348         val &= ~(VCAM_MASK | VGEN3_MASK);
 349         val |= VCAM_3_0;
 350         pmic_reg_write(p, REG_SETTING_0, val);
 351
 352         /* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */
 353         pmic_reg_read(p, REG_SETTING_1, &val);
 354         val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
 355         val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8;
 356         pmic_reg_write(p, REG_SETTING_1, val);
 357
 358         /* Configure VGEN3 and VCAM regulators to use external PNP */
 359         val = VGEN3CONFIG | VCAMCONFIG;
 360         pmic_reg_write(p, REG_MODE_1, val);
 361         udelay(200);
 362
 363         /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
 364         val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
 365                 VVIDEOEN | VAUDIOEN  | VSDEN;
 366         pmic_reg_write(p, REG_MODE_1, val);
 367
 368         pmic_reg_read(p, REG_POWER_CTL2, &val);
 369         val |= WDIRESET;
 370         pmic_reg_write(p, REG_POWER_CTL2, val);
 371
 372         udelay(2500);
 373
 374 }
 375 #endif
 376
 377 static void setup_gpios(void)
 378 {
 379         unsigned int i;
 380
 381         /* CAM_SUP_DISn, GPIO1_7 */
 382         mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
 383         mxc_iomux_set_pad(MX51_PIN_GPIO1_7, 0x82);
 384
 385         /* DAB Display EN, GPIO3_1 */
 386         mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4);
 387         mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, 0x82);
 388
 389         /* WDOG_TRIGGER, GPIO3_2 */
 390         mxc_request_iomux(MX51_PIN_DI1_PIN13, IOMUX_CONFIG_ALT4);
 391         mxc_iomux_set_pad(MX51_PIN_DI1_PIN13, 0x82);
 392
 393         /* Now we need to trigger the watchdog */
 394         WATCHDOG_RESET();
 395
 396         /* Display2 TxEN, GPIO3_3 */
 397         mxc_request_iomux(MX51_PIN_DI1_D0_CS, IOMUX_CONFIG_ALT4);
 398         mxc_iomux_set_pad(MX51_PIN_DI1_D0_CS, 0x82);
 399
 400         /* DAB Light EN, GPIO3_4 */
 401         mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
 402         mxc_iomux_set_pad(MX51_PIN_DI1_D1_CS, 0x82);
 403
 404         /* AUDIO_MUTE, GPIO3_5 */
 405         mxc_request_iomux(MX51_PIN_DISPB2_SER_DIN, IOMUX_CONFIG_ALT4);
 406         mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIN, 0x82);
 407
 408         /* SPARE_OUT, GPIO3_6 */
 409         mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_ALT4);
 410         mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIO, 0x82);
 411
 412         /* BEEPER_EN, GPIO3_26 */
 413         mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3);
 414         mxc_iomux_set_pad(MX51_PIN_NANDF_D14, 0x82);
 415
 416         /* POWER_OFF, GPIO3_27 */
 417         mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT3);
 418         mxc_iomux_set_pad(MX51_PIN_NANDF_D13, 0x82);
 419
 420         /* FRAM_WE, GPIO3_30 */
 421         mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT3);
 422         mxc_iomux_set_pad(MX51_PIN_NANDF_D10, 0x82);
 423
 424         /* EXPANSION_EN, GPIO4_26 */
 425         mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3);
 426         mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x82);
 427
 428         /* PWM Output GPIO1_2 */
 429         mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT1);
 430
 431         /*
 432          * Set GPIO1_4 to high and output; it is used to reset
 433          * the system on reboot
 434          */
 435         gpio_direction_output(4, 1);
 436
 437         gpio_direction_output(7, 0);
 438         for (i = 65; i < 71; i++)
 439                 gpio_direction_output(i, 0);
 440
 441         gpio_direction_output(94, 0);
 442
 443         /* Set POWER_OFF high */
 444         gpio_direction_output(91, 1);
 445
 446         gpio_direction_output(90, 0);
 447
 448         gpio_direction_output(122, 0);
 449
 450         gpio_direction_output(121, 1);
 451
 452         WATCHDOG_RESET();
 453 }
 454
 455 static void setup_fec(void)
 456 {
 457         /*FEC_MDIO*/
 458         mxc_request_iomux(MX51_PIN_EIM_EB2, IOMUX_CONFIG_ALT3);
 459         mxc_iomux_set_pad(MX51_PIN_EIM_EB2, 0x1FD);
 460
 461         /*FEC_MDC*/
 462         mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
 463         mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
 464
 465         /* FEC RDATA[3] */
 466         mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
 467         mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
 468
 469         /* FEC RDATA[2] */
 470         mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
 471         mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
 472
 473         /* FEC RDATA[1] */
 474         mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
 475         mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
 476
 477         /* FEC RDATA[0] */
 478         mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
 479         mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
 480
 481         /* FEC TDATA[3] */
 482         mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
 483         mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
 484
 485         /* FEC TDATA[2] */
 486         mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
 487         mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
 488
 489         /* FEC TDATA[1] */
 490         mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
 491         mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
 492
 493         /* FEC TDATA[0] */
 494         mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
 495         mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
 496
 497         /* FEC TX_EN */
 498         mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
 499         mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
 500
 501         /* FEC TX_ER */
 502         mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
 503         mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
 504
 505         /* FEC TX_CLK */
 506         mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
 507         mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
 508
 509         /* FEC TX_COL */
 510         mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
 511         mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
 512
 513         /* FEC RX_CLK */
 514         mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
 515         mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
 516
 517         /* FEC RX_CRS */
 518         mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
 519         mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
 520
 521         /* FEC RX_ER */
 522         mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
 523         mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
 524
 525         /* FEC RX_DV */
 526         mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
 527         mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
 528 }
 529
 530 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 531         {MMC_SDHC1_BASE_ADDR},
 532 };
 533
 534 int get_mmc_getcd(u8 *cd, struct mmc *mmc)
 535 {
 536         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 537
 538         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 539                 *cd = gpio_get_value(0);
 540         else
 541                 *cd = 0;
 542
 543         return 0;
 544 }
 545
 546 #ifdef CONFIG_FSL_ESDHC
 547 int board_mmc_init(bd_t *bis)
 548 {
 549         mxc_request_iomux(MX51_PIN_SD1_CMD,
 550                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 551         mxc_request_iomux(MX51_PIN_SD1_CLK,
 552                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 553         mxc_request_iomux(MX51_PIN_SD1_DATA0,
 554                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 555         mxc_request_iomux(MX51_PIN_SD1_DATA1,
 556                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 557         mxc_request_iomux(MX51_PIN_SD1_DATA2,
 558                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 559         mxc_request_iomux(MX51_PIN_SD1_DATA3,
 560                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 561         mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
 562                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 563                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 564                 PAD_CTL_PUE_PULL |
 565                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 566         mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
 567                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 568                 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
 569                 PAD_CTL_PUE_PULL |
 570                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 571         mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
 572                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 573                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 574                 PAD_CTL_PUE_PULL |
 575                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 576         mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
 577                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 578                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 579                 PAD_CTL_PUE_PULL |
 580                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 581         mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
 582                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 583                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 584                 PAD_CTL_PUE_PULL |
 585                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 586         mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
 587                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 588                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
 589                 PAD_CTL_PUE_PULL |
 590                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 591         mxc_request_iomux(MX51_PIN_GPIO1_0,
 592                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 593         mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
 594                 PAD_CTL_HYS_ENABLE);
 595         mxc_request_iomux(MX51_PIN_GPIO1_1,
 596                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 597         mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
 598                 PAD_CTL_HYS_ENABLE);
 599
 600         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 601         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 602 }
 603 #endif
 604
 605 void lcd_enable(void)
 606 {
 607         int ret;
 608
 609         mxc_request_iomux(MX51_PIN_DI1_PIN2, IOMUX_CONFIG_ALT0);
 610         mxc_request_iomux(MX51_PIN_DI1_PIN3, IOMUX_CONFIG_ALT0);
 611
 612         gpio_set_value(2, 1);
 613         mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0);
 614
 615         ret = ipuv3_fb_init(&nec_nl6448bc26_09c, 0, IPU_PIX_FMT_RGB666);
 616         if (ret)
 617                 puts("LCD cannot be configured\n");
 618 }
 619
 620 int board_early_init_f(void)
 621 {
 622
 623
 624         init_drive_strength();
 625
 626         /* Setup debug led */
 627         gpio_direction_output(6, 0);
 628         mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
 629         mxc_iomux_set_pad(MX51_PIN_GPIO1_6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 630
 631         /* wait a little while to give the pll time to settle */
 632         sdelay(100000);
 633
 634         setup_weim();
 635         setup_uart();
 636         setup_fec();
 637         setup_gpios();
 638
 639         spi_io_init();
 640
 641         return 0;
 642 }
 643
 644 static void backlight(int on)
 645 {
 646         if (on) {
 647                 gpio_set_value(65, 1);
 648                 udelay(10000);
 649                 gpio_set_value(68, 1);
 650         } else {
 651                 gpio_set_value(65, 0);
 652                 gpio_set_value(68, 0);
 653         }
 654 }
 655
 656 int board_init(void)
 657 {
 658         /* address of boot parameters */
 659         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 660
 661         lcd_enable();
 662
 663         backlight(1);
 664
 665         return 0;
 666 }
 667
 668 int board_late_init(void)
 669 {
 670         power_init_mx51();
 671
 672         reset_peripherals(1);
 673         udelay(2000);
 674         reset_peripherals(0);
 675         udelay(2000);
 676
 677         /* Early revisions require a second reset */
 678 #ifdef CONFIG_VISION2_HW_1_0
 679         reset_peripherals(1);
 680         udelay(2000);
 681         reset_peripherals(0);
 682         udelay(2000);
 683 #endif
 684
 685         return 0;
 686 }
 687
 688 /*
 689  * Do not overwrite the console
 690  * Use always serial for U-Boot console
 691  */
 692 int overwrite_console(void)
 693 {
 694         return 1;
 695 }
 696
 697 int checkboard(void)
 698 {
 699         puts("Board: TTControl Vision II CPU V\n");
 700
 701         return 0;
 702 }
 703
 704 int do_vision_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 705 {
 706         int on;
 707
 708         if (argc < 2)
 709                 return cmd_usage(cmdtp);
 710
 711         on = (strcmp(argv[1], "on") == 0);
 712         backlight(on);
 713
 714         return 0;
 715 }
 716
 717 U_BOOT_CMD(
 718         lcdbl, CONFIG_SYS_MAXARGS, 1, do_vision_lcd,
 719         "Vision2 Backlight",
 720         "lcdbl [on|off]\n"
 721 );