board/ttcontrol/vision2/vision2.c

   1 /*
   2  * (C) Copyright 2010
   3  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
   4  *
   5  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <asm/io.h>
  28 #include <asm/arch/imx-regs.h>
  29 #include <asm/arch/mx5x_pins.h>
  30 #include <asm/arch/crm_regs.h>
  31 #include <asm/arch/iomux.h>
  32 #include <asm/gpio.h>
  33 #include <asm/arch/sys_proto.h>
  34 #include <asm/errno.h>
  35 #include <i2c.h>
  36 #include <mmc.h>
  37 #include <fsl_esdhc.h>
  38 #include <fsl_pmic.h>
  39 #include <mc13892.h>
  40 #include <linux/fb.h>
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 static u32 system_rev;
  45
  46 extern int mx51_fb_init(struct fb_videomode *mode);
  47
  48 static struct fb_videomode nec_nl6448bc26_09c = {
  49         "NEC_NL6448BC26-09C",
  50         60,     /* Refresh */
  51         640,    /* xres */
  52         480,    /* yres */
  53         37650,  /* pixclock = 26.56Mhz */
  54         48,     /* left margin */
  55         16,     /* right margin */
  56         31,     /* upper margin */
  57         12,     /* lower margin */
  58         96,     /* hsync-len */
  59         2,      /* vsync-len */
  60         0,      /* sync */
  61         FB_VMODE_NONINTERLACED, /* vmode */
  62         0,      /* flag */
  63 };
  64
  65 #ifdef CONFIG_HW_WATCHDOG
  66 #include <watchdog.h>
  67 void hw_watchdog_reset(void)
  68 {
  69         int val;
  70
  71         /* toggle watchdog trigger pin */
  72         val = gpio_get_value(66);
  73         val = val ? 0 : 1;
  74         gpio_set_value(66, val);
  75 }
  76 #endif
  77
  78 static void init_drive_strength(void)
  79 {
  80         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
  81         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
  82         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
  83         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
  84         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
  85         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
  86         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
  87         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
  88                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
  89         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
  90                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
  91         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
  92         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
  93         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
  94         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
  95         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
  96         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
  97         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
  98         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
  99         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
 100         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
 101         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
 102         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
 103         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
 104         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
 105         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
 106         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
 107
 108         /* Setting pad options */
 109         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
 110                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 111                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 112         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
 113                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 114                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 115         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
 116                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 117                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 118         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
 119                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 120                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 121         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
 122                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 123                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 124         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
 125                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 126                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 127         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
 128                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 129                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 130         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
 131                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 132                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 133         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
 134                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 135                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 136         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
 137                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 138                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 139         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
 140                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 141                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 142         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
 143                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 144                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 145         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
 146                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 147                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 148         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
 149                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 150                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 151 }
 152
 153 u32 get_board_rev(void)
 154 {
 155         system_rev = get_cpu_rev();
 156
 157         return system_rev;
 158 }
 159
 160 int dram_init(void)
 161 {
 162         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
 163                 PHYS_SDRAM_1_SIZE);
 164
 165         return 0;
 166 }
 167
 168 static void setup_weim(void)
 169 {
 170         struct weim  *pweim = (struct weim *)WEIM_BASE_ADDR;
 171
 172         pweim->cs0gcr1 = 0x004100b9;
 173         pweim->cs0gcr2 = 0x00000001;
 174         pweim->cs0rcr1 = 0x0a018000;
 175         pweim->cs0rcr2 = 0;
 176         pweim->cs0wcr1 = 0x0704a240;
 177 }
 178
 179 static void setup_uart(void)
 180 {
 181         unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
 182                          PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST;
 183         /* console RX on Pin EIM_D25 */
 184         mxc_request_iomux(MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT3);
 185         mxc_iomux_set_pad(MX51_PIN_EIM_D25, pad);
 186         /* console TX on Pin EIM_D26 */
 187         mxc_request_iomux(MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT3);
 188         mxc_iomux_set_pad(MX51_PIN_EIM_D26, pad);
 189 }
 190
 191 #ifdef CONFIG_MXC_SPI
 192 void spi_io_init(void)
 193 {
 194         /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
 195         mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
 196         mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
 197                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 198
 199         /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
 200         mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
 201         mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
 202                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 203
 204         /* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */
 205         mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
 206         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0,
 207                 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
 208                 PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 209
 210         /*
 211          * SS1 will be used as GPIO because of uninterrupted
 212          * long SPI transmissions (GPIO4_25)
 213          */
 214         mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
 215         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1,
 216                 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
 217                 PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 218
 219         /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
 220         mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT7);
 221         mxc_iomux_set_pad(MX51_PIN_DI1_PIN11,
 222                 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
 223                 PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 224
 225         /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
 226         mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
 227         mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
 228                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 229 }
 230
 231 static void reset_peripherals(int reset)
 232 {
 233         if (reset) {
 234
 235                 /* reset_n is on NANDF_D15 */
 236                 gpio_direction_output(89, 0);
 237
 238 #ifdef CONFIG_VISION2_HW_1_0
 239                 /*
 240                  * set FEC Configuration lines
 241                  * set levels of FEC config lines
 242                  */
 243                 gpio_direction_output(75, 0);
 244                 gpio_direction_output(74, 1);
 245                 gpio_direction_output(95, 1);
 246
 247                 /* set direction of FEC config lines */
 248                 gpio_direction_output(59, 0);
 249                 gpio_direction_output(60, 0);
 250                 gpio_direction_output(61, 0);
 251                 gpio_direction_output(55, 1);
 252
 253                 /* FEC_RXD1 - sel GPIO (2-23) for configuration -> 1 */
 254                 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
 255                 /* FEC_RXD2 - sel GPIO (2-27) for configuration -> 0 */
 256                 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT1);
 257                 /* FEC_RXD3 - sel GPIO (2-28) for configuration -> 0 */
 258                 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT1);
 259                 /* FEC_RXER - sel GPIO (2-29) for configuration -> 0 */
 260                 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT1);
 261                 /* FEC_COL  - sel GPIO (3-10) for configuration -> 1 */
 262                 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT3);
 263                 /* FEC_RCLK - sel GPIO (3-11) for configuration -> 0 */
 264                 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT3);
 265                 /* FEC_RXD0 - sel GPIO (3-31) for configuration -> 1 */
 266                 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT3);
 267 #endif
 268
 269                 /*
 270                  * activate reset_n pin
 271                  * Select mux mode: ALT3 mux port: NAND D15
 272                  */
 273                 mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT3);
 274                 mxc_iomux_set_pad(MX51_PIN_NANDF_D15,
 275                         PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DRV_MAX);
 276         } else {
 277                 /* set FEC Control lines */
 278                 gpio_direction_input(89);
 279                 udelay(500);
 280
 281 #ifdef CONFIG_VISION2_HW_1_0
 282                 /* FEC RDATA[3] */
 283                 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
 284                 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
 285
 286                 /* FEC RDATA[2] */
 287                 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
 288                 mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
 289
 290                 /* FEC RDATA[1] */
 291                 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
 292                 mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
 293
 294                 /* FEC RDATA[0] */
 295                 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
 296                 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
 297
 298                 /* FEC RX_CLK */
 299                 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
 300                 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
 301
 302                 /* FEC RX_ER */
 303                 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
 304                 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
 305
 306                 /* FEC COL */
 307                 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
 308                 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
 309 #endif
 310         }
 311 }
 312
 313 static void power_init_mx51(void)
 314 {
 315         unsigned int val;
 316
 317         /* Write needed to Power Gate 2 register */
 318         val = pmic_reg_read(REG_POWER_MISC);
 319
 320         /* enable VCAM with 2.775V to enable read from PMIC */
 321         val = VCAMCONFIG | VCAMEN;
 322         pmic_reg_write(REG_MODE_1, val);
 323
 324         /*
 325          * Set switchers in Auto in NORMAL mode & STANDBY mode
 326          * Setup the switcher mode for SW1 & SW2
 327          */
 328         val = pmic_reg_read(REG_SW_4);
 329         val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
 330                 (SWMODE_MASK << SWMODE2_SHIFT)));
 331         val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
 332                 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
 333         pmic_reg_write(REG_SW_4, val);
 334
 335         /* Setup the switcher mode for SW3 & SW4 */
 336         val = pmic_reg_read(REG_SW_5);
 337         val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
 338                 (SWMODE_MASK << SWMODE3_SHIFT));
 339         val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
 340                 (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
 341         pmic_reg_write(REG_SW_5, val);
 342
 343
 344         /* Set VGEN3 to 1.8V, VCAM to 3.0V */
 345         val = pmic_reg_read(REG_SETTING_0);
 346         val &= ~(VCAM_MASK | VGEN3_MASK);
 347         val |= VCAM_3_0;
 348         pmic_reg_write(REG_SETTING_0, val);
 349
 350         /* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */
 351         val = pmic_reg_read(REG_SETTING_1);
 352         val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
 353         val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8;
 354         pmic_reg_write(REG_SETTING_1, val);
 355
 356         /* Configure VGEN3 and VCAM regulators to use external PNP */
 357         val = VGEN3CONFIG | VCAMCONFIG;
 358         pmic_reg_write(REG_MODE_1, val);
 359         udelay(200);
 360
 361         /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
 362         val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
 363                 VVIDEOEN | VAUDIOEN  | VSDEN;
 364         pmic_reg_write(REG_MODE_1, val);
 365
 366         val = pmic_reg_read(REG_POWER_CTL2);
 367         val |= WDIRESET;
 368         pmic_reg_write(REG_POWER_CTL2, val);
 369
 370         udelay(2500);
 371
 372 }
 373 #endif
 374
 375 static void setup_gpios(void)
 376 {
 377         unsigned int i;
 378
 379         /* CAM_SUP_DISn, GPIO1_7 */
 380         mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
 381         mxc_iomux_set_pad(MX51_PIN_GPIO1_7, 0x82);
 382
 383         /* DAB Display EN, GPIO3_1 */
 384         mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4);
 385         mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, 0x82);
 386
 387         /* WDOG_TRIGGER, GPIO3_2 */
 388         mxc_request_iomux(MX51_PIN_DI1_PIN13, IOMUX_CONFIG_ALT4);
 389         mxc_iomux_set_pad(MX51_PIN_DI1_PIN13, 0x82);
 390
 391         /* Now we need to trigger the watchdog */
 392         WATCHDOG_RESET();
 393
 394         /* Display2 TxEN, GPIO3_3 */
 395         mxc_request_iomux(MX51_PIN_DI1_D0_CS, IOMUX_CONFIG_ALT4);
 396         mxc_iomux_set_pad(MX51_PIN_DI1_D0_CS, 0x82);
 397
 398         /* DAB Light EN, GPIO3_4 */
 399         mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
 400         mxc_iomux_set_pad(MX51_PIN_DI1_D1_CS, 0x82);
 401
 402         /* AUDIO_MUTE, GPIO3_5 */
 403         mxc_request_iomux(MX51_PIN_DISPB2_SER_DIN, IOMUX_CONFIG_ALT4);
 404         mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIN, 0x82);
 405
 406         /* SPARE_OUT, GPIO3_6 */
 407         mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_ALT4);
 408         mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIO, 0x82);
 409
 410         /* BEEPER_EN, GPIO3_26 */
 411         mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3);
 412         mxc_iomux_set_pad(MX51_PIN_NANDF_D14, 0x82);
 413
 414         /* POWER_OFF, GPIO3_27 */
 415         mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT3);
 416         mxc_iomux_set_pad(MX51_PIN_NANDF_D13, 0x82);
 417
 418         /* FRAM_WE, GPIO3_30 */
 419         mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT3);
 420         mxc_iomux_set_pad(MX51_PIN_NANDF_D10, 0x82);
 421
 422         /* EXPANSION_EN, GPIO4_26 */
 423         mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3);
 424         mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x82);
 425
 426         /* PWM Output GPIO1_2 */
 427         mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT1);
 428
 429         /*
 430          * Set GPIO1_4 to high and output; it is used to reset
 431          * the system on reboot
 432          */
 433         gpio_direction_output(4, 1);
 434
 435         gpio_direction_output(7, 0);
 436         for (i = 65; i < 71; i++) {
 437                 gpio_direction_output(i, 0);
 438         }
 439
 440         gpio_direction_output(94, 0);
 441
 442         /* Set POWER_OFF high */
 443         gpio_direction_output(91, 1);
 444
 445         gpio_direction_output(90, 0);
 446
 447         gpio_direction_output(122, 0);
 448
 449         gpio_direction_output(121, 1);
 450
 451         WATCHDOG_RESET();
 452 }
 453
 454 static void setup_fec(void)
 455 {
 456         /*FEC_MDIO*/
 457         mxc_request_iomux(MX51_PIN_EIM_EB2, IOMUX_CONFIG_ALT3);
 458         mxc_iomux_set_pad(MX51_PIN_EIM_EB2, 0x1FD);
 459
 460         /*FEC_MDC*/
 461         mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
 462         mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
 463
 464         /* FEC RDATA[3] */
 465         mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
 466         mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
 467
 468         /* FEC RDATA[2] */
 469         mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
 470         mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
 471
 472         /* FEC RDATA[1] */
 473         mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
 474         mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
 475
 476         /* FEC RDATA[0] */
 477         mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
 478         mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
 479
 480         /* FEC TDATA[3] */
 481         mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
 482         mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
 483
 484         /* FEC TDATA[2] */
 485         mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
 486         mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
 487
 488         /* FEC TDATA[1] */
 489         mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
 490         mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
 491
 492         /* FEC TDATA[0] */
 493         mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
 494         mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
 495
 496         /* FEC TX_EN */
 497         mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
 498         mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
 499
 500         /* FEC TX_ER */
 501         mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
 502         mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
 503
 504         /* FEC TX_CLK */
 505         mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
 506         mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
 507
 508         /* FEC TX_COL */
 509         mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
 510         mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
 511
 512         /* FEC RX_CLK */
 513         mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
 514         mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
 515
 516         /* FEC RX_CRS */
 517         mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
 518         mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
 519
 520         /* FEC RX_ER */
 521         mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
 522         mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
 523
 524         /* FEC RX_DV */
 525         mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
 526         mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
 527 }
 528
 529 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 530         {MMC_SDHC1_BASE_ADDR, 1},
 531 };
 532
 533 int get_mmc_getcd(u8 *cd, struct mmc *mmc)
 534 {
 535         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 536
 537         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 538                 *cd = gpio_get_value(0);
 539         else
 540                 *cd = 0;
 541
 542         return 0;
 543 }
 544
 545 #ifdef CONFIG_FSL_ESDHC
 546 int board_mmc_init(bd_t *bis)
 547 {
 548         mxc_request_iomux(MX51_PIN_SD1_CMD,
 549                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 550         mxc_request_iomux(MX51_PIN_SD1_CLK,
 551                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 552         mxc_request_iomux(MX51_PIN_SD1_DATA0,
 553                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 554         mxc_request_iomux(MX51_PIN_SD1_DATA1,
 555                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 556         mxc_request_iomux(MX51_PIN_SD1_DATA2,
 557                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 558         mxc_request_iomux(MX51_PIN_SD1_DATA3,
 559                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 560         mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
 561                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 562                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 563                 PAD_CTL_PUE_PULL |
 564                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 565         mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
 566                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 567                 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
 568                 PAD_CTL_PUE_PULL |
 569                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 570         mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
 571                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 572                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 573                 PAD_CTL_PUE_PULL |
 574                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 575         mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
 576                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 577                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 578                 PAD_CTL_PUE_PULL |
 579                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 580         mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
 581                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 582                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 583                 PAD_CTL_PUE_PULL |
 584                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 585         mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
 586                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 587                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
 588                 PAD_CTL_PUE_PULL |
 589                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 590         mxc_request_iomux(MX51_PIN_GPIO1_0,
 591                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 592         mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
 593                 PAD_CTL_HYS_ENABLE);
 594         mxc_request_iomux(MX51_PIN_GPIO1_1,
 595                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 596         mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
 597                 PAD_CTL_HYS_ENABLE);
 598
 599         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 600 }
 601 #endif
 602
 603 int board_early_init_f(void)
 604 {
 605
 606
 607         init_drive_strength();
 608
 609         /* Setup debug led */
 610         gpio_direction_output(6, 0);
 611         mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
 612         mxc_iomux_set_pad(MX51_PIN_GPIO1_6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 613
 614         /* wait a little while to give the pll time to settle */
 615         sdelay(100000);
 616
 617         setup_weim();
 618         setup_uart();
 619         setup_fec();
 620         setup_gpios();
 621
 622         spi_io_init();
 623
 624         return 0;
 625 }
 626
 627 static void backlight(int on)
 628 {
 629         if (on) {
 630                 gpio_set_value(65, 1);
 631                 udelay(10000);
 632                 gpio_set_value(68, 1);
 633         } else {
 634                 gpio_set_value(65, 0);
 635                 gpio_set_value(68, 0);
 636         }
 637 }
 638
 639 void lcd_enable(void)
 640 {
 641         int ret;
 642
 643         mxc_request_iomux(MX51_PIN_DI1_PIN2, IOMUX_CONFIG_ALT0);
 644         mxc_request_iomux(MX51_PIN_DI1_PIN3, IOMUX_CONFIG_ALT0);
 645
 646         gpio_set_value(2, 1);
 647         mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0);
 648
 649         ret = mx51_fb_init(&nec_nl6448bc26_09c);
 650         if (ret)
 651                 puts("LCD cannot be configured\n");
 652 }
 653
 654 int board_init(void)
 655 {
 656         gd->bd->bi_arch_number = MACH_TYPE_TTC_VISION2; /* board id for linux */
 657         /* address of boot parameters */
 658         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 659
 660         return 0;
 661 }
 662
 663 int board_late_init(void)
 664 {
 665         power_init_mx51();
 666
 667         reset_peripherals(1);
 668         udelay(2000);
 669         reset_peripherals(0);
 670         udelay(2000);
 671
 672         /* Early revisions require a second reset */
 673 #ifdef CONFIG_VISION2_HW_1_0
 674         reset_peripherals(1);
 675         udelay(2000);
 676         reset_peripherals(0);
 677         udelay(2000);
 678 #endif
 679
 680         return 0;
 681 }
 682
 683 int checkboard(void)
 684 {
 685         puts("Board: TTControl Vision II CPU V\n");
 686
 687         return 0;
 688 }
 689
 690 int do_vision_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 691 {
 692         int on;
 693
 694         if (argc < 2)
 695                 return cmd_usage(cmdtp);
 696
 697         on = (strcmp(argv[1], "on") == 0);
 698         backlight(on);
 699
 700         return 0;
 701 }
 702
 703 U_BOOT_CMD(
 704         lcdbl, CONFIG_SYS_MAXARGS, 1, do_vision_lcd,
 705         "Vision2 Backlight",
 706         "lcdbl [on|off]\n"
 707 );