board/ttcontrol/vision2/vision2.c

   1 /*
   2  * (C) Copyright 2010
   3  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
   4  *
   5  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <asm/io.h>
  28 #include <asm/arch/imx-regs.h>
  29 #include <asm/arch/mx5x_pins.h>
  30 #include <asm/arch/crm_regs.h>
  31 #include <asm/arch/iomux.h>
  32 #include <asm/gpio.h>
  33 #include <asm/arch/sys_proto.h>
  34 #include <asm/errno.h>
  35 #include <i2c.h>
  36 #include <mmc.h>
  37 #include <pmic.h>
  38 #include <fsl_esdhc.h>
  39 #include <fsl_pmic.h>
  40 #include <mc13892.h>
  41 #include <linux/fb.h>
  42
  43 #include <ipu_pixfmt.h>
  44
  45 DECLARE_GLOBAL_DATA_PTR;
  46
  47 static u32 system_rev;
  48
  49 static struct fb_videomode nec_nl6448bc26_09c = {
  50         "NEC_NL6448BC26-09C",
  51         60,     /* Refresh */
  52         640,    /* xres */
  53         480,    /* yres */
  54         37650,  /* pixclock = 26.56Mhz */
  55         48,     /* left margin */
  56         16,     /* right margin */
  57         31,     /* upper margin */
  58         12,     /* lower margin */
  59         96,     /* hsync-len */
  60         2,      /* vsync-len */
  61         0,      /* sync */
  62         FB_VMODE_NONINTERLACED, /* vmode */
  63         0,      /* flag */
  64 };
  65
  66 #ifdef CONFIG_HW_WATCHDOG
  67 #include <watchdog.h>
  68 void hw_watchdog_reset(void)
  69 {
  70         int val;
  71
  72         /* toggle watchdog trigger pin */
  73         val = gpio_get_value(66);
  74         val = val ? 0 : 1;
  75         gpio_set_value(66, val);
  76 }
  77 #endif
  78
  79 static void init_drive_strength(void)
  80 {
  81         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
  82         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
  83         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
  84         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
  85         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
  86         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
  87         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
  88         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
  89                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
  90         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
  91                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
  92         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
  93         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
  94         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
  95         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
  96         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
  97         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
  98         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
  99         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
 100         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
 101         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
 102         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
 103         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
 104         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
 105         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
 106         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
 107         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
 108
 109         /* Setting pad options */
 110         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
 111                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 112                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 113         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
 114                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 115                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 116         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
 117                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 118                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 119         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
 120                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 121                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 122         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
 123                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 124                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 125         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
 126                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 127                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 128         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
 129                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 130                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 131         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
 132                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 133                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 134         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
 135                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 136                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 137         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
 138                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 139                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 140         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
 141                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 142                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 143         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
 144                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 145                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 146         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
 147                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 148                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 149         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
 150                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 151                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 152 }
 153
 154 u32 get_board_rev(void)
 155 {
 156         system_rev = get_cpu_rev();
 157
 158         return system_rev;
 159 }
 160
 161 int dram_init(void)
 162 {
 163         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
 164                 PHYS_SDRAM_1_SIZE);
 165
 166         return 0;
 167 }
 168
 169 static void setup_weim(void)
 170 {
 171         struct weim  *pweim = (struct weim *)WEIM_BASE_ADDR;
 172
 173         pweim->cs0gcr1 = 0x004100b9;
 174         pweim->cs0gcr2 = 0x00000001;
 175         pweim->cs0rcr1 = 0x0a018000;
 176         pweim->cs0rcr2 = 0;
 177         pweim->cs0wcr1 = 0x0704a240;
 178 }
 179
 180 static void setup_uart(void)
 181 {
 182         unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
 183                          PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST;
 184         /* console RX on Pin EIM_D25 */
 185         mxc_request_iomux(MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT3);
 186         mxc_iomux_set_pad(MX51_PIN_EIM_D25, pad);
 187         /* console TX on Pin EIM_D26 */
 188         mxc_request_iomux(MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT3);
 189         mxc_iomux_set_pad(MX51_PIN_EIM_D26, pad);
 190 }
 191
 192 #ifdef CONFIG_MXC_SPI
 193 void spi_io_init(void)
 194 {
 195         /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
 196         mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
 197         mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
 198                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 199
 200         /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
 201         mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
 202         mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
 203                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 204
 205         /* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */
 206         mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
 207         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0,
 208                 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
 209                 PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 210
 211         /*
 212          * SS1 will be used as GPIO because of uninterrupted
 213          * long SPI transmissions (GPIO4_25)
 214          */
 215         mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
 216         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1,
 217                 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
 218                 PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 219
 220         /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
 221         mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT7);
 222         mxc_iomux_set_pad(MX51_PIN_DI1_PIN11,
 223                 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
 224                 PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 225
 226         /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
 227         mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
 228         mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
 229                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 230 }
 231
 232 static void reset_peripherals(int reset)
 233 {
 234         if (reset) {
 235
 236                 /* reset_n is on NANDF_D15 */
 237                 gpio_direction_output(89, 0);
 238
 239 #ifdef CONFIG_VISION2_HW_1_0
 240                 /*
 241                  * set FEC Configuration lines
 242                  * set levels of FEC config lines
 243                  */
 244                 gpio_direction_output(75, 0);
 245                 gpio_direction_output(74, 1);
 246                 gpio_direction_output(95, 1);
 247
 248                 /* set direction of FEC config lines */
 249                 gpio_direction_output(59, 0);
 250                 gpio_direction_output(60, 0);
 251                 gpio_direction_output(61, 0);
 252                 gpio_direction_output(55, 1);
 253
 254                 /* FEC_RXD1 - sel GPIO (2-23) for configuration -> 1 */
 255                 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
 256                 /* FEC_RXD2 - sel GPIO (2-27) for configuration -> 0 */
 257                 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT1);
 258                 /* FEC_RXD3 - sel GPIO (2-28) for configuration -> 0 */
 259                 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT1);
 260                 /* FEC_RXER - sel GPIO (2-29) for configuration -> 0 */
 261                 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT1);
 262                 /* FEC_COL  - sel GPIO (3-10) for configuration -> 1 */
 263                 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT3);
 264                 /* FEC_RCLK - sel GPIO (3-11) for configuration -> 0 */
 265                 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT3);
 266                 /* FEC_RXD0 - sel GPIO (3-31) for configuration -> 1 */
 267                 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT3);
 268 #endif
 269
 270                 /*
 271                  * activate reset_n pin
 272                  * Select mux mode: ALT3 mux port: NAND D15
 273                  */
 274                 mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT3);
 275                 mxc_iomux_set_pad(MX51_PIN_NANDF_D15,
 276                         PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DRV_MAX);
 277         } else {
 278                 /* set FEC Control lines */
 279                 gpio_direction_input(89);
 280                 udelay(500);
 281
 282 #ifdef CONFIG_VISION2_HW_1_0
 283                 /* FEC RDATA[3] */
 284                 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
 285                 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
 286
 287                 /* FEC RDATA[2] */
 288                 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
 289                 mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
 290
 291                 /* FEC RDATA[1] */
 292                 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
 293                 mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
 294
 295                 /* FEC RDATA[0] */
 296                 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
 297                 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
 298
 299                 /* FEC RX_CLK */
 300                 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
 301                 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
 302
 303                 /* FEC RX_ER */
 304                 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
 305                 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
 306
 307                 /* FEC COL */
 308                 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
 309                 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
 310 #endif
 311         }
 312 }
 313
 314 static void power_init_mx51(void)
 315 {
 316         unsigned int val;
 317         struct pmic *p;
 318
 319         pmic_init();
 320         p = get_pmic();
 321
 322         /* Write needed to Power Gate 2 register */
 323         pmic_reg_read(p, REG_POWER_MISC, &val);
 324
 325         /* enable VCAM with 2.775V to enable read from PMIC */
 326         val = VCAMCONFIG | VCAMEN;
 327         pmic_reg_write(p, REG_MODE_1, val);
 328
 329         /*
 330          * Set switchers in Auto in NORMAL mode & STANDBY mode
 331          * Setup the switcher mode for SW1 & SW2
 332          */
 333         pmic_reg_read(p, REG_SW_4, &val);
 334         val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
 335                 (SWMODE_MASK << SWMODE2_SHIFT)));
 336         val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
 337                 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
 338         pmic_reg_write(p, REG_SW_4, val);
 339
 340         /* Setup the switcher mode for SW3 & SW4 */
 341         pmic_reg_read(p, REG_SW_5, &val);
 342         val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
 343                 (SWMODE_MASK << SWMODE3_SHIFT));
 344         val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
 345                 (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
 346         pmic_reg_write(p, REG_SW_5, val);
 347
 348
 349         /* Set VGEN3 to 1.8V, VCAM to 3.0V */
 350         pmic_reg_read(p, REG_SETTING_0, &val);
 351         val &= ~(VCAM_MASK | VGEN3_MASK);
 352         val |= VCAM_3_0;
 353         pmic_reg_write(p, REG_SETTING_0, val);
 354
 355         /* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */
 356         pmic_reg_read(p, REG_SETTING_1, &val);
 357         val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
 358         val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8;
 359         pmic_reg_write(p, REG_SETTING_1, val);
 360
 361         /* Configure VGEN3 and VCAM regulators to use external PNP */
 362         val = VGEN3CONFIG | VCAMCONFIG;
 363         pmic_reg_write(p, REG_MODE_1, val);
 364         udelay(200);
 365
 366         /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
 367         val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
 368                 VVIDEOEN | VAUDIOEN  | VSDEN;
 369         pmic_reg_write(p, REG_MODE_1, val);
 370
 371         pmic_reg_read(p, REG_POWER_CTL2, &val);
 372         val |= WDIRESET;
 373         pmic_reg_write(p, REG_POWER_CTL2, val);
 374
 375         udelay(2500);
 376
 377 }
 378 #endif
 379
 380 static void setup_gpios(void)
 381 {
 382         unsigned int i;
 383
 384         /* CAM_SUP_DISn, GPIO1_7 */
 385         mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
 386         mxc_iomux_set_pad(MX51_PIN_GPIO1_7, 0x82);
 387
 388         /* DAB Display EN, GPIO3_1 */
 389         mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4);
 390         mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, 0x82);
 391
 392         /* WDOG_TRIGGER, GPIO3_2 */
 393         mxc_request_iomux(MX51_PIN_DI1_PIN13, IOMUX_CONFIG_ALT4);
 394         mxc_iomux_set_pad(MX51_PIN_DI1_PIN13, 0x82);
 395
 396         /* Now we need to trigger the watchdog */
 397         WATCHDOG_RESET();
 398
 399         /* Display2 TxEN, GPIO3_3 */
 400         mxc_request_iomux(MX51_PIN_DI1_D0_CS, IOMUX_CONFIG_ALT4);
 401         mxc_iomux_set_pad(MX51_PIN_DI1_D0_CS, 0x82);
 402
 403         /* DAB Light EN, GPIO3_4 */
 404         mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
 405         mxc_iomux_set_pad(MX51_PIN_DI1_D1_CS, 0x82);
 406
 407         /* AUDIO_MUTE, GPIO3_5 */
 408         mxc_request_iomux(MX51_PIN_DISPB2_SER_DIN, IOMUX_CONFIG_ALT4);
 409         mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIN, 0x82);
 410
 411         /* SPARE_OUT, GPIO3_6 */
 412         mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_ALT4);
 413         mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIO, 0x82);
 414
 415         /* BEEPER_EN, GPIO3_26 */
 416         mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3);
 417         mxc_iomux_set_pad(MX51_PIN_NANDF_D14, 0x82);
 418
 419         /* POWER_OFF, GPIO3_27 */
 420         mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT3);
 421         mxc_iomux_set_pad(MX51_PIN_NANDF_D13, 0x82);
 422
 423         /* FRAM_WE, GPIO3_30 */
 424         mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT3);
 425         mxc_iomux_set_pad(MX51_PIN_NANDF_D10, 0x82);
 426
 427         /* EXPANSION_EN, GPIO4_26 */
 428         mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3);
 429         mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x82);
 430
 431         /* PWM Output GPIO1_2 */
 432         mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT1);
 433
 434         /*
 435          * Set GPIO1_4 to high and output; it is used to reset
 436          * the system on reboot
 437          */
 438         gpio_direction_output(4, 1);
 439
 440         gpio_direction_output(7, 0);
 441         for (i = 65; i < 71; i++) {
 442                 gpio_direction_output(i, 0);
 443         }
 444
 445         gpio_direction_output(94, 0);
 446
 447         /* Set POWER_OFF high */
 448         gpio_direction_output(91, 1);
 449
 450         gpio_direction_output(90, 0);
 451
 452         gpio_direction_output(122, 0);
 453
 454         gpio_direction_output(121, 1);
 455
 456         WATCHDOG_RESET();
 457 }
 458
 459 static void setup_fec(void)
 460 {
 461         /*FEC_MDIO*/
 462         mxc_request_iomux(MX51_PIN_EIM_EB2, IOMUX_CONFIG_ALT3);
 463         mxc_iomux_set_pad(MX51_PIN_EIM_EB2, 0x1FD);
 464
 465         /*FEC_MDC*/
 466         mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
 467         mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
 468
 469         /* FEC RDATA[3] */
 470         mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
 471         mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
 472
 473         /* FEC RDATA[2] */
 474         mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
 475         mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
 476
 477         /* FEC RDATA[1] */
 478         mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
 479         mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
 480
 481         /* FEC RDATA[0] */
 482         mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
 483         mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
 484
 485         /* FEC TDATA[3] */
 486         mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
 487         mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
 488
 489         /* FEC TDATA[2] */
 490         mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
 491         mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
 492
 493         /* FEC TDATA[1] */
 494         mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
 495         mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
 496
 497         /* FEC TDATA[0] */
 498         mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
 499         mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
 500
 501         /* FEC TX_EN */
 502         mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
 503         mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
 504
 505         /* FEC TX_ER */
 506         mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
 507         mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
 508
 509         /* FEC TX_CLK */
 510         mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
 511         mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
 512
 513         /* FEC TX_COL */
 514         mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
 515         mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
 516
 517         /* FEC RX_CLK */
 518         mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
 519         mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
 520
 521         /* FEC RX_CRS */
 522         mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
 523         mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
 524
 525         /* FEC RX_ER */
 526         mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
 527         mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
 528
 529         /* FEC RX_DV */
 530         mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
 531         mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
 532 }
 533
 534 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 535         {MMC_SDHC1_BASE_ADDR, 1},
 536 };
 537
 538 int get_mmc_getcd(u8 *cd, struct mmc *mmc)
 539 {
 540         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 541
 542         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 543                 *cd = gpio_get_value(0);
 544         else
 545                 *cd = 0;
 546
 547         return 0;
 548 }
 549
 550 #ifdef CONFIG_FSL_ESDHC
 551 int board_mmc_init(bd_t *bis)
 552 {
 553         mxc_request_iomux(MX51_PIN_SD1_CMD,
 554                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 555         mxc_request_iomux(MX51_PIN_SD1_CLK,
 556                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 557         mxc_request_iomux(MX51_PIN_SD1_DATA0,
 558                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 559         mxc_request_iomux(MX51_PIN_SD1_DATA1,
 560                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 561         mxc_request_iomux(MX51_PIN_SD1_DATA2,
 562                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 563         mxc_request_iomux(MX51_PIN_SD1_DATA3,
 564                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 565         mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
 566                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 567                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 568                 PAD_CTL_PUE_PULL |
 569                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 570         mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
 571                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 572                 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
 573                 PAD_CTL_PUE_PULL |
 574                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 575         mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
 576                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 577                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 578                 PAD_CTL_PUE_PULL |
 579                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 580         mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
 581                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 582                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 583                 PAD_CTL_PUE_PULL |
 584                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 585         mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
 586                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 587                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 588                 PAD_CTL_PUE_PULL |
 589                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 590         mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
 591                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 592                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
 593                 PAD_CTL_PUE_PULL |
 594                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 595         mxc_request_iomux(MX51_PIN_GPIO1_0,
 596                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 597         mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
 598                 PAD_CTL_HYS_ENABLE);
 599         mxc_request_iomux(MX51_PIN_GPIO1_1,
 600                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 601         mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
 602                 PAD_CTL_HYS_ENABLE);
 603
 604         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 605 }
 606 #endif
 607
 608 void lcd_enable(void)
 609 {
 610         int ret;
 611
 612         mxc_request_iomux(MX51_PIN_DI1_PIN2, IOMUX_CONFIG_ALT0);
 613         mxc_request_iomux(MX51_PIN_DI1_PIN3, IOMUX_CONFIG_ALT0);
 614
 615         gpio_set_value(2, 1);
 616         mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0);
 617
 618         ret = mx51_fb_init(&nec_nl6448bc26_09c, 0, IPU_PIX_FMT_RGB666);
 619         if (ret)
 620                 puts("LCD cannot be configured\n");
 621 }
 622
 623 int board_early_init_f(void)
 624 {
 625
 626
 627         init_drive_strength();
 628
 629         /* Setup debug led */
 630         gpio_direction_output(6, 0);
 631         mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
 632         mxc_iomux_set_pad(MX51_PIN_GPIO1_6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 633
 634         /* wait a little while to give the pll time to settle */
 635         sdelay(100000);
 636
 637         setup_weim();
 638         setup_uart();
 639         setup_fec();
 640         setup_gpios();
 641
 642         spi_io_init();
 643
 644         return 0;
 645 }
 646
 647 static void backlight(int on)
 648 {
 649         if (on) {
 650                 gpio_set_value(65, 1);
 651                 udelay(10000);
 652                 gpio_set_value(68, 1);
 653         } else {
 654                 gpio_set_value(65, 0);
 655                 gpio_set_value(68, 0);
 656         }
 657 }
 658
 659 int board_init(void)
 660 {
 661         /* address of boot parameters */
 662         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 663
 664         lcd_enable();
 665
 666         backlight(1);
 667
 668         return 0;
 669 }
 670
 671 int board_late_init(void)
 672 {
 673         power_init_mx51();
 674
 675         reset_peripherals(1);
 676         udelay(2000);
 677         reset_peripherals(0);
 678         udelay(2000);
 679
 680         /* Early revisions require a second reset */
 681 #ifdef CONFIG_VISION2_HW_1_0
 682         reset_peripherals(1);
 683         udelay(2000);
 684         reset_peripherals(0);
 685         udelay(2000);
 686 #endif
 687
 688         setenv("stdout", "serial");
 689
 690         return 0;
 691 }
 692
 693 int checkboard(void)
 694 {
 695         puts("Board: TTControl Vision II CPU V\n");
 696
 697         return 0;
 698 }
 699
 700 int do_vision_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 701 {
 702         int on;
 703
 704         if (argc < 2)
 705                 return cmd_usage(cmdtp);
 706
 707         on = (strcmp(argv[1], "on") == 0);
 708         backlight(on);
 709
 710         return 0;
 711 }
 712
 713 U_BOOT_CMD(
 714         lcdbl, CONFIG_SYS_MAXARGS, 1, do_vision_lcd,
 715         "Vision2 Backlight",
 716         "lcdbl [on|off]\n"
 717 );