board/ttcontrol/vision2/vision2.c

   1 /*
   2  * (C) Copyright 2010
   3  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
   4  *
   5  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <asm/io.h>
  28 #include <asm/arch/imx-regs.h>
  29 #include <asm/arch/mx5x_pins.h>
  30 #include <asm/arch/crm_regs.h>
  31 #include <asm/arch/iomux.h>
  32 #include <mxc_gpio.h>
  33 #include <asm/arch/sys_proto.h>
  34 #include <asm/errno.h>
  35 #include <i2c.h>
  36 #include <mmc.h>
  37 #include <fsl_esdhc.h>
  38 #include <fsl_pmic.h>
  39 #include <mc13892.h>
  40 #include <linux/fb.h>
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 static u32 system_rev;
  45
  46 extern int mx51_fb_init(struct fb_videomode *mode);
  47
  48 #ifdef CONFIG_HW_WATCHDOG
  49 #include <watchdog.h>
  50
  51 static struct fb_videomode nec_nl6448bc26_09c = {
  52         "NEC_NL6448BC26-09C",
  53         60,     /* Refresh */
  54         640,    /* xres */
  55         480,    /* yres */
  56         37650,  /* pixclock = 26.56Mhz */
  57         48,     /* left margin */
  58         16,     /* right margin */
  59         31,     /* upper margin */
  60         12,     /* lower margin */
  61         96,     /* hsync-len */
  62         2,      /* vsync-len */
  63         0,      /* sync */
  64         FB_VMODE_NONINTERLACED, /* vmode */
  65         0,      /* flag */
  66 };
  67
  68 void hw_watchdog_reset(void)
  69 {
  70         int val;
  71
  72         /* toggle watchdog trigger pin */
  73         val = mxc_gpio_get(66);
  74         val = val ? 0 : 1;
  75         mxc_gpio_set(66, val);
  76 }
  77 #endif
  78
  79 static void init_drive_strength(void)
  80 {
  81         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
  82         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
  83         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
  84         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
  85         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
  86         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
  87         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
  88         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
  89                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
  90         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
  91                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
  92         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
  93         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
  94         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
  95         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
  96         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
  97         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
  98         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
  99         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
 100         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
 101         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
 102         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
 103         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
 104         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
 105         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
 106         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
 107         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
 108
 109         /* Setting pad options */
 110         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
 111                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 112                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 113         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
 114                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 115                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 116         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
 117                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 118                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 119         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
 120                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 121                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 122         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
 123                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 124                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 125         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
 126                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 127                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 128         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
 129                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 130                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 131         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
 132                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 133                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 134         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
 135                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 136                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 137         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
 138                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 139                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 140         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
 141                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 142                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 143         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
 144                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 145                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 146         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
 147                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 148                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 149         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
 150                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 151                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 152 }
 153
 154 u32 get_board_rev(void)
 155 {
 156         system_rev = get_cpu_rev();
 157
 158         return system_rev;
 159 }
 160
 161 int dram_init(void)
 162 {
 163 #ifdef CONFIG_SYS_ARM_WITHOUT_RELOC
 164         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 165         gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
 166                 PHYS_SDRAM_1_SIZE);
 167 #if (CONFIG_NR_DRAM_BANKS > 1)
 168         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 169         gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
 170                 PHYS_SDRAM_2_SIZE);
 171 #endif
 172 #else
 173         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
 174                 PHYS_SDRAM_1_SIZE);
 175 #endif
 176
 177         return 0;
 178 }
 179
 180 static void setup_weim(void)
 181 {
 182         struct weim  *pweim = (struct weim *)WEIM_BASE_ADDR;
 183
 184         pweim->csgcr1 = 0x004100b9;
 185         pweim->csgcr2 = 0x00000001;
 186         pweim->csrcr1 = 0x0a018000;
 187         pweim->csrcr2 = 0;
 188         pweim->cswcr1 = 0x0704a240;
 189 }
 190
 191 static void setup_uart(void)
 192 {
 193         unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
 194                          PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST;
 195         /* console RX on Pin EIM_D25 */
 196         mxc_request_iomux(MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT3);
 197         mxc_iomux_set_pad(MX51_PIN_EIM_D25, pad);
 198         /* console TX on Pin EIM_D26 */
 199         mxc_request_iomux(MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT3);
 200         mxc_iomux_set_pad(MX51_PIN_EIM_D26, pad);
 201 }
 202
 203 #ifdef CONFIG_MXC_SPI
 204 void spi_io_init(void)
 205 {
 206         /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
 207         mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
 208         mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
 209                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 210
 211         /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
 212         mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
 213         mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
 214                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 215
 216         /* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */
 217         mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
 218         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0,
 219                 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
 220                 PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 221
 222         /*
 223          * SS1 will be used as GPIO because of uninterrupted
 224          * long SPI transmissions (GPIO4_25)
 225          */
 226         mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
 227         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1,
 228                 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
 229                 PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 230
 231         /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
 232         mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT7);
 233         mxc_iomux_set_pad(MX51_PIN_DI1_PIN11,
 234                 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
 235                 PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 236
 237         /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
 238         mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
 239         mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
 240                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 241 }
 242
 243 static void reset_peripherals(int reset)
 244 {
 245         if (reset) {
 246
 247                 /* reset_n is on NANDF_D15 */
 248                 mxc_gpio_set(89, 0);
 249                 mxc_gpio_direction(89, MXC_GPIO_DIRECTION_OUT);
 250
 251 #ifdef CONFIG_VISION2_HW_1_0
 252                 /*
 253                  * set FEC Configuration lines
 254                  * set levels of FEC config lines
 255                  */
 256                 mxc_gpio_set(75, 0);
 257                 mxc_gpio_set(74, 1);
 258                 mxc_gpio_set(95, 1);
 259                 mxc_gpio_direction(75, MXC_GPIO_DIRECTION_OUT);
 260                 mxc_gpio_direction(74, MXC_GPIO_DIRECTION_OUT);
 261                 mxc_gpio_direction(95, MXC_GPIO_DIRECTION_OUT);
 262
 263                 /* set direction of FEC config lines */
 264                 mxc_gpio_set(59, 0);
 265                 mxc_gpio_set(60, 0);
 266                 mxc_gpio_set(61, 0);
 267                 mxc_gpio_set(55, 1);
 268                 mxc_gpio_direction(59, MXC_GPIO_DIRECTION_OUT);
 269                 mxc_gpio_direction(60, MXC_GPIO_DIRECTION_OUT);
 270                 mxc_gpio_direction(61, MXC_GPIO_DIRECTION_OUT);
 271                 mxc_gpio_direction(55, MXC_GPIO_DIRECTION_OUT);
 272
 273                 /* FEC_RXD1 - sel GPIO (2-23) for configuration -> 1 */
 274                 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
 275                 /* FEC_RXD2 - sel GPIO (2-27) for configuration -> 0 */
 276                 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT1);
 277                 /* FEC_RXD3 - sel GPIO (2-28) for configuration -> 0 */
 278                 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT1);
 279                 /* FEC_RXER - sel GPIO (2-29) for configuration -> 0 */
 280                 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT1);
 281                 /* FEC_COL  - sel GPIO (3-10) for configuration -> 1 */
 282                 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT3);
 283                 /* FEC_RCLK - sel GPIO (3-11) for configuration -> 0 */
 284                 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT3);
 285                 /* FEC_RXD0 - sel GPIO (3-31) for configuration -> 1 */
 286                 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT3);
 287 #endif
 288
 289                 /*
 290                  * activate reset_n pin
 291                  * Select mux mode: ALT3 mux port: NAND D15
 292                  */
 293                 mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT3);
 294                 mxc_iomux_set_pad(MX51_PIN_NANDF_D15,
 295                         PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DRV_MAX);
 296         } else {
 297                 /* set FEC Control lines */
 298                 mxc_gpio_direction(89, MXC_GPIO_DIRECTION_IN);
 299                 udelay(500);
 300
 301 #ifdef CONFIG_VISION2_HW_1_0
 302                 /* FEC RDATA[3] */
 303                 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
 304                 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
 305
 306                 /* FEC RDATA[2] */
 307                 mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
 308                 mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
 309
 310                 /* FEC RDATA[1] */
 311                 mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
 312                 mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
 313
 314                 /* FEC RDATA[0] */
 315                 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
 316                 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
 317
 318                 /* FEC RX_CLK */
 319                 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
 320                 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
 321
 322                 /* FEC RX_ER */
 323                 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
 324                 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
 325
 326                 /* FEC COL */
 327                 mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
 328                 mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
 329 #endif
 330         }
 331 }
 332
 333 static void power_init_mx51(void)
 334 {
 335         unsigned int val;
 336
 337         /* Write needed to Power Gate 2 register */
 338         val = pmic_reg_read(REG_POWER_MISC);
 339
 340         /* enable VCAM with 2.775V to enable read from PMIC */
 341         val = VCAMCONFIG | VCAMEN;
 342         pmic_reg_write(REG_MODE_1, val);
 343
 344         /*
 345          * Set switchers in Auto in NORMAL mode & STANDBY mode
 346          * Setup the switcher mode for SW1 & SW2
 347          */
 348         val = pmic_reg_read(REG_SW_4);
 349         val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
 350                 (SWMODE_MASK << SWMODE2_SHIFT)));
 351         val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
 352                 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
 353         pmic_reg_write(REG_SW_4, val);
 354
 355         /* Setup the switcher mode for SW3 & SW4 */
 356         val = pmic_reg_read(REG_SW_5);
 357         val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
 358                 (SWMODE_MASK << SWMODE3_SHIFT));
 359         val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
 360                 (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
 361         pmic_reg_write(REG_SW_5, val);
 362
 363
 364         /* Set VGEN3 to 1.8V, VCAM to 3.0V */
 365         val = pmic_reg_read(REG_SETTING_0);
 366         val &= ~(VCAM_MASK | VGEN3_MASK);
 367         val |= VCAM_3_0;
 368         pmic_reg_write(REG_SETTING_0, val);
 369
 370         /* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */
 371         val = pmic_reg_read(REG_SETTING_1);
 372         val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
 373         val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8;
 374         pmic_reg_write(REG_SETTING_1, val);
 375
 376         /* Configure VGEN3 and VCAM regulators to use external PNP */
 377         val = VGEN3CONFIG | VCAMCONFIG;
 378         pmic_reg_write(REG_MODE_1, val);
 379         udelay(200);
 380
 381         /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
 382         val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
 383                 VVIDEOEN | VAUDIOEN  | VSDEN;
 384         pmic_reg_write(REG_MODE_1, val);
 385
 386         val = pmic_reg_read(REG_POWER_CTL2);
 387         val |= WDIRESET;
 388         pmic_reg_write(REG_POWER_CTL2, val);
 389
 390         udelay(2500);
 391
 392 }
 393 #endif
 394
 395 static void setup_gpios(void)
 396 {
 397         unsigned int i;
 398
 399         /* CAM_SUP_DISn, GPIO1_7 */
 400         mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
 401         mxc_iomux_set_pad(MX51_PIN_GPIO1_7, 0x82);
 402
 403         /* DAB Display EN, GPIO3_1 */
 404         mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4);
 405         mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, 0x82);
 406
 407         /* WDOG_TRIGGER, GPIO3_2 */
 408         mxc_request_iomux(MX51_PIN_DI1_PIN13, IOMUX_CONFIG_ALT4);
 409         mxc_iomux_set_pad(MX51_PIN_DI1_PIN13, 0x82);
 410
 411         /* Now we need to trigger the watchdog */
 412         WATCHDOG_RESET();
 413
 414         /* Display2 TxEN, GPIO3_3 */
 415         mxc_request_iomux(MX51_PIN_DI1_D0_CS, IOMUX_CONFIG_ALT4);
 416         mxc_iomux_set_pad(MX51_PIN_DI1_D0_CS, 0x82);
 417
 418         /* DAB Light EN, GPIO3_4 */
 419         mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
 420         mxc_iomux_set_pad(MX51_PIN_DI1_D1_CS, 0x82);
 421
 422         /* AUDIO_MUTE, GPIO3_5 */
 423         mxc_request_iomux(MX51_PIN_DISPB2_SER_DIN, IOMUX_CONFIG_ALT4);
 424         mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIN, 0x82);
 425
 426         /* SPARE_OUT, GPIO3_6 */
 427         mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_ALT4);
 428         mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIO, 0x82);
 429
 430         /* BEEPER_EN, GPIO3_26 */
 431         mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3);
 432         mxc_iomux_set_pad(MX51_PIN_NANDF_D14, 0x82);
 433
 434         /* POWER_OFF, GPIO3_27 */
 435         mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT3);
 436         mxc_iomux_set_pad(MX51_PIN_NANDF_D13, 0x82);
 437
 438         /* FRAM_WE, GPIO3_30 */
 439         mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT3);
 440         mxc_iomux_set_pad(MX51_PIN_NANDF_D10, 0x82);
 441
 442         /* EXPANSION_EN, GPIO4_26 */
 443         mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3);
 444         mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x82);
 445
 446         /* PWM Output GPIO1_2 */
 447         mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT1);
 448
 449         /*
 450          * Set GPIO1_4 to high and output; it is used to reset
 451          * the system on reboot
 452          */
 453         mxc_gpio_set(4, 1);
 454         mxc_gpio_direction(4, MXC_GPIO_DIRECTION_OUT);
 455
 456         mxc_gpio_set(7, 0);
 457         mxc_gpio_direction(7, MXC_GPIO_DIRECTION_OUT);
 458         for (i = 65; i < 71; i++) {
 459                 mxc_gpio_set(i, 0);
 460                 mxc_gpio_direction(i, MXC_GPIO_DIRECTION_OUT);
 461         }
 462
 463         mxc_gpio_set(94, 0);
 464         mxc_gpio_direction(94, MXC_GPIO_DIRECTION_OUT);
 465
 466         /* Set POWER_OFF high */
 467         mxc_gpio_set(91, 1);
 468         mxc_gpio_direction(91, MXC_GPIO_DIRECTION_OUT);
 469
 470         mxc_gpio_set(90, 0);
 471         mxc_gpio_direction(90, MXC_GPIO_DIRECTION_OUT);
 472
 473         mxc_gpio_set(122, 0);
 474         mxc_gpio_direction(122, MXC_GPIO_DIRECTION_OUT);
 475
 476         mxc_gpio_set(121, 1);
 477         mxc_gpio_direction(121, MXC_GPIO_DIRECTION_OUT);
 478
 479         WATCHDOG_RESET();
 480 }
 481
 482 static void setup_fec(void)
 483 {
 484         /*FEC_MDIO*/
 485         mxc_request_iomux(MX51_PIN_EIM_EB2, IOMUX_CONFIG_ALT3);
 486         mxc_iomux_set_pad(MX51_PIN_EIM_EB2, 0x1FD);
 487
 488         /*FEC_MDC*/
 489         mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
 490         mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
 491
 492         /* FEC RDATA[3] */
 493         mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
 494         mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
 495
 496         /* FEC RDATA[2] */
 497         mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
 498         mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
 499
 500         /* FEC RDATA[1] */
 501         mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
 502         mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
 503
 504         /* FEC RDATA[0] */
 505         mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
 506         mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
 507
 508         /* FEC TDATA[3] */
 509         mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
 510         mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
 511
 512         /* FEC TDATA[2] */
 513         mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
 514         mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
 515
 516         /* FEC TDATA[1] */
 517         mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
 518         mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
 519
 520         /* FEC TDATA[0] */
 521         mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
 522         mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
 523
 524         /* FEC TX_EN */
 525         mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
 526         mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
 527
 528         /* FEC TX_ER */
 529         mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
 530         mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
 531
 532         /* FEC TX_CLK */
 533         mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
 534         mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
 535
 536         /* FEC TX_COL */
 537         mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
 538         mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
 539
 540         /* FEC RX_CLK */
 541         mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
 542         mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
 543
 544         /* FEC RX_CRS */
 545         mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
 546         mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
 547
 548         /* FEC RX_ER */
 549         mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
 550         mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
 551
 552         /* FEC RX_DV */
 553         mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
 554         mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
 555 }
 556
 557 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 558         {MMC_SDHC1_BASE_ADDR, 1},
 559 };
 560
 561 int get_mmc_getcd(u8 *cd, struct mmc *mmc)
 562 {
 563         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 564
 565         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 566                 *cd = mxc_gpio_get(0);
 567         else
 568                 *cd = 0;
 569
 570         return 0;
 571 }
 572
 573 #ifdef CONFIG_FSL_ESDHC
 574 int board_mmc_init(bd_t *bis)
 575 {
 576         mxc_request_iomux(MX51_PIN_SD1_CMD,
 577                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 578         mxc_request_iomux(MX51_PIN_SD1_CLK,
 579                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 580         mxc_request_iomux(MX51_PIN_SD1_DATA0,
 581                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 582         mxc_request_iomux(MX51_PIN_SD1_DATA1,
 583                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 584         mxc_request_iomux(MX51_PIN_SD1_DATA2,
 585                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 586         mxc_request_iomux(MX51_PIN_SD1_DATA3,
 587                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 588         mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
 589                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 590                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 591                 PAD_CTL_PUE_PULL |
 592                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 593         mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
 594                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 595                 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
 596                 PAD_CTL_PUE_PULL |
 597                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 598         mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
 599                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 600                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 601                 PAD_CTL_PUE_PULL |
 602                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 603         mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
 604                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 605                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 606                 PAD_CTL_PUE_PULL |
 607                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 608         mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
 609                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 610                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 611                 PAD_CTL_PUE_PULL |
 612                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 613         mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
 614                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 615                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
 616                 PAD_CTL_PUE_PULL |
 617                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 618         mxc_request_iomux(MX51_PIN_GPIO1_0,
 619                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 620         mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
 621                 PAD_CTL_HYS_ENABLE);
 622         mxc_request_iomux(MX51_PIN_GPIO1_1,
 623                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 624         mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
 625                 PAD_CTL_HYS_ENABLE);
 626
 627         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 628 }
 629 #endif
 630
 631 int board_early_init_f(void)
 632 {
 633
 634
 635         init_drive_strength();
 636
 637         /* Setup debug led */
 638         mxc_gpio_set(6, 0);
 639         mxc_gpio_direction(6, MXC_GPIO_DIRECTION_OUT);
 640         mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
 641         mxc_iomux_set_pad(MX51_PIN_GPIO1_6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
 642
 643         /* wait a little while to give the pll time to settle */
 644         sdelay(100000);
 645
 646         setup_weim();
 647         setup_uart();
 648         setup_fec();
 649         setup_gpios();
 650
 651         spi_io_init();
 652
 653         return 0;
 654 }
 655
 656 static void backlight(int on)
 657 {
 658         if (on) {
 659                 mxc_gpio_set(65, 1);
 660                 udelay(10000);
 661                 mxc_gpio_set(68, 1);
 662         } else {
 663                 mxc_gpio_set(65, 0);
 664                 mxc_gpio_set(68, 0);
 665         }
 666 }
 667
 668 void lcd_enable(void)
 669 {
 670         int ret;
 671
 672         mxc_request_iomux(MX51_PIN_DI1_PIN2, IOMUX_CONFIG_ALT0);
 673         mxc_request_iomux(MX51_PIN_DI1_PIN3, IOMUX_CONFIG_ALT0);
 674
 675         mxc_gpio_set(2, 1);
 676         mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0);
 677
 678         ret = mx51_fb_init(&nec_nl6448bc26_09c);
 679         if (ret)
 680                 puts("LCD cannot be configured\n");
 681 }
 682
 683 int board_init(void)
 684 {
 685 #ifdef CONFIG_SYS_ARM_WITHOUT_RELOC
 686         board_early_init_f();
 687 #endif
 688         gd->bd->bi_arch_number = MACH_TYPE_TTC_VISION2; /* board id for linux */
 689         /* address of boot parameters */
 690         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 691
 692         return 0;
 693 }
 694
 695 int board_late_init(void)
 696 {
 697         power_init_mx51();
 698
 699         reset_peripherals(1);
 700         udelay(2000);
 701         reset_peripherals(0);
 702         udelay(2000);
 703
 704         /* Early revisions require a second reset */
 705 #ifdef CONFIG_VISION2_HW_1_0
 706         reset_peripherals(1);
 707         udelay(2000);
 708         reset_peripherals(0);
 709         udelay(2000);
 710 #endif
 711
 712         return 0;
 713 }
 714
 715 int checkboard(void)
 716 {
 717         u32 system_rev = get_cpu_rev();
 718         u32 cause;
 719         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 720
 721         puts("Board: TTControl Vision II CPU V");
 722
 723         switch (system_rev & 0xff) {
 724         case CHIP_REV_3_0:
 725                 puts("3.0 [");
 726                 break;
 727         case CHIP_REV_2_5:
 728                 puts("2.5 [");
 729                 break;
 730         case CHIP_REV_2_0:
 731                 puts("2.0 [");
 732                 break;
 733         case CHIP_REV_1_1:
 734                 puts("1.1 [");
 735                 break;
 736         case CHIP_REV_1_0:
 737         default:
 738                 puts("1.0 [");
 739                 break;
 740         }
 741
 742         cause = src_regs->srsr;
 743         switch (cause) {
 744         case 0x0001:
 745                 puts("POR");
 746                 break;
 747         case 0x0009:
 748                 puts("RST");
 749                 break;
 750         case 0x0010:
 751         case 0x0011:
 752                 puts("WDOG");
 753                 break;
 754         default:
 755                 printf("unknown 0x%x", cause);
 756         }
 757         puts("]\n");
 758
 759         return 0;
 760 }
 761
 762 int do_vision_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 763 {
 764         int on;
 765
 766         if (argc < 2)
 767                 return cmd_usage(cmdtp);
 768
 769         on = (strcmp(argv[1], "on") == 0);
 770         backlight(on);
 771
 772         return 0;
 773 }
 774
 775 U_BOOT_CMD(
 776         lcdbl, CONFIG_SYS_MAXARGS, 1, do_vision_lcd,
 777         "Vision2 Backlight",
 778         "lcdbl [on|off]\n"
 779 );