board/wandboard/wandboard.c

   1 /*
   2  * Copyright (C) 2013 Freescale Semiconductor, Inc.
   3  * Copyright (C) 2014 O.S. Systems Software LTDA.
   4  *
   5  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/mxc_hdmi.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/gpio.h>
  18 #include <asm/imx-common/iomux-v3.h>
  19 #include <asm/imx-common/mxc_i2c.h>
  20 #include <asm/imx-common/boot_mode.h>
  21 #include <asm/imx-common/video.h>
  22 #include <asm/io.h>
  23 #include <linux/sizes.h>
  24 #include <common.h>
  25 #include <fsl_esdhc.h>
  26 #include <mmc.h>
  27 #include <miiphy.h>
  28 #include <netdev.h>
  29 #include <phy.h>
  30 #include <input.h>
  31 #include <i2c.h>
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  36         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  37         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  38
  39 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  40         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  41         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  42
  43 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  44         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  45
  46 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  47         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  48         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  49
  50 #define USDHC1_CD_GPIO          IMX_GPIO_NR(1, 2)
  51 #define USDHC3_CD_GPIO          IMX_GPIO_NR(3, 9)
  52 #define ETH_PHY_RESET           IMX_GPIO_NR(3, 29)
  53 #define REV_DETECTION           IMX_GPIO_NR(2, 28)
  54
  55 int dram_init(void)
  56 {
  57         gd->ram_size = imx_ddr_size();
  58
  59         return 0;
  60 }
  61
  62 static iomux_v3_cfg_t const uart1_pads[] = {
  63         IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  64         IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  65 };
  66
  67 static iomux_v3_cfg_t const usdhc1_pads[] = {
  68         IOMUX_PADS(PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  69         IOMUX_PADS(PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  70         IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  71         IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  72         IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  73         IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  74         /* Carrier MicroSD Card Detect */
  75         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02),
  76 };
  77
  78 static iomux_v3_cfg_t const usdhc3_pads[] = {
  79         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  80         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  81         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  82         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  83         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  84         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  85         /* SOM MicroSD Card Detect */
  86         IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09),
  87 };
  88
  89 static iomux_v3_cfg_t const enet_pads[] = {
  90         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  91         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  92         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  93         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  94         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  95         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  96         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  97         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  98         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  99         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 100         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 101         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 102         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 103         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 104         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 105         /* AR8031 PHY Reset */
 106         IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29),
 107 };
 108
 109 static iomux_v3_cfg_t const rev_detection_pad[] = {
 110         IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 111 };
 112
 113 static void setup_iomux_uart(void)
 114 {
 115         SETUP_IOMUX_PADS(uart1_pads);
 116 }
 117
 118 static void setup_iomux_enet(void)
 119 {
 120         SETUP_IOMUX_PADS(enet_pads);
 121
 122         /* Reset AR8031 PHY */
 123         gpio_direction_output(ETH_PHY_RESET, 0);
 124         udelay(500);
 125         gpio_set_value(ETH_PHY_RESET, 1);
 126 }
 127
 128 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 129         {USDHC3_BASE_ADDR},
 130         {USDHC1_BASE_ADDR},
 131 };
 132
 133 int board_mmc_getcd(struct mmc *mmc)
 134 {
 135         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 136         int ret = 0;
 137
 138         switch (cfg->esdhc_base) {
 139         case USDHC1_BASE_ADDR:
 140                 ret = !gpio_get_value(USDHC1_CD_GPIO);
 141                 break;
 142         case USDHC3_BASE_ADDR:
 143                 ret = !gpio_get_value(USDHC3_CD_GPIO);
 144                 break;
 145         }
 146
 147         return ret;
 148 }
 149
 150 int board_mmc_init(bd_t *bis)
 151 {
 152         int ret;
 153         u32 index = 0;
 154
 155         /*
 156          * Following map is done:
 157          * (U-boot device node)    (Physical Port)
 158          * mmc0                    SOM MicroSD
 159          * mmc1                    Carrier board MicroSD
 160          */
 161         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 162                 switch (index) {
 163                 case 0:
 164                         SETUP_IOMUX_PADS(usdhc3_pads);
 165                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 166                         usdhc_cfg[0].max_bus_width = 4;
 167                         gpio_direction_input(USDHC3_CD_GPIO);
 168                         break;
 169                 case 1:
 170                         SETUP_IOMUX_PADS(usdhc1_pads);
 171                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 172                         usdhc_cfg[1].max_bus_width = 4;
 173                         gpio_direction_input(USDHC1_CD_GPIO);
 174                         break;
 175                 default:
 176                         printf("Warning: you configured more USDHC controllers"
 177                                "(%d) then supported by the board (%d)\n",
 178                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 179                         return -EINVAL;
 180                 }
 181
 182                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 183                 if (ret)
 184                         return ret;
 185         }
 186
 187         return 0;
 188 }
 189
 190 static int mx6_rgmii_rework(struct phy_device *phydev)
 191 {
 192         unsigned short val;
 193
 194         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 195         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 196         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 197         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 198
 199         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 200         val &= 0xffe3;
 201         val |= 0x18;
 202         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 203
 204         /* introduce tx clock delay */
 205         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 206         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 207         val |= 0x0100;
 208         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 209
 210         return 0;
 211 }
 212
 213 int board_phy_config(struct phy_device *phydev)
 214 {
 215         mx6_rgmii_rework(phydev);
 216
 217         if (phydev->drv->config)
 218                 phydev->drv->config(phydev);
 219
 220         return 0;
 221 }
 222
 223 #if defined(CONFIG_VIDEO_IPUV3)
 224 struct i2c_pads_info mx6q_i2c2_pad_info = {
 225         .scl = {
 226                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
 227                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 228                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
 229                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 230                 .gp = IMX_GPIO_NR(4, 12)
 231         },
 232         .sda = {
 233                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
 234                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 235                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
 236                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 237                 .gp = IMX_GPIO_NR(4, 13)
 238         }
 239 };
 240
 241 struct i2c_pads_info mx6dl_i2c2_pad_info = {
 242         .scl = {
 243                 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
 244                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 245                 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
 246                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 247                 .gp = IMX_GPIO_NR(4, 12)
 248         },
 249         .sda = {
 250                 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
 251                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 252                 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
 253                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 254                 .gp = IMX_GPIO_NR(4, 13)
 255         }
 256 };
 257
 258 static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
 259         IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
 260         IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
 261         IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
 262         IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
 263         IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
 264         IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
 265         IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
 266         IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
 267         IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
 268         IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
 269         IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
 270         IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
 271         IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
 272         IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
 273         IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
 274         IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
 275         IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
 276         IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
 277         IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
 278         IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
 279         IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
 280         IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
 281         IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
 282         IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10), /* DISP0_BKLEN */
 283         IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11), /* DISP0_VDDEN */
 284 };
 285
 286 static void do_enable_hdmi(struct display_info_t const *dev)
 287 {
 288         imx_enable_hdmi_phy();
 289 }
 290
 291 static int detect_i2c(struct display_info_t const *dev)
 292 {
 293         return (0 == i2c_set_bus_num(dev->bus)) &&
 294                         (0 == i2c_probe(dev->addr));
 295 }
 296
 297 static void enable_fwadapt_7wvga(struct display_info_t const *dev)
 298 {
 299         SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
 300
 301         gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
 302         gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
 303 }
 304
 305 struct display_info_t const displays[] = {{
 306         .bus    = -1,
 307         .addr   = 0,
 308         .pixfmt = IPU_PIX_FMT_RGB24,
 309         .detect = detect_hdmi,
 310         .enable = do_enable_hdmi,
 311         .mode   = {
 312                 .name           = "HDMI",
 313                 .refresh        = 60,
 314                 .xres           = 1024,
 315                 .yres           = 768,
 316                 .pixclock       = 15385,
 317                 .left_margin    = 220,
 318                 .right_margin   = 40,
 319                 .upper_margin   = 21,
 320                 .lower_margin   = 7,
 321                 .hsync_len      = 60,
 322                 .vsync_len      = 10,
 323                 .sync           = FB_SYNC_EXT,
 324                 .vmode          = FB_VMODE_NONINTERLACED
 325 } }, {
 326         .bus    = 1,
 327         .addr   = 0x10,
 328         .pixfmt = IPU_PIX_FMT_RGB666,
 329         .detect = detect_i2c,
 330         .enable = enable_fwadapt_7wvga,
 331         .mode   = {
 332                 .name           = "FWBADAPT-LCD-F07A-0102",
 333                 .refresh        = 60,
 334                 .xres           = 800,
 335                 .yres           = 480,
 336                 .pixclock       = 33260,
 337                 .left_margin    = 128,
 338                 .right_margin   = 128,
 339                 .upper_margin   = 22,
 340                 .lower_margin   = 22,
 341                 .hsync_len      = 1,
 342                 .vsync_len      = 1,
 343                 .sync           = 0,
 344                 .vmode          = FB_VMODE_NONINTERLACED
 345 } } };
 346 size_t display_count = ARRAY_SIZE(displays);
 347
 348 static void setup_display(void)
 349 {
 350         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 351         int reg;
 352
 353         enable_ipu_clock();
 354         imx_setup_hdmi();
 355
 356         reg = readl(&mxc_ccm->chsccdr);
 357         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 358                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 359         writel(reg, &mxc_ccm->chsccdr);
 360
 361         /* Disable LCD backlight */
 362         SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
 363         gpio_direction_input(IMX_GPIO_NR(4, 20));
 364 }
 365 #endif /* CONFIG_VIDEO_IPUV3 */
 366
 367 int board_eth_init(bd_t *bis)
 368 {
 369         setup_iomux_enet();
 370
 371         return cpu_eth_init(bis);
 372 }
 373
 374 int board_early_init_f(void)
 375 {
 376         setup_iomux_uart();
 377 #if defined(CONFIG_VIDEO_IPUV3)
 378         setup_display();
 379 #endif
 380         return 0;
 381 }
 382
 383 /*
 384  * Do not overwrite the console
 385  * Use always serial for U-Boot console
 386  */
 387 int overwrite_console(void)
 388 {
 389         return 1;
 390 }
 391
 392 #ifdef CONFIG_CMD_BMODE
 393 static const struct boot_mode board_boot_modes[] = {
 394         /* 4 bit bus width */
 395         {"mmc0",          MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 396         {"mmc1",          MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 397         {NULL,   0},
 398 };
 399 #endif
 400
 401 static bool is_revc1(void)
 402 {
 403         SETUP_IOMUX_PADS(rev_detection_pad);
 404         gpio_direction_input(REV_DETECTION);
 405
 406         if (gpio_get_value(REV_DETECTION))
 407                 return true;
 408         else
 409                 return false;
 410 }
 411
 412 int board_late_init(void)
 413 {
 414 #ifdef CONFIG_CMD_BMODE
 415         add_board_boot_modes(board_boot_modes);
 416 #endif
 417
 418 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 419         if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
 420                 setenv("board_rev", "MX6Q");
 421         else
 422                 setenv("board_rev", "MX6DL");
 423
 424         if (is_revc1())
 425                 setenv("board_name", "C1");
 426         else
 427                 setenv("board_name", "B1");
 428 #endif
 429         return 0;
 430 }
 431
 432 int board_init(void)
 433 {
 434         /* address of boot parameters */
 435         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 436
 437         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
 438         if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
 439                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
 440         else
 441                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
 442
 443         return 0;
 444 }
 445
 446 int checkboard(void)
 447 {
 448         if (is_revc1())
 449                 puts("Board: Wandboard rev C1\n");
 450         else
 451                 puts("Board: Wandboard rev B1\n");
 452
 453         return 0;
 454 }