2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
34 #define CONFIG_83XX 1 /* needed for Linux kernel header files*/
35 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
37 #include <ppc_asm.tmpl>
40 #include <asm/cache.h>
43 #ifndef CONFIG_IDENT_STRING
44 #define CONFIG_IDENT_STRING "MPC83XX"
47 /* We don't want the MMU yet.
52 * Floating Point enable, Machine Check and Recoverable Interr.
55 #define MSR_KERNEL (MSR_FP|MSR_RI)
57 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
60 #if !defined(CONFIG_NAND_SPL) && !defined(CFG_RAMBOOT)
65 * Set up GOT: Global Offset Table
67 * Use r14 to access the GOT
70 GOT_ENTRY(_GOT2_TABLE_)
71 GOT_ENTRY(__bss_start)
74 #ifndef CONFIG_NAND_SPL
75 GOT_ENTRY(_FIXUP_TABLE_)
77 GOT_ENTRY(_start_of_vectors)
78 GOT_ENTRY(_end_of_vectors)
79 GOT_ENTRY(transfer_to_handler)
84 * The Hard Reset Configuration Word (HRCW) table is in the first 64
85 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8
86 * times so the processor can fetch it out of flash whether the flash
87 * is 8, 16, 32, or 64 bits wide (hardware trickery).
90 #define _HRCW_TABLE_ENTRY(w) \
91 .fill 8,1,(((w)>>24)&0xff); \
92 .fill 8,1,(((w)>>16)&0xff); \
93 .fill 8,1,(((w)>> 8)&0xff); \
94 .fill 8,1,(((w) )&0xff)
96 _HRCW_TABLE_ENTRY(CFG_HRCW_LOW)
97 _HRCW_TABLE_ENTRY(CFG_HRCW_HIGH)
100 * Magic number and version string - put it after the HRCW since it
101 * cannot be first in flash like it is in many other processors.
103 .long 0x27051956 /* U-Boot Magic Number */
105 .globl version_string
107 .ascii U_BOOT_VERSION
108 .ascii " (", __DATE__, " - ", __TIME__, ")"
109 .ascii " ", CONFIG_IDENT_STRING, "\0"
112 #ifndef CONFIG_DEFAULT_IMMR
113 #error CONFIG_DEFAULT_IMMR must be defined
114 #endif /* CFG_DEFAULT_IMMR */
116 #define CFG_IMMR CONFIG_DEFAULT_IMMR
117 #endif /* CFG_IMMR */
120 * After configuration, a system reset exception is executed using the
121 * vector at offset 0x100 relative to the base set by MSR[IP]. If
122 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the
123 * base address is 0xfff00000. In the case of a Power On Reset or Hard
124 * Reset, the value of MSR[IP] is determined by the CIP field in the
127 * Other bits in the HRCW set up the Base Address and Port Size in BR0.
128 * This determines the location of the boot ROM (flash or EPROM) in the
129 * processor's address space at boot time. As long as the HRCW is set up
130 * so that we eventually end up executing the code below when the
131 * processor executes the reset exception, the actual values used should
134 * Once we have got here, the address mask in OR0 is cleared so that the
135 * bottom 32K of the boot ROM is effectively repeated all throughout the
136 * processor's address space, after which we can jump to the absolute
137 * address at which the boot ROM was linked at compile time, and proceed
138 * to initialise the memory controller without worrying if the rug will
139 * be pulled out from under us, so to speak (it will be fine as long as
140 * we configure BR0 with the same boot ROM link address).
142 . = EXC_OFF_SYS_RESET
145 _start: /* time t 0 */
146 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH*/
150 . = EXC_OFF_SYS_RESET + 0x10
154 li r21, BOOTFLAG_WARM /* Software reboot */
158 boot_cold: /* time t 3 */
159 lis r4, CONFIG_DEFAULT_IMMR@h
161 boot_warm: /* time t 5 */
162 mfmsr r5 /* save msr contents */
164 ori r3, r3, CFG_IMMR@l
167 /* Initialise the E300 processor core */
168 /*------------------------------------------*/
174 /* Inflate flash location so it appears everywhere, calculate */
175 /* the absolute address in final location of the FLASH, jump */
176 /* there and deflate the flash size back to minimal size */
177 /*------------------------------------------------------------*/
179 lis r4, (CFG_MONITOR_BASE)@h
180 ori r4, r4, (CFG_MONITOR_BASE)@l
181 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
185 #if 1 /* Remapping flash with LAW0. */
186 bl remap_flash_by_law0
188 #endif /* CFG_FLASHBOOT */
195 * Cache must be enabled here for stack-in-cache trick.
196 * This means we need to enable the BATS.
198 * 1) for the EVB, original gt regs need to be mapped
199 * 2) need to have an IBAT for the 0xf region,
200 * we are running there!
201 * Cache should be turned on after BATs, since by default
202 * everything is write-through.
203 * The init-mem BAT can be reused after reloc. The old
204 * gt-regs BAT can be reused after board_init_f calls
205 * board_early_init_f (EVB only).
207 /* enable address translation */
211 /* enable and invalidate the data cache */
214 #ifdef CFG_INIT_RAM_LOCK
219 /* set up the stack pointer in our newly created
221 lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
222 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
224 li r0, 0 /* Make room for stack frame header and */
225 stwu r0, -4(r1) /* clear final stack frame so that */
226 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
229 /* let the C-code set up the rest */
231 /* Be careful to keep code relocatable & stack humble */
232 /*------------------------------------------------------*/
234 GET_GOT /* initialize GOT access */
238 /* run low-level CPU init code (in Flash)*/
243 /* run 1st part of board init code (in Flash)*/
246 #ifndef CONFIG_NAND_SPL
251 .globl _start_of_vectors
255 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
257 /* Data Storage exception. */
258 STD_EXCEPTION(0x300, DataStorage, UnknownException)
260 /* Instruction Storage exception. */
261 STD_EXCEPTION(0x400, InstStorage, UnknownException)
263 /* External Interrupt exception. */
265 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
268 /* Alignment exception. */
271 EXCEPTION_PROLOG(SRR0, SRR1)
276 addi r3,r1,STACK_FRAME_OVERHEAD
278 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
279 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
280 lwz r6,GOT(transfer_to_handler)
284 .long AlignmentException - _start + EXC_OFF_SYS_RESET
285 .long int_return - _start + EXC_OFF_SYS_RESET
287 /* Program check exception */
290 EXCEPTION_PROLOG(SRR0, SRR1)
291 addi r3,r1,STACK_FRAME_OVERHEAD
293 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
294 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
295 lwz r6,GOT(transfer_to_handler)
299 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
300 .long int_return - _start + EXC_OFF_SYS_RESET
302 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
304 /* I guess we could implement decrementer, and may have
305 * to someday for timekeeping.
307 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
309 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
310 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
311 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
312 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
314 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
315 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
317 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
318 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
319 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
323 * This exception occurs when the program counter matches the
324 * Instruction Address Breakpoint Register (IABR).
326 * I want the cpu to halt if this occurs so I can hunt around
327 * with the debugger and look at things.
329 * When DEBUG is defined, both machine check enable (in the MSR)
330 * and checkstop reset enable (in the reset mode register) are
331 * turned off and so a checkstop condition will result in the cpu
334 * I force the cpu into a checkstop condition by putting an illegal
335 * instruction here (at least this is the theory).
337 * well - that didnt work, so just do an infinite loop!
341 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
343 STD_EXCEPTION(0x1400, SMI, UnknownException)
345 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
346 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
347 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
348 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
349 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
350 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
351 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
352 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
353 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
354 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
355 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
356 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
357 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
358 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
359 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
360 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
361 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
362 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
363 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
364 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
365 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
366 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
367 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
368 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
369 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
370 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
371 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
374 .globl _end_of_vectors
380 * This code finishes saving the registers to the exception frame
381 * and jumps to the appropriate handler for the exception.
382 * Register r21 is pointer into trap frame, r1 has new stack pointer.
384 .globl transfer_to_handler
395 andi. r24,r23,0x3f00 /* get vector offset */
399 lwz r24,0(r23) /* virtual address of handler */
400 lwz r23,4(r23) /* where to go when done */
405 rfi /* jump to handler, enable MMU */
408 mfmsr r28 /* Disable interrupts */
412 SYNC /* Some chip revs need this... */
427 lwz r2,_NIP(r1) /* Restore environment */
436 #endif /* !CONFIG_NAND_SPL */
439 * This code initialises the E300 processor core
440 * (conforms to PowerPC 603e spec)
441 * Note: expects original MSR contents to be in r5.
443 .globl init_e300_core
444 init_e300_core: /* time t 10 */
445 /* Initialize machine status; enable machine check interrupt */
446 /*-----------------------------------------------------------*/
448 li r3, MSR_KERNEL /* Set ME and RI flags */
449 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
451 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
453 SYNC /* Some chip revs need this... */
456 mtspr SRR1, r3 /* Make SRR1 match MSR */
460 #if defined(CONFIG_WATCHDOG)
461 /* Initialise the Wathcdog values and reset it (if req) */
462 /*------------------------------------------------------*/
463 lis r4, CFG_WATCHDOG_VALUE
464 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
474 /* Disable Wathcdog */
475 /*-------------------*/
477 /* Check to see if its enabled for disabling
478 once disabled by SW you can't re-enable */
484 #endif /* CONFIG_WATCHDOG */
486 #if defined(CONFIG_MASK_AER_AO)
487 /* Write the Arbiter Event Enable to mask Address Only traps. */
488 /* This prevents the dcbz instruction from being trapped when */
489 /* HID0_ABE Address Broadcast Enable is set and the MEMORY */
490 /* COHERENCY bit is set in the WIMG bits, which is often */
491 /* needed for PCI operation. */
493 rlwinm r0, r4, 0, ~AER_AO
495 #endif /* CONFIG_MASK_AER_AO */
497 /* Initialize the Hardware Implementation-dependent Registers */
498 /* HID0 also contains cache control */
499 /*------------------------------------------------------*/
501 lis r3, CFG_HID0_INIT@h
502 ori r3, r3, CFG_HID0_INIT@l
506 lis r3, CFG_HID0_FINAL@h
507 ori r3, r3, CFG_HID0_FINAL@l
512 ori r3, r3, CFG_HID2@l
517 /*------------------------------*/
520 /* setup_bats - set them up to some initial state */
526 addis r4, r0, CFG_IBAT0L@h
527 ori r4, r4, CFG_IBAT0L@l
528 addis r3, r0, CFG_IBAT0U@h
529 ori r3, r3, CFG_IBAT0U@l
534 addis r4, r0, CFG_DBAT0L@h
535 ori r4, r4, CFG_DBAT0L@l
536 addis r3, r0, CFG_DBAT0U@h
537 ori r3, r3, CFG_DBAT0U@l
542 addis r4, r0, CFG_IBAT1L@h
543 ori r4, r4, CFG_IBAT1L@l
544 addis r3, r0, CFG_IBAT1U@h
545 ori r3, r3, CFG_IBAT1U@l
550 addis r4, r0, CFG_DBAT1L@h
551 ori r4, r4, CFG_DBAT1L@l
552 addis r3, r0, CFG_DBAT1U@h
553 ori r3, r3, CFG_DBAT1U@l
558 addis r4, r0, CFG_IBAT2L@h
559 ori r4, r4, CFG_IBAT2L@l
560 addis r3, r0, CFG_IBAT2U@h
561 ori r3, r3, CFG_IBAT2U@l
566 addis r4, r0, CFG_DBAT2L@h
567 ori r4, r4, CFG_DBAT2L@l
568 addis r3, r0, CFG_DBAT2U@h
569 ori r3, r3, CFG_DBAT2U@l
574 addis r4, r0, CFG_IBAT3L@h
575 ori r4, r4, CFG_IBAT3L@l
576 addis r3, r0, CFG_IBAT3U@h
577 ori r3, r3, CFG_IBAT3U@l
582 addis r4, r0, CFG_DBAT3L@h
583 ori r4, r4, CFG_DBAT3L@l
584 addis r3, r0, CFG_DBAT3U@h
585 ori r3, r3, CFG_DBAT3U@l
589 #ifdef CONFIG_HIGH_BATS
591 addis r4, r0, CFG_IBAT4L@h
592 ori r4, r4, CFG_IBAT4L@l
593 addis r3, r0, CFG_IBAT4U@h
594 ori r3, r3, CFG_IBAT4U@l
599 addis r4, r0, CFG_DBAT4L@h
600 ori r4, r4, CFG_DBAT4L@l
601 addis r3, r0, CFG_DBAT4U@h
602 ori r3, r3, CFG_DBAT4U@l
607 addis r4, r0, CFG_IBAT5L@h
608 ori r4, r4, CFG_IBAT5L@l
609 addis r3, r0, CFG_IBAT5U@h
610 ori r3, r3, CFG_IBAT5U@l
615 addis r4, r0, CFG_DBAT5L@h
616 ori r4, r4, CFG_DBAT5L@l
617 addis r3, r0, CFG_DBAT5U@h
618 ori r3, r3, CFG_DBAT5U@l
623 addis r4, r0, CFG_IBAT6L@h
624 ori r4, r4, CFG_IBAT6L@l
625 addis r3, r0, CFG_IBAT6U@h
626 ori r3, r3, CFG_IBAT6U@l
631 addis r4, r0, CFG_DBAT6L@h
632 ori r4, r4, CFG_DBAT6L@l
633 addis r3, r0, CFG_DBAT6U@h
634 ori r3, r3, CFG_DBAT6U@l
639 addis r4, r0, CFG_IBAT7L@h
640 ori r4, r4, CFG_IBAT7L@l
641 addis r3, r0, CFG_IBAT7U@h
642 ori r3, r3, CFG_IBAT7U@l
647 addis r4, r0, CFG_DBAT7L@h
648 ori r4, r4, CFG_DBAT7L@l
649 addis r3, r0, CFG_DBAT7U@h
650 ori r3, r3, CFG_DBAT7U@l
657 /* invalidate all tlb's
659 * From the 603e User Manual: "The 603e provides the ability to
660 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie)
661 * instruction invalidates the TLB entry indexed by the EA, and
662 * operates on both the instruction and data TLBs simultaneously
663 * invalidating four TLB entries (both sets in each TLB). The
664 * index corresponds to bits 15-19 of the EA. To invalidate all
665 * entries within both TLBs, 32 tlbie instructions should be
666 * issued, incrementing this field by one each time."
668 * "Note that the tlbia instruction is not implemented on the
671 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000
672 * incrementing by 0x1000 each time. The code below is sort of
673 * based on code in "flush_tlbs" from arch/ppc/kernel/head.S
687 .globl enable_addr_trans
689 /* enable address translation */
691 ori r5, r5, (MSR_IR | MSR_DR)
696 .globl disable_addr_trans
698 /* disable address translation */
701 andi. r0, r3, (MSR_IR | MSR_DR)
710 * Note: requires that all cache bits in
711 * HID0 are in the low half word.
718 ori r4, r4, HID0_ILOCK
720 ori r4, r3, HID0_ICFI
722 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
724 mtspr HID0, r3 /* clears invalidate */
727 .globl icache_disable
731 ori r4, r4, HID0_ICE|HID0_ILOCK
733 ori r4, r3, HID0_ICFI
735 mtspr HID0, r4 /* sets invalidate, clears enable and lock*/
737 mtspr HID0, r3 /* clears invalidate */
743 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
749 li r5, HID0_DCFI|HID0_DLOCK
751 mtspr HID0, r3 /* no invalidate, unlock */
753 ori r5, r3, HID0_DCFI
754 mtspr HID0, r5 /* enable + invalidate */
755 mtspr HID0, r3 /* enable */
759 .globl dcache_disable
763 ori r4, r4, HID0_DCE|HID0_DLOCK
767 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
769 mtspr HID0, r3 /* clears invalidate */
775 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
795 /*-------------------------------------------------------------------*/
798 * void relocate_code (addr_sp, gd, addr_moni)
800 * This "function" does not return, instead it continues in RAM
801 * after relocating the monitor code.
805 * r5 = length in bytes
810 mr r1, r3 /* Set new stack pointer */
811 mr r9, r4 /* Save copy of Global Data pointer */
812 mr r10, r5 /* Save copy of Destination Address */
814 mr r3, r5 /* Destination Address */
815 lis r4, CFG_MONITOR_BASE@h /* Source Address */
816 ori r4, r4, CFG_MONITOR_BASE@l
817 lwz r5, GOT(__bss_start)
819 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
824 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE)
825 * + Destination Address
831 /* First our own GOT */
833 /* then the one used by the C code */
843 beq cr1,4f /* In place copy is not necessary */
844 beq 7f /* Protect against 0 count */
873 2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
881 * Now flush the cache: note that we must start from a cache aligned
882 * address. Otherwise we might miss one cache line.
886 beq 7f /* Always flush prefetch queue in any case */
894 sync /* Wait for all dcbst to complete on bus */
900 7: sync /* Wait for all icbi to complete on bus */
904 * We are done. Do not return, instead branch to second part of board
905 * initialization, now running from RAM.
907 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
914 * Relocation Function, r14 point to got2+0x8000
916 * Adjust got2 pointers, no need to check for 0, this code
917 * already puts a few entries in the table.
919 li r0,__got2_entries@sectoff@l
920 la r3,GOT(_GOT2_TABLE_)
921 lwz r11,GOT(_GOT2_TABLE_)
930 #ifndef CONFIG_NAND_SPL
932 * Now adjust the fixups and the pointers to the fixups
933 * in case we need to move ourselves again.
935 2: li r0,__fixup_entries@sectoff@l
936 lwz r3,GOT(_FIXUP_TABLE_)
952 * Now clear BSS segment
954 lwz r3,GOT(__bss_start)
955 #if defined(CONFIG_HYMOD)
957 * For HYMOD - the environment is the very last item in flash.
958 * The real .bss stops just before environment starts, so only
959 * clear up to that point.
961 * taken from mods for FADS board
963 lwz r4,GOT(environment)
979 mr r3, r9 /* Global Data pointer */
980 mr r4, r10 /* Destination Address */
983 #ifndef CONFIG_NAND_SPL
985 * Copy exception vector code to low memory
988 * r7: source address, r8: end address, r9: target address
993 lwz r8, GOT(_end_of_vectors)
995 li r9, 0x100 /* reset vector always at 0x100 */
998 bgelr /* return if r7>=r8 - just in case */
1000 mflr r4 /* save link register */
1010 * relocate `hdlr' and `int_return' entries
1012 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
1013 li r8, Alignment - _start + EXC_OFF_SYS_RESET
1016 addi r7, r7, 0x100 /* next exception vector */
1020 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1023 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1026 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1027 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
1030 addi r7, r7, 0x100 /* next exception vector */
1034 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1035 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
1038 addi r7, r7, 0x100 /* next exception vector */
1042 mfmsr r3 /* now that the vectors have */
1043 lis r7, MSR_IP@h /* relocated into low memory */
1044 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
1045 andc r3, r3, r7 /* (if it was on) */
1046 SYNC /* Some chip revs need this... */
1050 mtlr r4 /* restore link register */
1054 * Function: relocate entries for one exception vector
1057 lwz r0, 0(r7) /* hdlr ... */
1058 add r0, r0, r3 /* ... += dest_addr */
1061 lwz r0, 4(r7) /* int_return ... */
1062 add r0, r0, r3 /* ... += dest_addr */
1066 #endif /* !CONFIG_NAND_SPL */
1068 #ifdef CFG_INIT_RAM_LOCK
1070 /* Allocate Initial RAM in data cache.
1072 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
1073 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
1074 li r4, ((CFG_INIT_RAM_END & ~31) + \
1075 (CFG_INIT_RAM_ADDR & 31) + 31) / 32
1082 /* Lock the data cache */
1090 #ifndef CONFIG_NAND_SPL
1091 .globl unlock_ram_in_cache
1092 unlock_ram_in_cache:
1093 /* invalidate the INIT_RAM section */
1094 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
1095 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
1096 li r4, ((CFG_INIT_RAM_END & ~31) + \
1097 (CFG_INIT_RAM_ADDR & 31) + 31) / 32
1103 sync /* Wait for all icbi to complete on bus */
1106 /* Unlock the data cache and invalidate it */
1108 li r5, HID0_DLOCK|HID0_DCFI
1109 andc r3, r3, r5 /* no invalidate, unlock */
1110 ori r5, r3, HID0_DCFI /* invalidate, unlock */
1111 mtspr HID0, r5 /* invalidate, unlock */
1112 mtspr HID0, r3 /* no invalidate, unlock */
1115 #endif /* !CONFIG_NAND_SPL */
1116 #endif /* CFG_INIT_RAM_LOCK */
1118 #ifdef CFG_FLASHBOOT
1120 /* When booting from ROM (Flash or EPROM), clear the */
1121 /* Address Mask in OR0 so ROM appears everywhere */
1122 /*----------------------------------------------------*/
1123 lis r3, (CFG_IMMR)@h /* r3 <= CFG_IMMR */
1125 li r5, 0x7fff /* r5 <= 0x00007FFFF */
1127 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */
1129 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,
1130 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR]
1131 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot
1132 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is
1133 * 0xFF800. From the hard resetting to here, the processor fetched and
1134 * executed the instructions one by one. There is not absolutely
1135 * jumping happened. Laterly, the u-boot code has to do an absolutely
1136 * jumping to tell the CPU instruction fetching component what the
1137 * u-boot TEXT base address is. Because the TEXT base resides in the
1138 * boot ROM memory space, to garantee the code can run smoothly after
1139 * that jumping, we must map in the entire boot ROM by Local Access
1140 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting
1141 * address for boot ROM, such as 0xFE000000. In this case, the default
1142 * LBIU Local Access Widow 0 will not cover this memory space. So, we
1143 * need another window to map in it.
1145 lis r4, (CFG_FLASH_BASE)@h
1146 ori r4, r4, (CFG_FLASH_BASE)@l
1147 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_FLASH_BASE */
1149 /* Store 0x80000012 + log2(CFG_FLASH_SIZE) into LBLAWAR1 */
1150 lis r4, (0x80000012)@h
1151 ori r4, r4, (0x80000012)@l
1152 li r5, CFG_FLASH_SIZE
1153 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1157 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
1160 /* Though all the LBIU Local Access Windows and LBC Banks will be
1161 * initialized in the C code, we'd better configure boot ROM's
1162 * window 0 and bank 0 correctly at here.
1164 remap_flash_by_law0:
1165 /* Initialize the BR0 with the boot ROM starting address. */
1169 lis r5, (CFG_FLASH_BASE & 0xFFFF8000)@h
1170 ori r5, r5, (CFG_FLASH_BASE & 0xFFFF8000)@l
1172 stw r5, BR0(r3) /* r5 <= (CFG_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
1175 lis r5, ~((CFG_FLASH_SIZE << 4) - 1)
1179 lis r4, (CFG_FLASH_BASE)@h
1180 ori r4, r4, (CFG_FLASH_BASE)@l
1181 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_FLASH_BASE */
1183 /* Store 0x80000012 + log2(CFG_FLASH_SIZE) into LBLAWAR0 */
1184 lis r4, (0x80000012)@h
1185 ori r4, r4, (0x80000012)@l
1186 li r5, CFG_FLASH_SIZE
1187 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1190 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */
1194 stw r4, LBLAWBAR1(r3)
1195 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
1197 #endif /* CFG_FLASHBOOT */