cpu/mpc85xx/fdt.c

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2000
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <libfdt.h>
  28 #include <fdt_support.h>
  29 #include <asm/processor.h>
  30
  31 extern void ft_qe_setup(void *blob);
  32 #ifdef CONFIG_MP
  33 #include "mp.h"
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 void ft_fixup_cpu(void *blob, u64 memory_limit)
  37 {
  38         int off;
  39         ulong spin_tbl_addr = get_spin_addr();
  40         u32 bootpg, id = get_my_id();
  41
  42         /* if we have 4G or more of memory, put the boot page at 4Gb-4k */
  43         if ((u64)gd->ram_size > 0xfffff000)
  44                 bootpg = 0xfffff000;
  45         else
  46                 bootpg = gd->ram_size - 4096;
  47
  48         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  49         while (off != -FDT_ERR_NOTFOUND) {
  50                 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
  51
  52                 if (reg) {
  53                         if (*reg == id) {
  54                                 fdt_setprop_string(blob, off, "status", "okay");
  55                         } else {
  56                                 u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
  57                                 val = cpu_to_fdt32(val);
  58                                 fdt_setprop_string(blob, off, "status",
  59                                                                 "disabled");
  60                                 fdt_setprop_string(blob, off, "enable-method",
  61                                                                 "spin-table");
  62                                 fdt_setprop(blob, off, "cpu-release-addr",
  63                                                 &val, sizeof(val));
  64                         }
  65                 } else {
  66                         printf ("cpu NULL\n");
  67                 }
  68                 off = fdt_node_offset_by_prop_value(blob, off,
  69                                 "device_type", "cpu", 4);
  70         }
  71
  72         /* Reserve the boot page so OSes dont use it */
  73         if ((u64)bootpg < memory_limit) {
  74                 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
  75                 if (off < 0)
  76                         printf("%s: %s\n", __FUNCTION__, fdt_strerror(off));
  77         }
  78 }
  79 #endif
  80
  81 #ifdef CONFIG_L2_CACHE
  82 /* return size in kilobytes */
  83 static inline u32 l2cache_size(void)
  84 {
  85         volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR;
  86         volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
  87         u32 ver = SVR_SOC_VER(get_svr());
  88
  89         switch (l2siz_field) {
  90         case 0x0:
  91                 break;
  92         case 0x1:
  93                 if (ver == SVR_8540 || ver == SVR_8560   ||
  94                     ver == SVR_8541 || ver == SVR_8541_E ||
  95                     ver == SVR_8555 || ver == SVR_8555_E)
  96                         return 128;
  97                 else
  98                         return 256;
  99                 break;
 100         case 0x2:
 101                 if (ver == SVR_8540 || ver == SVR_8560   ||
 102                     ver == SVR_8541 || ver == SVR_8541_E ||
 103                     ver == SVR_8555 || ver == SVR_8555_E)
 104                         return 256;
 105                 else
 106                         return 512;
 107                 break;
 108         case 0x3:
 109                 return 1024;
 110                 break;
 111         }
 112
 113         return 0;
 114 }
 115
 116 static inline void ft_fixup_l2cache(void *blob)
 117 {
 118         int len, off;
 119         u32 *ph;
 120         struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
 121         char compat_buf[38];
 122
 123         const u32 line_size = 32;
 124         const u32 num_ways = 8;
 125         const u32 size = l2cache_size() * 1024;
 126         const u32 num_sets = size / (line_size * num_ways);
 127
 128         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 129         if (off < 0) {
 130                 debug("no cpu node fount\n");
 131                 return;
 132         }
 133
 134         ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
 135
 136         if (ph == NULL) {
 137                 debug("no next-level-cache property\n");
 138                 return ;
 139         }
 140
 141         off = fdt_node_offset_by_phandle(blob, *ph);
 142         if (off < 0) {
 143                 printf("%s: %s\n", __func__, fdt_strerror(off));
 144                 return ;
 145         }
 146
 147         if (cpu) {
 148                 len = sprintf(compat_buf, "fsl,mpc%s-l2-cache-controller",
 149                                 cpu->name);
 150                 sprintf(&compat_buf[len + 1], "cache");
 151         }
 152         fdt_setprop(blob, off, "cache-unified", NULL, 0);
 153         fdt_setprop_cell(blob, off, "cache-block-size", line_size);
 154         fdt_setprop_cell(blob, off, "cache-line-size", line_size);
 155         fdt_setprop_cell(blob, off, "cache-size", size);
 156         fdt_setprop_cell(blob, off, "cache-sets", num_sets);
 157         fdt_setprop_cell(blob, off, "cache-level", 2);
 158         fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf));
 159 }
 160 #else
 161 #define ft_fixup_l2cache(x)
 162 #endif
 163
 164 static inline void ft_fixup_cache(void *blob)
 165 {
 166         int off;
 167
 168         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 169
 170         while (off != -FDT_ERR_NOTFOUND) {
 171                 u32 l1cfg0 = mfspr(SPRN_L1CFG0);
 172                 u32 l1cfg1 = mfspr(SPRN_L1CFG1);
 173                 u32 isize, iline_size, inum_sets, inum_ways;
 174                 u32 dsize, dline_size, dnum_sets, dnum_ways;
 175
 176                 /* d-side config */
 177                 dsize = (l1cfg0 & 0x7ff) * 1024;
 178                 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
 179                 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
 180                 dnum_sets = dsize / (dline_size * dnum_ways);
 181
 182                 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
 183                 fdt_setprop_cell(blob, off, "d-cache-line-size", dline_size);
 184                 fdt_setprop_cell(blob, off, "d-cache-size", dsize);
 185                 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
 186
 187                 /* i-side config */
 188                 isize = (l1cfg1 & 0x7ff) * 1024;
 189                 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
 190                 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
 191                 inum_sets = isize / (iline_size * inum_ways);
 192
 193                 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
 194                 fdt_setprop_cell(blob, off, "i-cache-line-size", iline_size);
 195                 fdt_setprop_cell(blob, off, "i-cache-size", isize);
 196                 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
 197
 198                 off = fdt_node_offset_by_prop_value(blob, off,
 199                                 "device_type", "cpu", 4);
 200         }
 201
 202         ft_fixup_l2cache(blob);
 203 }
 204
 205
 206 void ft_cpu_setup(void *blob, bd_t *bd)
 207 {
 208 #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
 209     defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
 210         fdt_fixup_ethernet(blob, bd);
 211 #endif
 212
 213         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 214                 "timebase-frequency", bd->bi_busfreq / 8, 1);
 215         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 216                 "bus-frequency", bd->bi_busfreq, 1);
 217         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 218                 "clock-frequency", bd->bi_intfreq, 1);
 219         do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
 220                 "bus-frequency", bd->bi_busfreq, 1);
 221 #ifdef CONFIG_QE
 222         ft_qe_setup(blob);
 223 #endif
 224
 225 #ifdef CFG_NS16550
 226         do_fixup_by_compat_u32(blob, "ns16550",
 227                 "clock-frequency", bd->bi_busfreq, 1);
 228 #endif
 229
 230 #ifdef CONFIG_CPM2
 231         do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
 232                 "current-speed", bd->bi_baudrate, 1);
 233
 234         do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
 235                 "clock-frequency", bd->bi_brgfreq, 1);
 236 #endif
 237
 238         fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 239
 240 #ifdef CONFIG_MP
 241         ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
 242 #endif
 243
 244         ft_fixup_cache(blob);
 245 }