drivers/ddr/altera/sequencer.c

   1 /*
   2  * Copyright Altera Corporation (C) 2012-2015
   3  *
   4  * SPDX-License-Identifier:    BSD-3-Clause
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/sdram.h>
  10 #include <errno.h>
  11 #include "sequencer.h"
  12 #include "sequencer_auto.h"
  13 #include "sequencer_auto_ac_init.h"
  14 #include "sequencer_auto_inst_init.h"
  15 #include "sequencer_defines.h"
  16
  17 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
  18         (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
  19
  20 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
  21         (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
  22
  23 static struct socfpga_sdr_reg_file *sdr_reg_file =
  24         (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
  25
  26 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
  27         (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
  28
  29 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
  30         (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
  31
  32 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
  33         (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
  34
  35 static struct socfpga_data_mgr *data_mgr =
  36         (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
  37
  38 static struct socfpga_sdr_ctrl *sdr_ctrl =
  39         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
  40
  41 #define DELTA_D         1
  42
  43 /*
  44  * In order to reduce ROM size, most of the selectable calibration steps are
  45  * decided at compile time based on the user's calibration mode selection,
  46  * as captured by the STATIC_CALIB_STEPS selection below.
  47  *
  48  * However, to support simulation-time selection of fast simulation mode, where
  49  * we skip everything except the bare minimum, we need a few of the steps to
  50  * be dynamic.  In those cases, we either use the DYNAMIC_CALIB_STEPS for the
  51  * check, which is based on the rtl-supplied value, or we dynamically compute
  52  * the value to use based on the dynamically-chosen calibration mode
  53  */
  54
  55 #define DLEVEL 0
  56 #define STATIC_IN_RTL_SIM 0
  57 #define STATIC_SKIP_DELAY_LOOPS 0
  58
  59 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
  60         STATIC_SKIP_DELAY_LOOPS)
  61
  62 /* calibration steps requested by the rtl */
  63 uint16_t dyn_calib_steps;
  64
  65 /*
  66  * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
  67  * instead of static, we use boolean logic to select between
  68  * non-skip and skip values
  69  *
  70  * The mask is set to include all bits when not-skipping, but is
  71  * zero when skipping
  72  */
  73
  74 uint16_t skip_delay_mask;       /* mask off bits when skipping/not-skipping */
  75
  76 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
  77         ((non_skip_value) & skip_delay_mask)
  78
  79 struct gbl_type *gbl;
  80 struct param_type *param;
  81 uint32_t curr_shadow_reg;
  82
  83 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
  84         uint32_t write_group, uint32_t use_dm,
  85         uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
  86
  87 static void set_failing_group_stage(uint32_t group, uint32_t stage,
  88         uint32_t substage)
  89 {
  90         /*
  91          * Only set the global stage if there was not been any other
  92          * failing group
  93          */
  94         if (gbl->error_stage == CAL_STAGE_NIL)  {
  95                 gbl->error_substage = substage;
  96                 gbl->error_stage = stage;
  97                 gbl->error_group = group;
  98         }
  99 }
 100
 101 static void reg_file_set_group(u16 set_group)
 102 {
 103         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
 104 }
 105
 106 static void reg_file_set_stage(u8 set_stage)
 107 {
 108         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
 109 }
 110
 111 static void reg_file_set_sub_stage(u8 set_sub_stage)
 112 {
 113         set_sub_stage &= 0xff;
 114         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
 115 }
 116
 117 /**
 118  * phy_mgr_initialize() - Initialize PHY Manager
 119  *
 120  * Initialize PHY Manager.
 121  */
 122 static void phy_mgr_initialize(void)
 123 {
 124         u32 ratio;
 125
 126         debug("%s:%d\n", __func__, __LINE__);
 127         /* Calibration has control over path to memory */
 128         /*
 129          * In Hard PHY this is a 2-bit control:
 130          * 0: AFI Mux Select
 131          * 1: DDIO Mux Select
 132          */
 133         writel(0x3, &phy_mgr_cfg->mux_sel);
 134
 135         /* USER memory clock is not stable we begin initialization  */
 136         writel(0, &phy_mgr_cfg->reset_mem_stbl);
 137
 138         /* USER calibration status all set to zero */
 139         writel(0, &phy_mgr_cfg->cal_status);
 140
 141         writel(0, &phy_mgr_cfg->cal_debug_info);
 142
 143         /* Init params only if we do NOT skip calibration. */
 144         if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
 145                 return;
 146
 147         ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
 148                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
 149         param->read_correct_mask_vg = (1 << ratio) - 1;
 150         param->write_correct_mask_vg = (1 << ratio) - 1;
 151         param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
 152         param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
 153         ratio = RW_MGR_MEM_DATA_WIDTH /
 154                 RW_MGR_MEM_DATA_MASK_WIDTH;
 155         param->dm_correct_mask = (1 << ratio) - 1;
 156 }
 157
 158 /**
 159  * set_rank_and_odt_mask() - Set Rank and ODT mask
 160  * @rank:       Rank mask
 161  * @odt_mode:   ODT mode, OFF or READ_WRITE
 162  *
 163  * Set Rank and ODT mask (On-Die Termination).
 164  */
 165 static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
 166 {
 167         u32 odt_mask_0 = 0;
 168         u32 odt_mask_1 = 0;
 169         u32 cs_and_odt_mask;
 170
 171         if (odt_mode == RW_MGR_ODT_MODE_OFF) {
 172                 odt_mask_0 = 0x0;
 173                 odt_mask_1 = 0x0;
 174         } else {        /* RW_MGR_ODT_MODE_READ_WRITE */
 175                 switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
 176                 case 1: /* 1 Rank */
 177                         /* Read: ODT = 0 ; Write: ODT = 1 */
 178                         odt_mask_0 = 0x0;
 179                         odt_mask_1 = 0x1;
 180                         break;
 181                 case 2: /* 2 Ranks */
 182                         if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
 183                                 /*
 184                                  * - Dual-Slot , Single-Rank (1 CS per DIMM)
 185                                  *   OR
 186                                  * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
 187                                  *
 188                                  * Since MEM_NUMBER_OF_RANKS is 2, they
 189                                  * are both single rank with 2 CS each
 190                                  * (special for RDIMM).
 191                                  *
 192                                  * Read: Turn on ODT on the opposite rank
 193                                  * Write: Turn on ODT on all ranks
 194                                  */
 195                                 odt_mask_0 = 0x3 & ~(1 << rank);
 196                                 odt_mask_1 = 0x3;
 197                         } else {
 198                                 /*
 199                                  * - Single-Slot , Dual-Rank (2 CS per DIMM)
 200                                  *
 201                                  * Read: Turn on ODT off on all ranks
 202                                  * Write: Turn on ODT on active rank
 203                                  */
 204                                 odt_mask_0 = 0x0;
 205                                 odt_mask_1 = 0x3 & (1 << rank);
 206                         }
 207                         break;
 208                 case 4: /* 4 Ranks */
 209                         /* Read:
 210                          * ----------+-----------------------+
 211                          *           |         ODT           |
 212                          * Read From +-----------------------+
 213                          *   Rank    |  3  |  2  |  1  |  0  |
 214                          * ----------+-----+-----+-----+-----+
 215                          *     0     |  0  |  1  |  0  |  0  |
 216                          *     1     |  1  |  0  |  0  |  0  |
 217                          *     2     |  0  |  0  |  0  |  1  |
 218                          *     3     |  0  |  0  |  1  |  0  |
 219                          * ----------+-----+-----+-----+-----+
 220                          *
 221                          * Write:
 222                          * ----------+-----------------------+
 223                          *           |         ODT           |
 224                          * Write To  +-----------------------+
 225                          *   Rank    |  3  |  2  |  1  |  0  |
 226                          * ----------+-----+-----+-----+-----+
 227                          *     0     |  0  |  1  |  0  |  1  |
 228                          *     1     |  1  |  0  |  1  |  0  |
 229                          *     2     |  0  |  1  |  0  |  1  |
 230                          *     3     |  1  |  0  |  1  |  0  |
 231                          * ----------+-----+-----+-----+-----+
 232                          */
 233                         switch (rank) {
 234                         case 0:
 235                                 odt_mask_0 = 0x4;
 236                                 odt_mask_1 = 0x5;
 237                                 break;
 238                         case 1:
 239                                 odt_mask_0 = 0x8;
 240                                 odt_mask_1 = 0xA;
 241                                 break;
 242                         case 2:
 243                                 odt_mask_0 = 0x1;
 244                                 odt_mask_1 = 0x5;
 245                                 break;
 246                         case 3:
 247                                 odt_mask_0 = 0x2;
 248                                 odt_mask_1 = 0xA;
 249                                 break;
 250                         }
 251                         break;
 252                 }
 253         }
 254
 255         cs_and_odt_mask = (0xFF & ~(1 << rank)) |
 256                           ((0xFF & odt_mask_0) << 8) |
 257                           ((0xFF & odt_mask_1) << 16);
 258         writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 259                                 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
 260 }
 261
 262 /**
 263  * scc_mgr_set() - Set SCC Manager register
 264  * @off:        Base offset in SCC Manager space
 265  * @grp:        Read/Write group
 266  * @val:        Value to be set
 267  *
 268  * This function sets the SCC Manager (Scan Chain Control Manager) register.
 269  */
 270 static void scc_mgr_set(u32 off, u32 grp, u32 val)
 271 {
 272         writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
 273 }
 274
 275 /**
 276  * scc_mgr_initialize() - Initialize SCC Manager registers
 277  *
 278  * Initialize SCC Manager registers.
 279  */
 280 static void scc_mgr_initialize(void)
 281 {
 282         /*
 283          * Clear register file for HPS. 16 (2^4) is the size of the
 284          * full register file in the scc mgr:
 285          *      RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
 286          *                             MEM_IF_READ_DQS_WIDTH - 1);
 287          */
 288         int i;
 289
 290         for (i = 0; i < 16; i++) {
 291                 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
 292                            __func__, __LINE__, i);
 293                 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
 294         }
 295 }
 296
 297 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
 298 {
 299         scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
 300 }
 301
 302 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
 303 {
 304         scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
 305 }
 306
 307 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
 308 {
 309         scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
 310 }
 311
 312 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
 313 {
 314         scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
 315 }
 316
 317 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
 318 {
 319         scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
 320                     delay);
 321 }
 322
 323 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
 324 {
 325         scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
 326 }
 327
 328 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
 329 {
 330         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
 331 }
 332
 333 static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
 334 {
 335         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
 336                     delay);
 337 }
 338
 339 static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
 340 {
 341         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
 342                     RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
 343                     delay);
 344 }
 345
 346 /* load up dqs config settings */
 347 static void scc_mgr_load_dqs(uint32_t dqs)
 348 {
 349         writel(dqs, &sdr_scc_mgr->dqs_ena);
 350 }
 351
 352 /* load up dqs io config settings */
 353 static void scc_mgr_load_dqs_io(void)
 354 {
 355         writel(0, &sdr_scc_mgr->dqs_io_ena);
 356 }
 357
 358 /* load up dq config settings */
 359 static void scc_mgr_load_dq(uint32_t dq_in_group)
 360 {
 361         writel(dq_in_group, &sdr_scc_mgr->dq_ena);
 362 }
 363
 364 /* load up dm config settings */
 365 static void scc_mgr_load_dm(uint32_t dm)
 366 {
 367         writel(dm, &sdr_scc_mgr->dm_ena);
 368 }
 369
 370 /**
 371  * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
 372  * @off:        Base offset in SCC Manager space
 373  * @grp:        Read/Write group
 374  * @val:        Value to be set
 375  * @update:     If non-zero, trigger SCC Manager update for all ranks
 376  *
 377  * This function sets the SCC Manager (Scan Chain Control Manager) register
 378  * and optionally triggers the SCC update for all ranks.
 379  */
 380 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
 381                                   const int update)
 382 {
 383         u32 r;
 384
 385         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 386              r += NUM_RANKS_PER_SHADOW_REG) {
 387                 scc_mgr_set(off, grp, val);
 388
 389                 if (update || (r == 0)) {
 390                         writel(grp, &sdr_scc_mgr->dqs_ena);
 391                         writel(0, &sdr_scc_mgr->update);
 392                 }
 393         }
 394 }
 395
 396 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
 397 {
 398         /*
 399          * USER although the h/w doesn't support different phases per
 400          * shadow register, for simplicity our scc manager modeling
 401          * keeps different phase settings per shadow reg, and it's
 402          * important for us to keep them in sync to match h/w.
 403          * for efficiency, the scan chain update should occur only
 404          * once to sr0.
 405          */
 406         scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
 407                               read_group, phase, 0);
 408 }
 409
 410 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
 411                                                      uint32_t phase)
 412 {
 413         /*
 414          * USER although the h/w doesn't support different phases per
 415          * shadow register, for simplicity our scc manager modeling
 416          * keeps different phase settings per shadow reg, and it's
 417          * important for us to keep them in sync to match h/w.
 418          * for efficiency, the scan chain update should occur only
 419          * once to sr0.
 420          */
 421         scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
 422                               write_group, phase, 0);
 423 }
 424
 425 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
 426                                                uint32_t delay)
 427 {
 428         /*
 429          * In shadow register mode, the T11 settings are stored in
 430          * registers in the core, which are updated by the DQS_ENA
 431          * signals. Not issuing the SCC_MGR_UPD command allows us to
 432          * save lots of rank switching overhead, by calling
 433          * select_shadow_regs_for_update with update_scan_chains
 434          * set to 0.
 435          */
 436         scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
 437                               read_group, delay, 1);
 438         writel(0, &sdr_scc_mgr->update);
 439 }
 440
 441 /**
 442  * scc_mgr_set_oct_out1_delay() - Set OCT output delay
 443  * @write_group:        Write group
 444  * @delay:              Delay value
 445  *
 446  * This function sets the OCT output delay in SCC manager.
 447  */
 448 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
 449 {
 450         const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
 451                           RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
 452         const int base = write_group * ratio;
 453         int i;
 454         /*
 455          * Load the setting in the SCC manager
 456          * Although OCT affects only write data, the OCT delay is controlled
 457          * by the DQS logic block which is instantiated once per read group.
 458          * For protocols where a write group consists of multiple read groups,
 459          * the setting must be set multiple times.
 460          */
 461         for (i = 0; i < ratio; i++)
 462                 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
 463 }
 464
 465 /**
 466  * scc_mgr_set_hhp_extras() - Set HHP extras.
 467  *
 468  * Load the fixed setting in the SCC manager HHP extras.
 469  */
 470 static void scc_mgr_set_hhp_extras(void)
 471 {
 472         /*
 473          * Load the fixed setting in the SCC manager
 474          * bits: 0:0 = 1'b1     - DQS bypass
 475          * bits: 1:1 = 1'b1     - DQ bypass
 476          * bits: 4:2 = 3'b001   - rfifo_mode
 477          * bits: 6:5 = 2'b01    - rfifo clock_select
 478          * bits: 7:7 = 1'b0     - separate gating from ungating setting
 479          * bits: 8:8 = 1'b0     - separate OE from Output delay setting
 480          */
 481         const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
 482                           (1 << 2) | (1 << 1) | (1 << 0);
 483         const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
 484                          SCC_MGR_HHP_GLOBALS_OFFSET |
 485                          SCC_MGR_HHP_EXTRAS_OFFSET;
 486
 487         debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
 488                    __func__, __LINE__);
 489         writel(value, addr);
 490         debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
 491                    __func__, __LINE__);
 492 }
 493
 494 /**
 495  * scc_mgr_zero_all() - Zero all DQS config
 496  *
 497  * Zero all DQS config.
 498  */
 499 static void scc_mgr_zero_all(void)
 500 {
 501         int i, r;
 502
 503         /*
 504          * USER Zero all DQS config settings, across all groups and all
 505          * shadow registers
 506          */
 507         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 508              r += NUM_RANKS_PER_SHADOW_REG) {
 509                 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
 510                         /*
 511                          * The phases actually don't exist on a per-rank basis,
 512                          * but there's no harm updating them several times, so
 513                          * let's keep the code simple.
 514                          */
 515                         scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
 516                         scc_mgr_set_dqs_en_phase(i, 0);
 517                         scc_mgr_set_dqs_en_delay(i, 0);
 518                 }
 519
 520                 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
 521                         scc_mgr_set_dqdqs_output_phase(i, 0);
 522                         /* Arria V/Cyclone V don't have out2. */
 523                         scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
 524                 }
 525         }
 526
 527         /* Multicast to all DQS group enables. */
 528         writel(0xff, &sdr_scc_mgr->dqs_ena);
 529         writel(0, &sdr_scc_mgr->update);
 530 }
 531
 532 /**
 533  * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
 534  * @write_group:        Write group
 535  *
 536  * Set bypass mode and trigger SCC update.
 537  */
 538 static void scc_set_bypass_mode(const u32 write_group)
 539 {
 540         /* Multicast to all DQ enables. */
 541         writel(0xff, &sdr_scc_mgr->dq_ena);
 542         writel(0xff, &sdr_scc_mgr->dm_ena);
 543
 544         /* Update current DQS IO enable. */
 545         writel(0, &sdr_scc_mgr->dqs_io_ena);
 546
 547         /* Update the DQS logic. */
 548         writel(write_group, &sdr_scc_mgr->dqs_ena);
 549
 550         /* Hit update. */
 551         writel(0, &sdr_scc_mgr->update);
 552 }
 553
 554 /**
 555  * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
 556  * @write_group:        Write group
 557  *
 558  * Load DQS settings for Write Group, do not trigger SCC update.
 559  */
 560 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
 561 {
 562         const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
 563                           RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
 564         const int base = write_group * ratio;
 565         int i;
 566         /*
 567          * Load the setting in the SCC manager
 568          * Although OCT affects only write data, the OCT delay is controlled
 569          * by the DQS logic block which is instantiated once per read group.
 570          * For protocols where a write group consists of multiple read groups,
 571          * the setting must be set multiple times.
 572          */
 573         for (i = 0; i < ratio; i++)
 574                 writel(base + i, &sdr_scc_mgr->dqs_ena);
 575 }
 576
 577 /**
 578  * scc_mgr_zero_group() - Zero all configs for a group
 579  *
 580  * Zero DQ, DM, DQS and OCT configs for a group.
 581  */
 582 static void scc_mgr_zero_group(const u32 write_group, const int out_only)
 583 {
 584         int i, r;
 585
 586         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 587              r += NUM_RANKS_PER_SHADOW_REG) {
 588                 /* Zero all DQ config settings. */
 589                 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
 590                         scc_mgr_set_dq_out1_delay(i, 0);
 591                         if (!out_only)
 592                                 scc_mgr_set_dq_in_delay(i, 0);
 593                 }
 594
 595                 /* Multicast to all DQ enables. */
 596                 writel(0xff, &sdr_scc_mgr->dq_ena);
 597
 598                 /* Zero all DM config settings. */
 599                 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
 600                         scc_mgr_set_dm_out1_delay(i, 0);
 601
 602                 /* Multicast to all DM enables. */
 603                 writel(0xff, &sdr_scc_mgr->dm_ena);
 604
 605                 /* Zero all DQS IO settings. */
 606                 if (!out_only)
 607                         scc_mgr_set_dqs_io_in_delay(0);
 608
 609                 /* Arria V/Cyclone V don't have out2. */
 610                 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
 611                 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
 612                 scc_mgr_load_dqs_for_write_group(write_group);
 613
 614                 /* Multicast to all DQS IO enables (only 1 in total). */
 615                 writel(0, &sdr_scc_mgr->dqs_io_ena);
 616
 617                 /* Hit update to zero everything. */
 618                 writel(0, &sdr_scc_mgr->update);
 619         }
 620 }
 621
 622 /*
 623  * apply and load a particular input delay for the DQ pins in a group
 624  * group_bgn is the index of the first dq pin (in the write group)
 625  */
 626 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
 627 {
 628         uint32_t i, p;
 629
 630         for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
 631                 scc_mgr_set_dq_in_delay(p, delay);
 632                 scc_mgr_load_dq(p);
 633         }
 634 }
 635
 636 /**
 637  * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
 638  * @delay:              Delay value
 639  *
 640  * Apply and load a particular output delay for the DQ pins in a group.
 641  */
 642 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
 643 {
 644         int i;
 645
 646         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
 647                 scc_mgr_set_dq_out1_delay(i, delay);
 648                 scc_mgr_load_dq(i);
 649         }
 650 }
 651
 652 /* apply and load a particular output delay for the DM pins in a group */
 653 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
 654 {
 655         uint32_t i;
 656
 657         for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
 658                 scc_mgr_set_dm_out1_delay(i, delay1);
 659                 scc_mgr_load_dm(i);
 660         }
 661 }
 662
 663
 664 /* apply and load delay on both DQS and OCT out1 */
 665 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
 666                                                     uint32_t delay)
 667 {
 668         scc_mgr_set_dqs_out1_delay(delay);
 669         scc_mgr_load_dqs_io();
 670
 671         scc_mgr_set_oct_out1_delay(write_group, delay);
 672         scc_mgr_load_dqs_for_write_group(write_group);
 673 }
 674
 675 /**
 676  * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
 677  * @write_group:        Write group
 678  * @delay:              Delay value
 679  *
 680  * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
 681  */
 682 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
 683                                                   const u32 delay)
 684 {
 685         u32 i, new_delay;
 686
 687         /* DQ shift */
 688         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
 689                 scc_mgr_load_dq(i);
 690
 691         /* DM shift */
 692         for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
 693                 scc_mgr_load_dm(i);
 694
 695         /* DQS shift */
 696         new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
 697         if (new_delay > IO_IO_OUT2_DELAY_MAX) {
 698                 debug_cond(DLEVEL == 1,
 699                            "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
 700                            __func__, __LINE__, write_group, delay, new_delay,
 701                            IO_IO_OUT2_DELAY_MAX,
 702                            new_delay - IO_IO_OUT2_DELAY_MAX);
 703                 new_delay -= IO_IO_OUT2_DELAY_MAX;
 704                 scc_mgr_set_dqs_out1_delay(new_delay);
 705         }
 706
 707         scc_mgr_load_dqs_io();
 708
 709         /* OCT shift */
 710         new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
 711         if (new_delay > IO_IO_OUT2_DELAY_MAX) {
 712                 debug_cond(DLEVEL == 1,
 713                            "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
 714                            __func__, __LINE__, write_group, delay,
 715                            new_delay, IO_IO_OUT2_DELAY_MAX,
 716                            new_delay - IO_IO_OUT2_DELAY_MAX);
 717                 new_delay -= IO_IO_OUT2_DELAY_MAX;
 718                 scc_mgr_set_oct_out1_delay(write_group, new_delay);
 719         }
 720
 721         scc_mgr_load_dqs_for_write_group(write_group);
 722 }
 723
 724 /**
 725  * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
 726  * @write_group:        Write group
 727  * @delay:              Delay value
 728  *
 729  * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
 730  */
 731 static void
 732 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
 733                                                 const u32 delay)
 734 {
 735         int r;
 736
 737         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 738              r += NUM_RANKS_PER_SHADOW_REG) {
 739                 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
 740                 writel(0, &sdr_scc_mgr->update);
 741         }
 742 }
 743
 744 /**
 745  * set_jump_as_return() - Return instruction optimization
 746  *
 747  * Optimization used to recover some slots in ddr3 inst_rom could be
 748  * applied to other protocols if we wanted to
 749  */
 750 static void set_jump_as_return(void)
 751 {
 752         /*
 753          * To save space, we replace return with jump to special shared
 754          * RETURN instruction so we set the counter to large value so that
 755          * we always jump.
 756          */
 757         writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
 758         writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 759 }
 760
 761 /*
 762  * should always use constants as argument to ensure all computations are
 763  * performed at compile time
 764  */
 765 static void delay_for_n_mem_clocks(const uint32_t clocks)
 766 {
 767         uint32_t afi_clocks;
 768         uint8_t inner = 0;
 769         uint8_t outer = 0;
 770         uint16_t c_loop = 0;
 771
 772         debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
 773
 774
 775         afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
 776         /* scale (rounding up) to get afi clocks */
 777
 778         /*
 779          * Note, we don't bother accounting for being off a little bit
 780          * because of a few extra instructions in outer loops
 781          * Note, the loops have a test at the end, and do the test before
 782          * the decrement, and so always perform the loop
 783          * 1 time more than the counter value
 784          */
 785         if (afi_clocks == 0) {
 786                 ;
 787         } else if (afi_clocks <= 0x100) {
 788                 inner = afi_clocks-1;
 789                 outer = 0;
 790                 c_loop = 0;
 791         } else if (afi_clocks <= 0x10000) {
 792                 inner = 0xff;
 793                 outer = (afi_clocks-1) >> 8;
 794                 c_loop = 0;
 795         } else {
 796                 inner = 0xff;
 797                 outer = 0xff;
 798                 c_loop = (afi_clocks-1) >> 16;
 799         }
 800
 801         /*
 802          * rom instructions are structured as follows:
 803          *
 804          *    IDLE_LOOP2: jnz cntr0, TARGET_A
 805          *    IDLE_LOOP1: jnz cntr1, TARGET_B
 806          *                return
 807          *
 808          * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
 809          * TARGET_B is set to IDLE_LOOP2 as well
 810          *
 811          * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
 812          * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
 813          *
 814          * a little confusing, but it helps save precious space in the inst_rom
 815          * and sequencer rom and keeps the delays more accurate and reduces
 816          * overhead
 817          */
 818         if (afi_clocks <= 0x100) {
 819                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
 820                         &sdr_rw_load_mgr_regs->load_cntr1);
 821
 822                 writel(RW_MGR_IDLE_LOOP1,
 823                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 824
 825                 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 826                                           RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 827         } else {
 828                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
 829                         &sdr_rw_load_mgr_regs->load_cntr0);
 830
 831                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
 832                         &sdr_rw_load_mgr_regs->load_cntr1);
 833
 834                 writel(RW_MGR_IDLE_LOOP2,
 835                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 836
 837                 writel(RW_MGR_IDLE_LOOP2,
 838                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 839
 840                 /* hack to get around compiler not being smart enough */
 841                 if (afi_clocks <= 0x10000) {
 842                         /* only need to run once */
 843                         writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 844                                                   RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 845                 } else {
 846                         do {
 847                                 writel(RW_MGR_IDLE_LOOP2,
 848                                         SDR_PHYGRP_RWMGRGRP_ADDRESS |
 849                                         RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 850                         } while (c_loop-- != 0);
 851                 }
 852         }
 853         debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
 854 }
 855
 856 /**
 857  * rw_mgr_mem_init_load_regs() - Load instruction registers
 858  * @cntr0:      Counter 0 value
 859  * @cntr1:      Counter 1 value
 860  * @cntr2:      Counter 2 value
 861  * @jump:       Jump instruction value
 862  *
 863  * Load instruction registers.
 864  */
 865 static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
 866 {
 867         uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
 868                            RW_MGR_RUN_SINGLE_GROUP_OFFSET;
 869
 870         /* Load counters */
 871         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
 872                &sdr_rw_load_mgr_regs->load_cntr0);
 873         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
 874                &sdr_rw_load_mgr_regs->load_cntr1);
 875         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
 876                &sdr_rw_load_mgr_regs->load_cntr2);
 877
 878         /* Load jump address */
 879         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 880         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 881         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
 882
 883         /* Execute count instruction */
 884         writel(jump, grpaddr);
 885 }
 886
 887 /**
 888  * rw_mgr_mem_load_user() - Load user calibration values
 889  * @fin1:       Final instruction 1
 890  * @fin2:       Final instruction 2
 891  * @precharge:  If 1, precharge the banks at the end
 892  *
 893  * Load user calibration values and optionally precharge the banks.
 894  */
 895 static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
 896                                  const int precharge)
 897 {
 898         u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
 899                       RW_MGR_RUN_SINGLE_GROUP_OFFSET;
 900         u32 r;
 901
 902         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
 903                 if (param->skip_ranks[r]) {
 904                         /* request to skip the rank */
 905                         continue;
 906                 }
 907
 908                 /* set rank */
 909                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
 910
 911                 /* precharge all banks ... */
 912                 if (precharge)
 913                         writel(RW_MGR_PRECHARGE_ALL, grpaddr);
 914
 915                 /*
 916                  * USER Use Mirror-ed commands for odd ranks if address
 917                  * mirrorring is on
 918                  */
 919                 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
 920                         set_jump_as_return();
 921                         writel(RW_MGR_MRS2_MIRR, grpaddr);
 922                         delay_for_n_mem_clocks(4);
 923                         set_jump_as_return();
 924                         writel(RW_MGR_MRS3_MIRR, grpaddr);
 925                         delay_for_n_mem_clocks(4);
 926                         set_jump_as_return();
 927                         writel(RW_MGR_MRS1_MIRR, grpaddr);
 928                         delay_for_n_mem_clocks(4);
 929                         set_jump_as_return();
 930                         writel(fin1, grpaddr);
 931                 } else {
 932                         set_jump_as_return();
 933                         writel(RW_MGR_MRS2, grpaddr);
 934                         delay_for_n_mem_clocks(4);
 935                         set_jump_as_return();
 936                         writel(RW_MGR_MRS3, grpaddr);
 937                         delay_for_n_mem_clocks(4);
 938                         set_jump_as_return();
 939                         writel(RW_MGR_MRS1, grpaddr);
 940                         set_jump_as_return();
 941                         writel(fin2, grpaddr);
 942                 }
 943
 944                 if (precharge)
 945                         continue;
 946
 947                 set_jump_as_return();
 948                 writel(RW_MGR_ZQCL, grpaddr);
 949
 950                 /* tZQinit = tDLLK = 512 ck cycles */
 951                 delay_for_n_mem_clocks(512);
 952         }
 953 }
 954
 955 /**
 956  * rw_mgr_mem_initialize() - Initialize RW Manager
 957  *
 958  * Initialize RW Manager.
 959  */
 960 static void rw_mgr_mem_initialize(void)
 961 {
 962         debug("%s:%d\n", __func__, __LINE__);
 963
 964         /* The reset / cke part of initialization is broadcasted to all ranks */
 965         writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 966                                 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
 967
 968         /*
 969          * Here's how you load register for a loop
 970          * Counters are located @ 0x800
 971          * Jump address are located @ 0xC00
 972          * For both, registers 0 to 3 are selected using bits 3 and 2, like
 973          * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
 974          * I know this ain't pretty, but Avalon bus throws away the 2 least
 975          * significant bits
 976          */
 977
 978         /* Start with memory RESET activated */
 979
 980         /* tINIT = 200us */
 981
 982         /*
 983          * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
 984          * If a and b are the number of iteration in 2 nested loops
 985          * it takes the following number of cycles to complete the operation:
 986          * number_of_cycles = ((2 + n) * a + 2) * b
 987          * where n is the number of instruction in the inner loop
 988          * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
 989          * b = 6A
 990          */
 991         rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
 992                                   SEQ_TINIT_CNTR2_VAL,
 993                                   RW_MGR_INIT_RESET_0_CKE_0);
 994
 995         /* Indicate that memory is stable. */
 996         writel(1, &phy_mgr_cfg->reset_mem_stbl);
 997
 998         /*
 999          * transition the RESET to high
1000          * Wait for 500us
1001          */
1002
1003         /*
1004          * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
1005          * If a and b are the number of iteration in 2 nested loops
1006          * it takes the following number of cycles to complete the operation
1007          * number_of_cycles = ((2 + n) * a + 2) * b
1008          * where n is the number of instruction in the inner loop
1009          * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
1010          * b = FF
1011          */
1012         rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
1013                                   SEQ_TRESET_CNTR2_VAL,
1014                                   RW_MGR_INIT_RESET_1_CKE_0);
1015
1016         /* Bring up clock enable. */
1017
1018         /* tXRP < 250 ck cycles */
1019         delay_for_n_mem_clocks(250);
1020
1021         rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
1022                              0);
1023 }
1024
1025 /*
1026  * At the end of calibration we have to program the user settings in, and
1027  * USER  hand off the memory to the user.
1028  */
1029 static void rw_mgr_mem_handoff(void)
1030 {
1031         rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
1032         /*
1033          * USER  need to wait tMOD (12CK or 15ns) time before issuing
1034          * other commands, but we will have plenty of NIOS cycles before
1035          * actual handoff so its okay.
1036          */
1037 }
1038
1039 /**
1040  * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
1041  * @rank_bgn:   Rank number
1042  * @group:      Read/Write Group
1043  * @all_ranks:  Test all ranks
1044  *
1045  * Performs a guaranteed read on the patterns we are going to use during a
1046  * read test to ensure memory works.
1047  */
1048 static int
1049 rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
1050                                         const u32 all_ranks)
1051 {
1052         const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1053                          RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1054         const u32 addr_offset =
1055                          (group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS) << 2;
1056         const u32 rank_end = all_ranks ?
1057                                 RW_MGR_MEM_NUMBER_OF_RANKS :
1058                                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1059         const u32 shift_ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
1060                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1061         const u32 correct_mask_vg = param->read_correct_mask_vg;
1062
1063         u32 tmp_bit_chk, base_rw_mgr, bit_chk;
1064         int vg, r;
1065         int ret = 0;
1066
1067         bit_chk = param->read_correct_mask;
1068
1069         for (r = rank_bgn; r < rank_end; r++) {
1070                 /* Request to skip the rank */
1071                 if (param->skip_ranks[r])
1072                         continue;
1073
1074                 /* Set rank */
1075                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1076
1077                 /* Load up a constant bursts of read commands */
1078                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1079                 writel(RW_MGR_GUARANTEED_READ,
1080                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1081
1082                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1083                 writel(RW_MGR_GUARANTEED_READ_CONT,
1084                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1085
1086                 tmp_bit_chk = 0;
1087                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;
1088                      vg >= 0; vg--) {
1089                         /* Reset the FIFOs to get pointers to known state. */
1090                         writel(0, &phy_mgr_cmd->fifo_reset);
1091                         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1092                                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
1093                         writel(RW_MGR_GUARANTEED_READ,
1094                                addr + addr_offset + (vg << 2));
1095
1096                         base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1097                         tmp_bit_chk <<= shift_ratio;
1098                         tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr;
1099                 }
1100
1101                 bit_chk &= tmp_bit_chk;
1102         }
1103
1104         writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1105
1106         set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1107
1108         if (bit_chk != param->read_correct_mask)
1109                 ret = -EIO;
1110
1111         debug_cond(DLEVEL == 1,
1112                    "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
1113                    __func__, __LINE__, group, bit_chk,
1114                    param->read_correct_mask, ret);
1115
1116         return ret;
1117 }
1118
1119 /**
1120  * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
1121  * @rank_bgn:   Rank number
1122  * @all_ranks:  Test all ranks
1123  *
1124  * Load up the patterns we are going to use during a read test.
1125  */
1126 static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
1127                                                     const int all_ranks)
1128 {
1129         const u32 rank_end = all_ranks ?
1130                         RW_MGR_MEM_NUMBER_OF_RANKS :
1131                         (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1132         u32 r;
1133
1134         debug("%s:%d\n", __func__, __LINE__);
1135
1136         for (r = rank_bgn; r < rank_end; r++) {
1137                 if (param->skip_ranks[r])
1138                         /* request to skip the rank */
1139                         continue;
1140
1141                 /* set rank */
1142                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1143
1144                 /* Load up a constant bursts */
1145                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1146
1147                 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1148                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1149
1150                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1151
1152                 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1153                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1154
1155                 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1156
1157                 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1158                         &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1159
1160                 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1161
1162                 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1163                         &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1164
1165                 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1166                                                 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1167         }
1168
1169         set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1170 }
1171
1172 /*
1173  * try a read and see if it returns correct data back. has dummy reads
1174  * inserted into the mix used to align dqs enable. has more thorough checks
1175  * than the regular read test.
1176  */
1177 static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group,
1178         uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1179         uint32_t all_groups, uint32_t all_ranks)
1180 {
1181         uint32_t r, vg;
1182         uint32_t correct_mask_vg;
1183         uint32_t tmp_bit_chk;
1184         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1185                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1186         uint32_t addr;
1187         uint32_t base_rw_mgr;
1188
1189         *bit_chk = param->read_correct_mask;
1190         correct_mask_vg = param->read_correct_mask_vg;
1191
1192         uint32_t quick_read_mode = (((STATIC_CALIB_STEPS) &
1193                 CALIB_SKIP_DELAY_SWEEPS) && ENABLE_SUPER_QUICK_CALIBRATION);
1194
1195         for (r = rank_bgn; r < rank_end; r++) {
1196                 if (param->skip_ranks[r])
1197                         /* request to skip the rank */
1198                         continue;
1199
1200                 /* set rank */
1201                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1202
1203                 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1204
1205                 writel(RW_MGR_READ_B2B_WAIT1,
1206                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1207
1208                 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1209                 writel(RW_MGR_READ_B2B_WAIT2,
1210                         &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1211
1212                 if (quick_read_mode)
1213                         writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1214                         /* need at least two (1+1) reads to capture failures */
1215                 else if (all_groups)
1216                         writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1217                 else
1218                         writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1219
1220                 writel(RW_MGR_READ_B2B,
1221                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1222                 if (all_groups)
1223                         writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1224                                RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1225                                &sdr_rw_load_mgr_regs->load_cntr3);
1226                 else
1227                         writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1228
1229                 writel(RW_MGR_READ_B2B,
1230                         &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1231
1232                 tmp_bit_chk = 0;
1233                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1234                         /* reset the fifos to get pointers to known state */
1235                         writel(0, &phy_mgr_cmd->fifo_reset);
1236                         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1237                                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
1238
1239                         tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1240                                 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1241
1242                         if (all_groups)
1243                                 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
1244                         else
1245                                 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1246
1247                         writel(RW_MGR_READ_B2B, addr +
1248                                ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1249                                vg) << 2));
1250
1251                         base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1252                         tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
1253
1254                         if (vg == 0)
1255                                 break;
1256                 }
1257                 *bit_chk &= tmp_bit_chk;
1258         }
1259
1260         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1261         writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1262
1263         if (all_correct) {
1264                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1265                 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ALL,%u) =>\
1266                            (%u == %u) => %lu", __func__, __LINE__, group,
1267                            all_groups, *bit_chk, param->read_correct_mask,
1268                            (long unsigned int)(*bit_chk ==
1269                            param->read_correct_mask));
1270                 return *bit_chk == param->read_correct_mask;
1271         } else  {
1272                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1273                 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ONE,%u) =>\
1274                            (%u != %lu) => %lu\n", __func__, __LINE__,
1275                            group, all_groups, *bit_chk, (long unsigned int)0,
1276                            (long unsigned int)(*bit_chk != 0x00));
1277                 return *bit_chk != 0x00;
1278         }
1279 }
1280
1281 static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
1282         uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1283         uint32_t all_groups)
1284 {
1285         return rw_mgr_mem_calibrate_read_test(0, group, num_tries, all_correct,
1286                                               bit_chk, all_groups, 1);
1287 }
1288
1289 static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
1290 {
1291         writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1292         (*v)++;
1293 }
1294
1295 static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t *v)
1296 {
1297         uint32_t i;
1298
1299         for (i = 0; i < VFIFO_SIZE-1; i++)
1300                 rw_mgr_incr_vfifo(grp, v);
1301 }
1302
1303 static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
1304 {
1305         uint32_t  v;
1306         uint32_t fail_cnt = 0;
1307         uint32_t test_status;
1308
1309         for (v = 0; v < VFIFO_SIZE; ) {
1310                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
1311                            __func__, __LINE__, v);
1312                 test_status = rw_mgr_mem_calibrate_read_test_all_ranks
1313                         (grp, 1, PASS_ONE_BIT, bit_chk, 0);
1314                 if (!test_status) {
1315                         fail_cnt++;
1316
1317                         if (fail_cnt == 2)
1318                                 break;
1319                 }
1320
1321                 /* fiddle with FIFO */
1322                 rw_mgr_incr_vfifo(grp, &v);
1323         }
1324
1325         if (v >= VFIFO_SIZE) {
1326                 /* no failing read found!! Something must have gone wrong */
1327                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo failed\n",
1328                            __func__, __LINE__);
1329                 return 0;
1330         } else {
1331                 return v;
1332         }
1333 }
1334
1335 static int find_working_phase(uint32_t *grp, uint32_t *bit_chk,
1336                               uint32_t dtaps_per_ptap, uint32_t *work_bgn,
1337                               uint32_t *v, uint32_t *d, uint32_t *p,
1338                               uint32_t *i, uint32_t *max_working_cnt)
1339 {
1340         uint32_t found_begin = 0;
1341         uint32_t tmp_delay = 0;
1342         uint32_t test_status;
1343
1344         for (*d = 0; *d <= dtaps_per_ptap; (*d)++, tmp_delay +=
1345                 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1346                 *work_bgn = tmp_delay;
1347                 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1348
1349                 for (*i = 0; *i < VFIFO_SIZE; (*i)++) {
1350                         for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_bgn +=
1351                                 IO_DELAY_PER_OPA_TAP) {
1352                                 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1353
1354                                 test_status =
1355                                 rw_mgr_mem_calibrate_read_test_all_ranks
1356                                 (*grp, 1, PASS_ONE_BIT, bit_chk, 0);
1357
1358                                 if (test_status) {
1359                                         *max_working_cnt = 1;
1360                                         found_begin = 1;
1361                                         break;
1362                                 }
1363                         }
1364
1365                         if (found_begin)
1366                                 break;
1367
1368                         if (*p > IO_DQS_EN_PHASE_MAX)
1369                                 /* fiddle with FIFO */
1370                                 rw_mgr_incr_vfifo(*grp, v);
1371                 }
1372
1373                 if (found_begin)
1374                         break;
1375         }
1376
1377         if (*i >= VFIFO_SIZE) {
1378                 /* cannot find working solution */
1379                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/\
1380                            ptap/dtap\n", __func__, __LINE__);
1381                 return 0;
1382         } else {
1383                 return 1;
1384         }
1385 }
1386
1387 static void sdr_backup_phase(uint32_t *grp, uint32_t *bit_chk,
1388                              uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1389                              uint32_t *p, uint32_t *max_working_cnt)
1390 {
1391         uint32_t found_begin = 0;
1392         uint32_t tmp_delay;
1393
1394         /* Special case code for backing up a phase */
1395         if (*p == 0) {
1396                 *p = IO_DQS_EN_PHASE_MAX;
1397                 rw_mgr_decr_vfifo(*grp, v);
1398         } else {
1399                 (*p)--;
1400         }
1401         tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1402         scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1403
1404         for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn;
1405                 (*d)++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1406                 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1407
1408                 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1409                                                              PASS_ONE_BIT,
1410                                                              bit_chk, 0)) {
1411                         found_begin = 1;
1412                         *work_bgn = tmp_delay;
1413                         break;
1414                 }
1415         }
1416
1417         /* We have found a working dtap before the ptap found above */
1418         if (found_begin == 1)
1419                 (*max_working_cnt)++;
1420
1421         /*
1422          * Restore VFIFO to old state before we decremented it
1423          * (if needed).
1424          */
1425         (*p)++;
1426         if (*p > IO_DQS_EN_PHASE_MAX) {
1427                 *p = 0;
1428                 rw_mgr_incr_vfifo(*grp, v);
1429         }
1430
1431         scc_mgr_set_dqs_en_delay_all_ranks(*grp, 0);
1432 }
1433
1434 static int sdr_nonworking_phase(uint32_t *grp, uint32_t *bit_chk,
1435                              uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1436                              uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
1437                              uint32_t *work_end)
1438 {
1439         uint32_t found_end = 0;
1440
1441         (*p)++;
1442         *work_end += IO_DELAY_PER_OPA_TAP;
1443         if (*p > IO_DQS_EN_PHASE_MAX) {
1444                 /* fiddle with FIFO */
1445                 *p = 0;
1446                 rw_mgr_incr_vfifo(*grp, v);
1447         }
1448
1449         for (; *i < VFIFO_SIZE + 1; (*i)++) {
1450                 for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_end
1451                         += IO_DELAY_PER_OPA_TAP) {
1452                         scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1453
1454                         if (!rw_mgr_mem_calibrate_read_test_all_ranks
1455                                 (*grp, 1, PASS_ONE_BIT, bit_chk, 0)) {
1456                                 found_end = 1;
1457                                 break;
1458                         } else {
1459                                 (*max_working_cnt)++;
1460                         }
1461                 }
1462
1463                 if (found_end)
1464                         break;
1465
1466                 if (*p > IO_DQS_EN_PHASE_MAX) {
1467                         /* fiddle with FIFO */
1468                         rw_mgr_incr_vfifo(*grp, v);
1469                         *p = 0;
1470                 }
1471         }
1472
1473         if (*i >= VFIFO_SIZE + 1) {
1474                 /* cannot see edge of failing read */
1475                 debug_cond(DLEVEL == 2, "%s:%d sdr_nonworking_phase: end:\
1476                            failed\n", __func__, __LINE__);
1477                 return 0;
1478         } else {
1479                 return 1;
1480         }
1481 }
1482
1483 static int sdr_find_window_centre(uint32_t *grp, uint32_t *bit_chk,
1484                                   uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1485                                   uint32_t *p, uint32_t *work_mid,
1486                                   uint32_t *work_end)
1487 {
1488         int i;
1489         int tmp_delay = 0;
1490
1491         *work_mid = (*work_bgn + *work_end) / 2;
1492
1493         debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1494                    *work_bgn, *work_end, *work_mid);
1495         /* Get the middle delay to be less than a VFIFO delay */
1496         for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX;
1497                 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1498                 ;
1499         debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1500         while (*work_mid > tmp_delay)
1501                 *work_mid -= tmp_delay;
1502         debug_cond(DLEVEL == 2, "new work_mid %d\n", *work_mid);
1503
1504         tmp_delay = 0;
1505         for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX && tmp_delay < *work_mid;
1506                 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1507                 ;
1508         tmp_delay -= IO_DELAY_PER_OPA_TAP;
1509         debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", (*p) - 1, tmp_delay);
1510         for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_mid; (*d)++,
1511                 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP)
1512                 ;
1513         debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", *d, tmp_delay);
1514
1515         scc_mgr_set_dqs_en_phase_all_ranks(*grp, (*p) - 1);
1516         scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1517
1518         /*
1519          * push vfifo until we can successfully calibrate. We can do this
1520          * because the largest possible margin in 1 VFIFO cycle.
1521          */
1522         for (i = 0; i < VFIFO_SIZE; i++) {
1523                 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
1524                            *v);
1525                 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1526                                                              PASS_ONE_BIT,
1527                                                              bit_chk, 0)) {
1528                         break;
1529                 }
1530
1531                 /* fiddle with FIFO */
1532                 rw_mgr_incr_vfifo(*grp, v);
1533         }
1534
1535         if (i >= VFIFO_SIZE) {
1536                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center: \
1537                            failed\n", __func__, __LINE__);
1538                 return 0;
1539         } else {
1540                 return 1;
1541         }
1542 }
1543
1544 /* find a good dqs enable to use */
1545 static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
1546 {
1547         uint32_t v, d, p, i;
1548         uint32_t max_working_cnt;
1549         uint32_t bit_chk;
1550         uint32_t dtaps_per_ptap;
1551         uint32_t work_bgn, work_mid, work_end;
1552         uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
1553
1554         debug("%s:%d %u\n", __func__, __LINE__, grp);
1555
1556         reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1557
1558         scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1559         scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1560
1561         /* ************************************************************** */
1562         /* * Step 0 : Determine number of delay taps for each phase tap * */
1563         dtaps_per_ptap = IO_DELAY_PER_OPA_TAP/IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1564
1565         /* ********************************************************* */
1566         /* * Step 1 : First push vfifo until we get a failing read * */
1567         v = find_vfifo_read(grp, &bit_chk);
1568
1569         max_working_cnt = 0;
1570
1571         /* ******************************************************** */
1572         /* * step 2: find first working phase, increment in ptaps * */
1573         work_bgn = 0;
1574         if (find_working_phase(&grp, &bit_chk, dtaps_per_ptap, &work_bgn, &v, &d,
1575                                 &p, &i, &max_working_cnt) == 0)
1576                 return 0;
1577
1578         work_end = work_bgn;
1579
1580         /*
1581          * If d is 0 then the working window covers a phase tap and
1582          * we can follow the old procedure otherwise, we've found the beginning,
1583          * and we need to increment the dtaps until we find the end.
1584          */
1585         if (d == 0) {
1586                 /* ********************************************************* */
1587                 /* * step 3a: if we have room, back off by one and
1588                 increment in dtaps * */
1589
1590                 sdr_backup_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1591                                  &max_working_cnt);
1592
1593                 /* ********************************************************* */
1594                 /* * step 4a: go forward from working phase to non working
1595                 phase, increment in ptaps * */
1596                 if (sdr_nonworking_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1597                                          &i, &max_working_cnt, &work_end) == 0)
1598                         return 0;
1599
1600                 /* ********************************************************* */
1601                 /* * step 5a:  back off one from last, increment in dtaps  * */
1602
1603                 /* Special case code for backing up a phase */
1604                 if (p == 0) {
1605                         p = IO_DQS_EN_PHASE_MAX;
1606                         rw_mgr_decr_vfifo(grp, &v);
1607                 } else {
1608                         p = p - 1;
1609                 }
1610
1611                 work_end -= IO_DELAY_PER_OPA_TAP;
1612                 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1613
1614                 /* * The actual increment of dtaps is done outside of
1615                 the if/else loop to share code */
1616                 d = 0;
1617
1618                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p: \
1619                            vfifo=%u ptap=%u\n", __func__, __LINE__,
1620                            v, p);
1621         } else {
1622                 /* ******************************************************* */
1623                 /* * step 3-5b:  Find the right edge of the window using
1624                 delay taps   * */
1625                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase:vfifo=%u \
1626                            ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
1627                            v, p, d, work_bgn);
1628
1629                 work_end = work_bgn;
1630
1631                 /* * The actual increment of dtaps is done outside of the
1632                 if/else loop to share code */
1633
1634                 /* Only here to counterbalance a subtract later on which is
1635                 not needed if this branch of the algorithm is taken */
1636                 max_working_cnt++;
1637         }
1638
1639         /* The dtap increment to find the failing edge is done here */
1640         for (; d <= IO_DQS_EN_DELAY_MAX; d++, work_end +=
1641                 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1642                         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1643                                    end-2: dtap=%u\n", __func__, __LINE__, d);
1644                         scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1645
1646                         if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1647                                                                       PASS_ONE_BIT,
1648                                                                       &bit_chk, 0)) {
1649                                 break;
1650                         }
1651         }
1652
1653         /* Go back to working dtap */
1654         if (d != 0)
1655                 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1656
1657         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p/d: vfifo=%u \
1658                    ptap=%u dtap=%u end=%u\n", __func__, __LINE__,
1659                    v, p, d-1, work_end);
1660
1661         if (work_end < work_bgn) {
1662                 /* nil range */
1663                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: end-2: \
1664                            failed\n", __func__, __LINE__);
1665                 return 0;
1666         }
1667
1668         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: found range [%u,%u]\n",
1669                    __func__, __LINE__, work_bgn, work_end);
1670
1671         /* *************************************************************** */
1672         /*
1673          * * We need to calculate the number of dtaps that equal a ptap
1674          * * To do that we'll back up a ptap and re-find the edge of the
1675          * * window using dtaps
1676          */
1677
1678         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: calculate dtaps_per_ptap \
1679                    for tracking\n", __func__, __LINE__);
1680
1681         /* Special case code for backing up a phase */
1682         if (p == 0) {
1683                 p = IO_DQS_EN_PHASE_MAX;
1684                 rw_mgr_decr_vfifo(grp, &v);
1685                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1686                            cycle/phase: v=%u p=%u\n", __func__, __LINE__,
1687                            v, p);
1688         } else {
1689                 p = p - 1;
1690                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1691                            phase only: v=%u p=%u", __func__, __LINE__,
1692                            v, p);
1693         }
1694
1695         scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1696
1697         /*
1698          * Increase dtap until we first see a passing read (in case the
1699          * window is smaller than a ptap),
1700          * and then a failing read to mark the edge of the window again
1701          */
1702
1703         /* Find a passing read */
1704         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find passing read\n",
1705                    __func__, __LINE__);
1706         found_passing_read = 0;
1707         found_failing_read = 0;
1708         initial_failing_dtap = d;
1709         for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
1710                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: testing \
1711                            read d=%u\n", __func__, __LINE__, d);
1712                 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1713
1714                 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1715                                                              PASS_ONE_BIT,
1716                                                              &bit_chk, 0)) {
1717                         found_passing_read = 1;
1718                         break;
1719                 }
1720         }
1721
1722         if (found_passing_read) {
1723                 /* Find a failing read */
1724                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find failing \
1725                            read\n", __func__, __LINE__);
1726                 for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
1727                         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1728                                    testing read d=%u\n", __func__, __LINE__, d);
1729                         scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1730
1731                         if (!rw_mgr_mem_calibrate_read_test_all_ranks
1732                                 (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
1733                                 found_failing_read = 1;
1734                                 break;
1735                         }
1736                 }
1737         } else {
1738                 debug_cond(DLEVEL == 1, "%s:%d find_dqs_en_phase: failed to \
1739                            calculate dtaps", __func__, __LINE__);
1740                 debug_cond(DLEVEL == 1, "per ptap. Fall back on static value\n");
1741         }
1742
1743         /*
1744          * The dynamically calculated dtaps_per_ptap is only valid if we
1745          * found a passing/failing read. If we didn't, it means d hit the max
1746          * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1747          * statically calculated value.
1748          */
1749         if (found_passing_read && found_failing_read)
1750                 dtaps_per_ptap = d - initial_failing_dtap;
1751
1752         writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1753         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
1754                    - %u = %u",  __func__, __LINE__, d,
1755                    initial_failing_dtap, dtaps_per_ptap);
1756
1757         /* ******************************************** */
1758         /* * step 6:  Find the centre of the window   * */
1759         if (sdr_find_window_centre(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1760                                    &work_mid, &work_end) == 0)
1761                 return 0;
1762
1763         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center found: \
1764                    vfifo=%u ptap=%u dtap=%u\n", __func__, __LINE__,
1765                    v, p-1, d);
1766         return 1;
1767 }
1768
1769 /*
1770  * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
1771  * dq_in_delay values
1772  */
1773 static int
1774 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
1775 (uint32_t write_group, uint32_t read_group, uint32_t test_bgn)
1776 {
1777         /* We start at zero, so have one less dq to devide among */
1778         const u32 delay_step = IO_IO_IN_DELAY_MAX /
1779                                (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
1780         int found;
1781         u32 i, p, d, r;
1782
1783         debug("%s:%d (%u,%u,%u)\n", __func__, __LINE__,
1784               write_group, read_group, test_bgn);
1785
1786         /* Try different dq_in_delays since the DQ path is shorter than DQS. */
1787         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1788              r += NUM_RANKS_PER_SHADOW_REG) {
1789                 for (i = 0, p = test_bgn, d = 0;
1790                      i < RW_MGR_MEM_DQ_PER_READ_DQS;
1791                      i++, p++, d += delay_step) {
1792                         debug_cond(DLEVEL == 1,
1793                                    "%s:%d: g=%u/%u r=%u i=%u p=%u d=%u\n",
1794                                    __func__, __LINE__, write_group, read_group,
1795                                    r, i, p, d);
1796
1797                         scc_mgr_set_dq_in_delay(p, d);
1798                         scc_mgr_load_dq(p);
1799                 }
1800
1801                 writel(0, &sdr_scc_mgr->update);
1802         }
1803
1804         found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group);
1805
1806         debug_cond(DLEVEL == 1,
1807                    "%s:%d: g=%u/%u found=%u; Reseting delay chain to zero\n",
1808                    __func__, __LINE__, write_group, read_group, found);
1809
1810         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1811              r += NUM_RANKS_PER_SHADOW_REG) {
1812                 for (i = 0, p = test_bgn;
1813                      i < RW_MGR_MEM_DQ_PER_READ_DQS;
1814                      i++, p++) {
1815                         scc_mgr_set_dq_in_delay(p, 0);
1816                         scc_mgr_load_dq(p);
1817                 }
1818
1819                 writel(0, &sdr_scc_mgr->update);
1820         }
1821
1822         if (!found)
1823                 return -EINVAL;
1824
1825         return 0;
1826 }
1827
1828 /* per-bit deskew DQ and center */
1829 static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
1830         uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
1831         uint32_t use_read_test, uint32_t update_fom)
1832 {
1833         uint32_t i, p, d, min_index;
1834         /*
1835          * Store these as signed since there are comparisons with
1836          * signed numbers.
1837          */
1838         uint32_t bit_chk;
1839         uint32_t sticky_bit_chk;
1840         int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1841         int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1842         int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
1843         int32_t mid;
1844         int32_t orig_mid_min, mid_min;
1845         int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
1846                 final_dqs_en;
1847         int32_t dq_margin, dqs_margin;
1848         uint32_t stop;
1849         uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
1850         uint32_t addr;
1851
1852         debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
1853
1854         addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
1855         start_dqs = readl(addr + (read_group << 2));
1856         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
1857                 start_dqs_en = readl(addr + ((read_group << 2)
1858                                      - IO_DQS_EN_DELAY_OFFSET));
1859
1860         /* set the left and right edge of each bit to an illegal value */
1861         /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1862         sticky_bit_chk = 0;
1863         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1864                 left_edge[i]  = IO_IO_IN_DELAY_MAX + 1;
1865                 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1866         }
1867
1868         /* Search for the left edge of the window for each bit */
1869         for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
1870                 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
1871
1872                 writel(0, &sdr_scc_mgr->update);
1873
1874                 /*
1875                  * Stop searching when the read test doesn't pass AND when
1876                  * we've seen a passing read on every bit.
1877                  */
1878                 if (use_read_test) {
1879                         stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1880                                 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1881                                 &bit_chk, 0, 0);
1882                 } else {
1883                         rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1884                                                         0, PASS_ONE_BIT,
1885                                                         &bit_chk, 0);
1886                         bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1887                                 (read_group - (write_group *
1888                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
1889                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1890                         stop = (bit_chk == 0);
1891                 }
1892                 sticky_bit_chk = sticky_bit_chk | bit_chk;
1893                 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1894                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1895                            && %u", __func__, __LINE__, d,
1896                            sticky_bit_chk,
1897                         param->read_correct_mask, stop);
1898
1899                 if (stop == 1) {
1900                         break;
1901                 } else {
1902                         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1903                                 if (bit_chk & 1) {
1904                                         /* Remember a passing test as the
1905                                         left_edge */
1906                                         left_edge[i] = d;
1907                                 } else {
1908                                         /* If a left edge has not been seen yet,
1909                                         then a future passing test will mark
1910                                         this edge as the right edge */
1911                                         if (left_edge[i] ==
1912                                                 IO_IO_IN_DELAY_MAX + 1) {
1913                                                 right_edge[i] = -(d + 1);
1914                                         }
1915                                 }
1916                                 bit_chk = bit_chk >> 1;
1917                         }
1918                 }
1919         }
1920
1921         /* Reset DQ delay chains to 0 */
1922         scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
1923         sticky_bit_chk = 0;
1924         for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
1925                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1926                            %d right_edge[%u]: %d\n", __func__, __LINE__,
1927                            i, left_edge[i], i, right_edge[i]);
1928
1929                 /*
1930                  * Check for cases where we haven't found the left edge,
1931                  * which makes our assignment of the the right edge invalid.
1932                  * Reset it to the illegal value.
1933                  */
1934                 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
1935                         right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1936                         right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1937                         debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
1938                                    right_edge[%u]: %d\n", __func__, __LINE__,
1939                                    i, right_edge[i]);
1940                 }
1941
1942                 /*
1943                  * Reset sticky bit (except for bits where we have seen
1944                  * both the left and right edge).
1945                  */
1946                 sticky_bit_chk = sticky_bit_chk << 1;
1947                 if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
1948                     (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1949                         sticky_bit_chk = sticky_bit_chk | 1;
1950                 }
1951
1952                 if (i == 0)
1953                         break;
1954         }
1955
1956         /* Search for the right edge of the window for each bit */
1957         for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
1958                 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1959                 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1960                         uint32_t delay = d + start_dqs_en;
1961                         if (delay > IO_DQS_EN_DELAY_MAX)
1962                                 delay = IO_DQS_EN_DELAY_MAX;
1963                         scc_mgr_set_dqs_en_delay(read_group, delay);
1964                 }
1965                 scc_mgr_load_dqs(read_group);
1966
1967                 writel(0, &sdr_scc_mgr->update);
1968
1969                 /*
1970                  * Stop searching when the read test doesn't pass AND when
1971                  * we've seen a passing read on every bit.
1972                  */
1973                 if (use_read_test) {
1974                         stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1975                                 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1976                                 &bit_chk, 0, 0);
1977                 } else {
1978                         rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1979                                                         0, PASS_ONE_BIT,
1980                                                         &bit_chk, 0);
1981                         bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1982                                 (read_group - (write_group *
1983                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
1984                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1985                         stop = (bit_chk == 0);
1986                 }
1987                 sticky_bit_chk = sticky_bit_chk | bit_chk;
1988                 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1989
1990                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
1991                            %u && %u", __func__, __LINE__, d,
1992                            sticky_bit_chk, param->read_correct_mask, stop);
1993
1994                 if (stop == 1) {
1995                         break;
1996                 } else {
1997                         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1998                                 if (bit_chk & 1) {
1999                                         /* Remember a passing test as
2000                                         the right_edge */
2001                                         right_edge[i] = d;
2002                                 } else {
2003                                         if (d != 0) {
2004                                                 /* If a right edge has not been
2005                                                 seen yet, then a future passing
2006                                                 test will mark this edge as the
2007                                                 left edge */
2008                                                 if (right_edge[i] ==
2009                                                 IO_IO_IN_DELAY_MAX + 1) {
2010                                                         left_edge[i] = -(d + 1);
2011                                                 }
2012                                         } else {
2013                                                 /* d = 0 failed, but it passed
2014                                                 when testing the left edge,
2015                                                 so it must be marginal,
2016                                                 set it to -1 */
2017                                                 if (right_edge[i] ==
2018                                                         IO_IO_IN_DELAY_MAX + 1 &&
2019                                                         left_edge[i] !=
2020                                                         IO_IO_IN_DELAY_MAX
2021                                                         + 1) {
2022                                                         right_edge[i] = -1;
2023                                                 }
2024                                                 /* If a right edge has not been
2025                                                 seen yet, then a future passing
2026                                                 test will mark this edge as the
2027                                                 left edge */
2028                                                 else if (right_edge[i] ==
2029                                                         IO_IO_IN_DELAY_MAX +
2030                                                         1) {
2031                                                         left_edge[i] = -(d + 1);
2032                                                 }
2033                                         }
2034                                 }
2035
2036                                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
2037                                            d=%u]: ", __func__, __LINE__, d);
2038                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
2039                                            (int)(bit_chk & 1), i, left_edge[i]);
2040                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2041                                            right_edge[i]);
2042                                 bit_chk = bit_chk >> 1;
2043                         }
2044                 }
2045         }
2046
2047         /* Check that all bits have a window */
2048         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2049                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
2050                            %d right_edge[%u]: %d", __func__, __LINE__,
2051                            i, left_edge[i], i, right_edge[i]);
2052                 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
2053                         == IO_IO_IN_DELAY_MAX + 1)) {
2054                         /*
2055                          * Restore delay chain settings before letting the loop
2056                          * in rw_mgr_mem_calibrate_vfifo to retry different
2057                          * dqs/ck relationships.
2058                          */
2059                         scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
2060                         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2061                                 scc_mgr_set_dqs_en_delay(read_group,
2062                                                          start_dqs_en);
2063                         }
2064                         scc_mgr_load_dqs(read_group);
2065                         writel(0, &sdr_scc_mgr->update);
2066
2067                         debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
2068                                    find edge [%u]: %d %d", __func__, __LINE__,
2069                                    i, left_edge[i], right_edge[i]);
2070                         if (use_read_test) {
2071                                 set_failing_group_stage(read_group *
2072                                         RW_MGR_MEM_DQ_PER_READ_DQS + i,
2073                                         CAL_STAGE_VFIFO,
2074                                         CAL_SUBSTAGE_VFIFO_CENTER);
2075                         } else {
2076                                 set_failing_group_stage(read_group *
2077                                         RW_MGR_MEM_DQ_PER_READ_DQS + i,
2078                                         CAL_STAGE_VFIFO_AFTER_WRITES,
2079                                         CAL_SUBSTAGE_VFIFO_CENTER);
2080                         }
2081                         return 0;
2082                 }
2083         }
2084
2085         /* Find middle of window for each DQ bit */
2086         mid_min = left_edge[0] - right_edge[0];
2087         min_index = 0;
2088         for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2089                 mid = left_edge[i] - right_edge[i];
2090                 if (mid < mid_min) {
2091                         mid_min = mid;
2092                         min_index = i;
2093                 }
2094         }
2095
2096         /*
2097          * -mid_min/2 represents the amount that we need to move DQS.
2098          * If mid_min is odd and positive we'll need to add one to
2099          * make sure the rounding in further calculations is correct
2100          * (always bias to the right), so just add 1 for all positive values.
2101          */
2102         if (mid_min > 0)
2103                 mid_min++;
2104
2105         mid_min = mid_min / 2;
2106
2107         debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2108                    __func__, __LINE__, mid_min, min_index);
2109
2110         /* Determine the amount we can change DQS (which is -mid_min) */
2111         orig_mid_min = mid_min;
2112         new_dqs = start_dqs - mid_min;
2113         if (new_dqs > IO_DQS_IN_DELAY_MAX)
2114                 new_dqs = IO_DQS_IN_DELAY_MAX;
2115         else if (new_dqs < 0)
2116                 new_dqs = 0;
2117
2118         mid_min = start_dqs - new_dqs;
2119         debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2120                    mid_min, new_dqs);
2121
2122         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2123                 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2124                         mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2125                 else if (start_dqs_en - mid_min < 0)
2126                         mid_min += start_dqs_en - mid_min;
2127         }
2128         new_dqs = start_dqs - mid_min;
2129
2130         debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2131                    new_dqs=%d mid_min=%d\n", start_dqs,
2132                    IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2133                    new_dqs, mid_min);
2134
2135         /* Initialize data for export structures */
2136         dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2137         dq_margin  = IO_IO_IN_DELAY_MAX + 1;
2138
2139         /* add delay to bring centre of all DQ windows to the same "level" */
2140         for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2141                 /* Use values before divide by 2 to reduce round off error */
2142                 shift_dq = (left_edge[i] - right_edge[i] -
2143                         (left_edge[min_index] - right_edge[min_index]))/2  +
2144                         (orig_mid_min - mid_min);
2145
2146                 debug_cond(DLEVEL == 2, "vfifo_center: before: \
2147                            shift_dq[%u]=%d\n", i, shift_dq);
2148
2149                 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
2150                 temp_dq_in_delay1 = readl(addr + (p << 2));
2151                 temp_dq_in_delay2 = readl(addr + (i << 2));
2152
2153                 if (shift_dq + (int32_t)temp_dq_in_delay1 >
2154                         (int32_t)IO_IO_IN_DELAY_MAX) {
2155                         shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2156                 } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
2157                         shift_dq = -(int32_t)temp_dq_in_delay1;
2158                 }
2159                 debug_cond(DLEVEL == 2, "vfifo_center: after: \
2160                            shift_dq[%u]=%d\n", i, shift_dq);
2161                 final_dq[i] = temp_dq_in_delay1 + shift_dq;
2162                 scc_mgr_set_dq_in_delay(p, final_dq[i]);
2163                 scc_mgr_load_dq(p);
2164
2165                 debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
2166                            left_edge[i] - shift_dq + (-mid_min),
2167                            right_edge[i] + shift_dq - (-mid_min));
2168                 /* To determine values for export structures */
2169                 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2170                         dq_margin = left_edge[i] - shift_dq + (-mid_min);
2171
2172                 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2173                         dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2174         }
2175
2176         final_dqs = new_dqs;
2177         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2178                 final_dqs_en = start_dqs_en - mid_min;
2179
2180         /* Move DQS-en */
2181         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2182                 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2183                 scc_mgr_load_dqs(read_group);
2184         }
2185
2186         /* Move DQS */
2187         scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2188         scc_mgr_load_dqs(read_group);
2189         debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
2190                    dqs_margin=%d", __func__, __LINE__,
2191                    dq_margin, dqs_margin);
2192
2193         /*
2194          * Do not remove this line as it makes sure all of our decisions
2195          * have been applied. Apply the update bit.
2196          */
2197         writel(0, &sdr_scc_mgr->update);
2198
2199         return (dq_margin >= 0) && (dqs_margin >= 0);
2200 }
2201
2202 /**
2203  * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
2204  * @rw_group:   Read/Write Group
2205  * @phase:      DQ/DQS phase
2206  *
2207  * Because initially no communication ca be reliably performed with the memory
2208  * device, the sequencer uses a guaranteed write mechanism to write data into
2209  * the memory device.
2210  */
2211 static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
2212                                                  const u32 phase)
2213 {
2214         int ret;
2215
2216         /* Set a particular DQ/DQS phase. */
2217         scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
2218
2219         debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
2220                    __func__, __LINE__, rw_group, phase);
2221
2222         /*
2223          * Altera EMI_RM 2015.05.04 :: Figure 1-25
2224          * Load up the patterns used by read calibration using the
2225          * current DQDQS phase.
2226          */
2227         rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2228
2229         if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
2230                 return 0;
2231
2232         /*
2233          * Altera EMI_RM 2015.05.04 :: Figure 1-26
2234          * Back-to-Back reads of the patterns used for calibration.
2235          */
2236         ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
2237         if (ret)
2238                 debug_cond(DLEVEL == 1,
2239                            "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2240                            __func__, __LINE__, rw_group, phase);
2241         return ret;
2242 }
2243
2244 /**
2245  * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2246  * @rw_group:   Read/Write Group
2247  * @test_bgn:   Rank at which the test begins
2248  *
2249  * DQS enable calibration ensures reliable capture of the DQ signal without
2250  * glitches on the DQS line.
2251  */
2252 static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
2253                                                        const u32 test_bgn)
2254 {
2255         int ret;
2256
2257         /*
2258          * Altera EMI_RM 2015.05.04 :: Figure 1-27
2259          * DQS and DQS Eanble Signal Relationships.
2260          */
2261         ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay(
2262                                                 rw_group, rw_group, test_bgn);
2263         return ret;
2264 }
2265
2266 /**
2267  * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
2268  * @rw_group:           Read/Write Group
2269  * @test_bgn:           Rank at which the test begins
2270  * @use_read_test:      Perform a read test
2271  * @update_fom:         Update FOM
2272  *
2273  * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
2274  * within a group.
2275  */
2276 static int
2277 rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
2278                                       const int use_read_test,
2279                                       const int update_fom)
2280
2281 {
2282         int ret, grp_calibrated;
2283         u32 rank_bgn, sr;
2284
2285         /*
2286          * Altera EMI_RM 2015.05.04 :: Figure 1-28
2287          * Read per-bit deskew can be done on a per shadow register basis.
2288          */
2289         grp_calibrated = 1;
2290         for (rank_bgn = 0, sr = 0;
2291              rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2292              rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
2293                 /* Check if this set of ranks should be skipped entirely. */
2294                 if (param->skip_shadow_regs[sr])
2295                         continue;
2296
2297                 ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
2298                                                         rw_group, test_bgn,
2299                                                         use_read_test,
2300                                                         update_fom);
2301                 if (ret)
2302                         continue;
2303
2304                 grp_calibrated = 0;
2305         }
2306
2307         if (!grp_calibrated)
2308                 return -EIO;
2309
2310         return 0;
2311 }
2312
2313 /**
2314  * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2315  * @rw_group:           Read/Write Group
2316  * @test_bgn:           Rank at which the test begins
2317  *
2318  * Stage 1: Calibrate the read valid prediction FIFO.
2319  *
2320  * This function implements UniPHY calibration Stage 1, as explained in
2321  * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2322  *
2323  * - read valid prediction will consist of finding:
2324  *   - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2325  *   - DQS input phase  and DQS input delay (DQ/DQS Centering)
2326  *  - we also do a per-bit deskew on the DQ lines.
2327  */
2328 static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
2329 {
2330         uint32_t p, d;
2331         uint32_t dtaps_per_ptap;
2332         uint32_t failed_substage;
2333
2334         int ret;
2335
2336         debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
2337
2338         /* Update info for sims */
2339         reg_file_set_group(rw_group);
2340         reg_file_set_stage(CAL_STAGE_VFIFO);
2341         reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2342
2343         failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2344
2345         /* USER Determine number of delay taps for each phase tap. */
2346         dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
2347                                       IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
2348
2349         for (d = 0; d <= dtaps_per_ptap; d += 2) {
2350                 /*
2351                  * In RLDRAMX we may be messing the delay of pins in
2352                  * the same write rw_group but outside of the current read
2353                  * the rw_group, but that's ok because we haven't calibrated
2354                  * output side yet.
2355                  */
2356                 if (d > 0) {
2357                         scc_mgr_apply_group_all_out_delay_add_all_ranks(
2358                                                                 rw_group, d);
2359                 }
2360
2361                 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
2362                         /* 1) Guaranteed Write */
2363                         ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
2364                         if (ret)
2365                                 break;
2366
2367                         /* 2) DQS Enable Calibration */
2368                         ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
2369                                                                           test_bgn);
2370                         if (ret) {
2371                                 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2372                                 continue;
2373                         }
2374
2375                         /* 3) Centering DQ/DQS */
2376                         /*
2377                          * If doing read after write calibration, do not update
2378                          * FOM now. Do it then.
2379                          */
2380                         ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group,
2381                                                                 test_bgn, 1, 0);
2382                         if (ret) {
2383                                 failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
2384                                 continue;
2385                         }
2386
2387                         /* All done. */
2388                         goto cal_done_ok;
2389                 }
2390         }
2391
2392         /* Calibration Stage 1 failed. */
2393         set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
2394         return 0;
2395
2396         /* Calibration Stage 1 completed OK. */
2397 cal_done_ok:
2398         /*
2399          * Reset the delay chains back to zero if they have moved > 1
2400          * (check for > 1 because loop will increase d even when pass in
2401          * first case).
2402          */
2403         if (d > 2)
2404                 scc_mgr_zero_group(rw_group, 1);
2405
2406         return 1;
2407 }
2408
2409 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2410 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2411                                                uint32_t test_bgn)
2412 {
2413         uint32_t rank_bgn, sr;
2414         uint32_t grp_calibrated;
2415         uint32_t write_group;
2416
2417         debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2418
2419         /* update info for sims */
2420
2421         reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2422         reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2423
2424         write_group = read_group;
2425
2426         /* update info for sims */
2427         reg_file_set_group(read_group);
2428
2429         grp_calibrated = 1;
2430         /* Read per-bit deskew can be done on a per shadow register basis */
2431         for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2432                 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2433                 /* Determine if this set of ranks should be skipped entirely */
2434                 if (!param->skip_shadow_regs[sr]) {
2435                 /* This is the last calibration round, update FOM here */
2436                         if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2437                                                                 write_group,
2438                                                                 read_group,
2439                                                                 test_bgn, 0,
2440                                                                 1)) {
2441                                 grp_calibrated = 0;
2442                         }
2443                 }
2444         }
2445
2446
2447         if (grp_calibrated == 0) {
2448                 set_failing_group_stage(write_group,
2449                                         CAL_STAGE_VFIFO_AFTER_WRITES,
2450                                         CAL_SUBSTAGE_VFIFO_CENTER);
2451                 return 0;
2452         }
2453
2454         return 1;
2455 }
2456
2457 /* Calibrate LFIFO to find smallest read latency */
2458 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2459 {
2460         uint32_t found_one;
2461         uint32_t bit_chk;
2462
2463         debug("%s:%d\n", __func__, __LINE__);
2464
2465         /* update info for sims */
2466         reg_file_set_stage(CAL_STAGE_LFIFO);
2467         reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2468
2469         /* Load up the patterns used by read calibration for all ranks */
2470         rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2471         found_one = 0;
2472
2473         do {
2474                 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2475                 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2476                            __func__, __LINE__, gbl->curr_read_lat);
2477
2478                 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2479                                                               NUM_READ_TESTS,
2480                                                               PASS_ALL_BITS,
2481                                                               &bit_chk, 1)) {
2482                         break;
2483                 }
2484
2485                 found_one = 1;
2486                 /* reduce read latency and see if things are working */
2487                 /* correctly */
2488                 gbl->curr_read_lat--;
2489         } while (gbl->curr_read_lat > 0);
2490
2491         /* reset the fifos to get pointers to known state */
2492
2493         writel(0, &phy_mgr_cmd->fifo_reset);
2494
2495         if (found_one) {
2496                 /* add a fudge factor to the read latency that was determined */
2497                 gbl->curr_read_lat += 2;
2498                 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2499                 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2500                            read_lat=%u\n", __func__, __LINE__,
2501                            gbl->curr_read_lat);
2502                 return 1;
2503         } else {
2504                 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2505                                         CAL_SUBSTAGE_READ_LATENCY);
2506
2507                 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2508                            read_lat=%u\n", __func__, __LINE__,
2509                            gbl->curr_read_lat);
2510                 return 0;
2511         }
2512 }
2513
2514 /*
2515  * issue write test command.
2516  * two variants are provided. one that just tests a write pattern and
2517  * another that tests datamask functionality.
2518  */
2519 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2520                                                   uint32_t test_dm)
2521 {
2522         uint32_t mcc_instruction;
2523         uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2524                 ENABLE_SUPER_QUICK_CALIBRATION);
2525         uint32_t rw_wl_nop_cycles;
2526         uint32_t addr;
2527
2528         /*
2529          * Set counter and jump addresses for the right
2530          * number of NOP cycles.
2531          * The number of supported NOP cycles can range from -1 to infinity
2532          * Three different cases are handled:
2533          *
2534          * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2535          *    mechanism will be used to insert the right number of NOPs
2536          *
2537          * 2. For a number of NOP cycles equals to 0, the micro-instruction
2538          *    issuing the write command will jump straight to the
2539          *    micro-instruction that turns on DQS (for DDRx), or outputs write
2540          *    data (for RLD), skipping
2541          *    the NOP micro-instruction all together
2542          *
2543          * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2544          *    turned on in the same micro-instruction that issues the write
2545          *    command. Then we need
2546          *    to directly jump to the micro-instruction that sends out the data
2547          *
2548          * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2549          *       (2 and 3). One jump-counter (0) is used to perform multiple
2550          *       write-read operations.
2551          *       one counter left to issue this command in "multiple-group" mode
2552          */
2553
2554         rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2555
2556         if (rw_wl_nop_cycles == -1) {
2557                 /*
2558                  * CNTR 2 - We want to execute the special write operation that
2559                  * turns on DQS right away and then skip directly to the
2560                  * instruction that sends out the data. We set the counter to a
2561                  * large number so that the jump is always taken.
2562                  */
2563                 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2564
2565                 /* CNTR 3 - Not used */
2566                 if (test_dm) {
2567                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
2568                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
2569                                &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2570                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2571                                &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2572                 } else {
2573                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
2574                         writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2575                                 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2576                         writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2577                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2578                 }
2579         } else if (rw_wl_nop_cycles == 0) {
2580                 /*
2581                  * CNTR 2 - We want to skip the NOP operation and go straight
2582                  * to the DQS enable instruction. We set the counter to a large
2583                  * number so that the jump is always taken.
2584                  */
2585                 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2586
2587                 /* CNTR 3 - Not used */
2588                 if (test_dm) {
2589                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2590                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
2591                                &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2592                 } else {
2593                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2594                         writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2595                                 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2596                 }
2597         } else {
2598                 /*
2599                  * CNTR 2 - In this case we want to execute the next instruction
2600                  * and NOT take the jump. So we set the counter to 0. The jump
2601                  * address doesn't count.
2602                  */
2603                 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2604                 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2605
2606                 /*
2607                  * CNTR 3 - Set the nop counter to the number of cycles we
2608                  * need to loop for, minus 1.
2609                  */
2610                 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
2611                 if (test_dm) {
2612                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2613                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2614                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2615                 } else {
2616                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2617                         writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2618                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2619                 }
2620         }
2621
2622         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2623                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
2624
2625         if (quick_write_mode)
2626                 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
2627         else
2628                 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
2629
2630         writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
2631
2632         /*
2633          * CNTR 1 - This is used to ensure enough time elapses
2634          * for read data to come back.
2635          */
2636         writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
2637
2638         if (test_dm) {
2639                 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2640                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2641         } else {
2642                 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2643                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2644         }
2645
2646         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
2647         writel(mcc_instruction, addr + (group << 2));
2648 }
2649
2650 /* Test writes, can check for a single bit pass or multiple bit pass */
2651 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2652         uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2653         uint32_t *bit_chk, uint32_t all_ranks)
2654 {
2655         uint32_t r;
2656         uint32_t correct_mask_vg;
2657         uint32_t tmp_bit_chk;
2658         uint32_t vg;
2659         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2660                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2661         uint32_t addr_rw_mgr;
2662         uint32_t base_rw_mgr;
2663
2664         *bit_chk = param->write_correct_mask;
2665         correct_mask_vg = param->write_correct_mask_vg;
2666
2667         for (r = rank_bgn; r < rank_end; r++) {
2668                 if (param->skip_ranks[r]) {
2669                         /* request to skip the rank */
2670                         continue;
2671                 }
2672
2673                 /* set rank */
2674                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2675
2676                 tmp_bit_chk = 0;
2677                 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
2678                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2679                         /* reset the fifos to get pointers to known state */
2680                         writel(0, &phy_mgr_cmd->fifo_reset);
2681
2682                         tmp_bit_chk = tmp_bit_chk <<
2683                                 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2684                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2685                         rw_mgr_mem_calibrate_write_test_issue(write_group *
2686                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2687                                 use_dm);
2688
2689                         base_rw_mgr = readl(addr_rw_mgr);
2690                         tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2691                         if (vg == 0)
2692                                 break;
2693                 }
2694                 *bit_chk &= tmp_bit_chk;
2695         }
2696
2697         if (all_correct) {
2698                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2699                 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2700                            %u => %lu", write_group, use_dm,
2701                            *bit_chk, param->write_correct_mask,
2702                            (long unsigned int)(*bit_chk ==
2703                            param->write_correct_mask));
2704                 return *bit_chk == param->write_correct_mask;
2705         } else {
2706                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2707                 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2708                        write_group, use_dm, *bit_chk);
2709                 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2710                         (long unsigned int)(*bit_chk != 0));
2711                 return *bit_chk != 0x00;
2712         }
2713 }
2714
2715 /*
2716  * center all windows. do per-bit-deskew to possibly increase size of
2717  * certain windows.
2718  */
2719 static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2720         uint32_t write_group, uint32_t test_bgn)
2721 {
2722         uint32_t i, p, min_index;
2723         int32_t d;
2724         /*
2725          * Store these as signed since there are comparisons with
2726          * signed numbers.
2727          */
2728         uint32_t bit_chk;
2729         uint32_t sticky_bit_chk;
2730         int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2731         int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2732         int32_t mid;
2733         int32_t mid_min, orig_mid_min;
2734         int32_t new_dqs, start_dqs, shift_dq;
2735         int32_t dq_margin, dqs_margin, dm_margin;
2736         uint32_t stop;
2737         uint32_t temp_dq_out1_delay;
2738         uint32_t addr;
2739
2740         debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2741
2742         dm_margin = 0;
2743
2744         addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2745         start_dqs = readl(addr +
2746                           (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2747
2748         /* per-bit deskew */
2749
2750         /*
2751          * set the left and right edge of each bit to an illegal value
2752          * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2753          */
2754         sticky_bit_chk = 0;
2755         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2756                 left_edge[i]  = IO_IO_OUT1_DELAY_MAX + 1;
2757                 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2758         }
2759
2760         /* Search for the left edge of the window for each bit */
2761         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
2762                 scc_mgr_apply_group_dq_out1_delay(write_group, d);
2763
2764                 writel(0, &sdr_scc_mgr->update);
2765
2766                 /*
2767                  * Stop searching when the read test doesn't pass AND when
2768                  * we've seen a passing read on every bit.
2769                  */
2770                 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2771                         0, PASS_ONE_BIT, &bit_chk, 0);
2772                 sticky_bit_chk = sticky_bit_chk | bit_chk;
2773                 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2774                 debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
2775                            == %u && %u [bit_chk= %u ]\n",
2776                         d, sticky_bit_chk, param->write_correct_mask,
2777                         stop, bit_chk);
2778
2779                 if (stop == 1) {
2780                         break;
2781                 } else {
2782                         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2783                                 if (bit_chk & 1) {
2784                                         /*
2785                                          * Remember a passing test as the
2786                                          * left_edge.
2787                                          */
2788                                         left_edge[i] = d;
2789                                 } else {
2790                                         /*
2791                                          * If a left edge has not been seen
2792                                          * yet, then a future passing test will
2793                                          * mark this edge as the right edge.
2794                                          */
2795                                         if (left_edge[i] ==
2796                                                 IO_IO_OUT1_DELAY_MAX + 1) {
2797                                                 right_edge[i] = -(d + 1);
2798                                         }
2799                                 }
2800                                 debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
2801                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2802                                            (int)(bit_chk & 1), i, left_edge[i]);
2803                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2804                                        right_edge[i]);
2805                                 bit_chk = bit_chk >> 1;
2806                         }
2807                 }
2808         }
2809
2810         /* Reset DQ delay chains to 0 */
2811         scc_mgr_apply_group_dq_out1_delay(0);
2812         sticky_bit_chk = 0;
2813         for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
2814                 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2815                            %d right_edge[%u]: %d\n", __func__, __LINE__,
2816                            i, left_edge[i], i, right_edge[i]);
2817
2818                 /*
2819                  * Check for cases where we haven't found the left edge,
2820                  * which makes our assignment of the the right edge invalid.
2821                  * Reset it to the illegal value.
2822                  */
2823                 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
2824                     (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
2825                         right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2826                         debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
2827                                    right_edge[%u]: %d\n", __func__, __LINE__,
2828                                    i, right_edge[i]);
2829                 }
2830
2831                 /*
2832                  * Reset sticky bit (except for bits where we have
2833                  * seen the left edge).
2834                  */
2835                 sticky_bit_chk = sticky_bit_chk << 1;
2836                 if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
2837                         sticky_bit_chk = sticky_bit_chk | 1;
2838
2839                 if (i == 0)
2840                         break;
2841         }
2842
2843         /* Search for the right edge of the window for each bit */
2844         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
2845                 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2846                                                         d + start_dqs);
2847
2848                 writel(0, &sdr_scc_mgr->update);
2849
2850                 /*
2851                  * Stop searching when the read test doesn't pass AND when
2852                  * we've seen a passing read on every bit.
2853                  */
2854                 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2855                         0, PASS_ONE_BIT, &bit_chk, 0);
2856
2857                 sticky_bit_chk = sticky_bit_chk | bit_chk;
2858                 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2859
2860                 debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
2861                            %u && %u\n", d, sticky_bit_chk,
2862                            param->write_correct_mask, stop);
2863
2864                 if (stop == 1) {
2865                         if (d == 0) {
2866                                 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
2867                                         i++) {
2868                                         /* d = 0 failed, but it passed when
2869                                         testing the left edge, so it must be
2870                                         marginal, set it to -1 */
2871                                         if (right_edge[i] ==
2872                                                 IO_IO_OUT1_DELAY_MAX + 1 &&
2873                                                 left_edge[i] !=
2874                                                 IO_IO_OUT1_DELAY_MAX + 1) {
2875                                                 right_edge[i] = -1;
2876                                         }
2877                                 }
2878                         }
2879                         break;
2880                 } else {
2881                         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2882                                 if (bit_chk & 1) {
2883                                         /*
2884                                          * Remember a passing test as
2885                                          * the right_edge.
2886                                          */
2887                                         right_edge[i] = d;
2888                                 } else {
2889                                         if (d != 0) {
2890                                                 /*
2891                                                  * If a right edge has not
2892                                                  * been seen yet, then a future
2893                                                  * passing test will mark this
2894                                                  * edge as the left edge.
2895                                                  */
2896                                                 if (right_edge[i] ==
2897                                                     IO_IO_OUT1_DELAY_MAX + 1)
2898                                                         left_edge[i] = -(d + 1);
2899                                         } else {
2900                                                 /*
2901                                                  * d = 0 failed, but it passed
2902                                                  * when testing the left edge,
2903                                                  * so it must be marginal, set
2904                                                  * it to -1.
2905                                                  */
2906                                                 if (right_edge[i] ==
2907                                                     IO_IO_OUT1_DELAY_MAX + 1 &&
2908                                                     left_edge[i] !=
2909                                                     IO_IO_OUT1_DELAY_MAX + 1)
2910                                                         right_edge[i] = -1;
2911                                                 /*
2912                                                  * If a right edge has not been
2913                                                  * seen yet, then a future
2914                                                  * passing test will mark this
2915                                                  * edge as the left edge.
2916                                                  */
2917                                                 else if (right_edge[i] ==
2918                                                         IO_IO_OUT1_DELAY_MAX +
2919                                                         1)
2920                                                         left_edge[i] = -(d + 1);
2921                                         }
2922                                 }
2923                                 debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
2924                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2925                                            (int)(bit_chk & 1), i, left_edge[i]);
2926                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2927                                            right_edge[i]);
2928                                 bit_chk = bit_chk >> 1;
2929                         }
2930                 }
2931         }
2932
2933         /* Check that all bits have a window */
2934         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2935                 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2936                            %d right_edge[%u]: %d", __func__, __LINE__,
2937                            i, left_edge[i], i, right_edge[i]);
2938                 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
2939                     (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
2940                         set_failing_group_stage(test_bgn + i,
2941                                                 CAL_STAGE_WRITES,
2942                                                 CAL_SUBSTAGE_WRITES_CENTER);
2943                         return 0;
2944                 }
2945         }
2946
2947         /* Find middle of window for each DQ bit */
2948         mid_min = left_edge[0] - right_edge[0];
2949         min_index = 0;
2950         for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2951                 mid = left_edge[i] - right_edge[i];
2952                 if (mid < mid_min) {
2953                         mid_min = mid;
2954                         min_index = i;
2955                 }
2956         }
2957
2958         /*
2959          * -mid_min/2 represents the amount that we need to move DQS.
2960          * If mid_min is odd and positive we'll need to add one to
2961          * make sure the rounding in further calculations is correct
2962          * (always bias to the right), so just add 1 for all positive values.
2963          */
2964         if (mid_min > 0)
2965                 mid_min++;
2966         mid_min = mid_min / 2;
2967         debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2968                    __LINE__, mid_min);
2969
2970         /* Determine the amount we can change DQS (which is -mid_min) */
2971         orig_mid_min = mid_min;
2972         new_dqs = start_dqs;
2973         mid_min = 0;
2974         debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2975                    mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2976         /* Initialize data for export structures */
2977         dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2978         dq_margin  = IO_IO_OUT1_DELAY_MAX + 1;
2979
2980         /* add delay to bring centre of all DQ windows to the same "level" */
2981         for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2982                 /* Use values before divide by 2 to reduce round off error */
2983                 shift_dq = (left_edge[i] - right_edge[i] -
2984                         (left_edge[min_index] - right_edge[min_index]))/2  +
2985                 (orig_mid_min - mid_min);
2986
2987                 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2988                            [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2989
2990                 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2991                 temp_dq_out1_delay = readl(addr + (i << 2));
2992                 if (shift_dq + (int32_t)temp_dq_out1_delay >
2993                         (int32_t)IO_IO_OUT1_DELAY_MAX) {
2994                         shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2995                 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
2996                         shift_dq = -(int32_t)temp_dq_out1_delay;
2997                 }
2998                 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
2999                            i, shift_dq);
3000                 scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
3001                 scc_mgr_load_dq(i);
3002
3003                 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
3004                            left_edge[i] - shift_dq + (-mid_min),
3005                            right_edge[i] + shift_dq - (-mid_min));
3006                 /* To determine values for export structures */
3007                 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
3008                         dq_margin = left_edge[i] - shift_dq + (-mid_min);
3009
3010                 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
3011                         dqs_margin = right_edge[i] + shift_dq - (-mid_min);
3012         }
3013
3014         /* Move DQS */
3015         scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3016         writel(0, &sdr_scc_mgr->update);
3017
3018         /* Centre DM */
3019         debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
3020
3021         /*
3022          * set the left and right edge of each bit to an illegal value,
3023          * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
3024          */
3025         left_edge[0]  = IO_IO_OUT1_DELAY_MAX + 1;
3026         right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
3027         int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3028         int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3029         int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
3030         int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
3031         int32_t win_best = 0;
3032
3033         /* Search for the/part of the window with DM shift */
3034         for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
3035                 scc_mgr_apply_group_dm_out1_delay(d);
3036                 writel(0, &sdr_scc_mgr->update);
3037
3038                 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3039                                                     PASS_ALL_BITS, &bit_chk,
3040                                                     0)) {
3041                         /* USE Set current end of the window */
3042                         end_curr = -d;
3043                         /*
3044                          * If a starting edge of our window has not been seen
3045                          * this is our current start of the DM window.
3046                          */
3047                         if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3048                                 bgn_curr = -d;
3049
3050                         /*
3051                          * If current window is bigger than best seen.
3052                          * Set best seen to be current window.
3053                          */
3054                         if ((end_curr-bgn_curr+1) > win_best) {
3055                                 win_best = end_curr-bgn_curr+1;
3056                                 bgn_best = bgn_curr;
3057                                 end_best = end_curr;
3058                         }
3059                 } else {
3060                         /* We just saw a failing test. Reset temp edge */
3061                         bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3062                         end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3063                         }
3064                 }
3065
3066
3067         /* Reset DM delay chains to 0 */
3068         scc_mgr_apply_group_dm_out1_delay(0);
3069
3070         /*
3071          * Check to see if the current window nudges up aganist 0 delay.
3072          * If so we need to continue the search by shifting DQS otherwise DQS
3073          * search begins as a new search. */
3074         if (end_curr != 0) {
3075                 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3076                 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3077         }
3078
3079         /* Search for the/part of the window with DQS shifts */
3080         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
3081                 /*
3082                  * Note: This only shifts DQS, so are we limiting ourselve to
3083                  * width of DQ unnecessarily.
3084                  */
3085                 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
3086                                                         d + new_dqs);
3087
3088                 writel(0, &sdr_scc_mgr->update);
3089                 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3090                                                     PASS_ALL_BITS, &bit_chk,
3091                                                     0)) {
3092                         /* USE Set current end of the window */
3093                         end_curr = d;
3094                         /*
3095                          * If a beginning edge of our window has not been seen
3096                          * this is our current begin of the DM window.
3097                          */
3098                         if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3099                                 bgn_curr = d;
3100
3101                         /*
3102                          * If current window is bigger than best seen. Set best
3103                          * seen to be current window.
3104                          */
3105                         if ((end_curr-bgn_curr+1) > win_best) {
3106                                 win_best = end_curr-bgn_curr+1;
3107                                 bgn_best = bgn_curr;
3108                                 end_best = end_curr;
3109                         }
3110                 } else {
3111                         /* We just saw a failing test. Reset temp edge */
3112                         bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3113                         end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3114
3115                         /* Early exit optimization: if ther remaining delay
3116                         chain space is less than already seen largest window
3117                         we can exit */
3118                         if ((win_best-1) >
3119                                 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3120                                         break;
3121                                 }
3122                         }
3123                 }
3124
3125         /* assign left and right edge for cal and reporting; */
3126         left_edge[0] = -1*bgn_best;
3127         right_edge[0] = end_best;
3128
3129         debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3130                    __LINE__, left_edge[0], right_edge[0]);
3131
3132         /* Move DQS (back to orig) */
3133         scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3134
3135         /* Move DM */
3136
3137         /* Find middle of window for the DM bit */
3138         mid = (left_edge[0] - right_edge[0]) / 2;
3139
3140         /* only move right, since we are not moving DQS/DQ */
3141         if (mid < 0)
3142                 mid = 0;
3143
3144         /* dm_marign should fail if we never find a window */
3145         if (win_best == 0)
3146                 dm_margin = -1;
3147         else
3148                 dm_margin = left_edge[0] - mid;
3149
3150         scc_mgr_apply_group_dm_out1_delay(mid);
3151         writel(0, &sdr_scc_mgr->update);
3152
3153         debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3154                    dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3155                    right_edge[0], mid, dm_margin);
3156         /* Export values */
3157         gbl->fom_out += dq_margin + dqs_margin;
3158
3159         debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3160                    dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3161                    dq_margin, dqs_margin, dm_margin);
3162
3163         /*
3164          * Do not remove this line as it makes sure all of our
3165          * decisions have been applied.
3166          */
3167         writel(0, &sdr_scc_mgr->update);
3168         return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3169 }
3170
3171 /* calibrate the write operations */
3172 static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
3173         uint32_t test_bgn)
3174 {
3175         /* update info for sims */
3176         debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
3177
3178         reg_file_set_stage(CAL_STAGE_WRITES);
3179         reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3180
3181         reg_file_set_group(g);
3182
3183         if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
3184                 set_failing_group_stage(g, CAL_STAGE_WRITES,
3185                                         CAL_SUBSTAGE_WRITES_CENTER);
3186                 return 0;
3187         }
3188
3189         return 1;
3190 }
3191
3192 /**
3193  * mem_precharge_and_activate() - Precharge all banks and activate
3194  *
3195  * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3196  */
3197 static void mem_precharge_and_activate(void)
3198 {
3199         int r;
3200
3201         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3202                 /* Test if the rank should be skipped. */
3203                 if (param->skip_ranks[r])
3204                         continue;
3205
3206                 /* Set rank. */
3207                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3208
3209                 /* Precharge all banks. */
3210                 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3211                                              RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3212
3213                 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3214                 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3215                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3216
3217                 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3218                 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3219                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3220
3221                 /* Activate rows. */
3222                 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3223                                                 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3224         }
3225 }
3226
3227 /**
3228  * mem_init_latency() - Configure memory RLAT and WLAT settings
3229  *
3230  * Configure memory RLAT and WLAT parameters.
3231  */
3232 static void mem_init_latency(void)
3233 {
3234         /*
3235          * For AV/CV, LFIFO is hardened and always runs at full rate
3236          * so max latency in AFI clocks, used here, is correspondingly
3237          * smaller.
3238          */
3239         const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
3240         u32 rlat, wlat;
3241
3242         debug("%s:%d\n", __func__, __LINE__);
3243
3244         /*
3245          * Read in write latency.
3246          * WL for Hard PHY does not include additive latency.
3247          */
3248         wlat = readl(&data_mgr->t_wl_add);
3249         wlat += readl(&data_mgr->mem_t_add);
3250
3251         gbl->rw_wl_nop_cycles = wlat - 1;
3252
3253         /* Read in readl latency. */
3254         rlat = readl(&data_mgr->t_rl_add);
3255
3256         /* Set a pretty high read latency initially. */
3257         gbl->curr_read_lat = rlat + 16;
3258         if (gbl->curr_read_lat > max_latency)
3259                 gbl->curr_read_lat = max_latency;
3260
3261         writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3262
3263         /* Advertise write latency. */
3264         writel(wlat, &phy_mgr_cfg->afi_wlat);
3265 }
3266
3267 /**
3268  * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3269  *
3270  * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3271  */
3272 static void mem_skip_calibrate(void)
3273 {
3274         uint32_t vfifo_offset;
3275         uint32_t i, j, r;
3276
3277         debug("%s:%d\n", __func__, __LINE__);
3278         /* Need to update every shadow register set used by the interface */
3279         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3280              r += NUM_RANKS_PER_SHADOW_REG) {
3281                 /*
3282                  * Set output phase alignment settings appropriate for
3283                  * skip calibration.
3284                  */
3285                 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3286                         scc_mgr_set_dqs_en_phase(i, 0);
3287 #if IO_DLL_CHAIN_LENGTH == 6
3288                         scc_mgr_set_dqdqs_output_phase(i, 6);
3289 #else
3290                         scc_mgr_set_dqdqs_output_phase(i, 7);
3291 #endif
3292                         /*
3293                          * Case:33398
3294                          *
3295                          * Write data arrives to the I/O two cycles before write
3296                          * latency is reached (720 deg).
3297                          *   -> due to bit-slip in a/c bus
3298                          *   -> to allow board skew where dqs is longer than ck
3299                          *      -> how often can this happen!?
3300                          *      -> can claim back some ptaps for high freq
3301                          *       support if we can relax this, but i digress...
3302                          *
3303                          * The write_clk leads mem_ck by 90 deg
3304                          * The minimum ptap of the OPA is 180 deg
3305                          * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3306                          * The write_clk is always delayed by 2 ptaps
3307                          *
3308                          * Hence, to make DQS aligned to CK, we need to delay
3309                          * DQS by:
3310                          *    (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3311                          *
3312                          * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3313                          * gives us the number of ptaps, which simplies to:
3314                          *
3315                          *    (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3316                          */
3317                         scc_mgr_set_dqdqs_output_phase(i,
3318                                         1.25 * IO_DLL_CHAIN_LENGTH - 2);
3319                 }
3320                 writel(0xff, &sdr_scc_mgr->dqs_ena);
3321                 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3322
3323                 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3324                         writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3325                                   SCC_MGR_GROUP_COUNTER_OFFSET);
3326                 }
3327                 writel(0xff, &sdr_scc_mgr->dq_ena);
3328                 writel(0xff, &sdr_scc_mgr->dm_ena);
3329                 writel(0, &sdr_scc_mgr->update);
3330         }
3331
3332         /* Compensate for simulation model behaviour */
3333         for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3334                 scc_mgr_set_dqs_bus_in_delay(i, 10);
3335                 scc_mgr_load_dqs(i);
3336         }
3337         writel(0, &sdr_scc_mgr->update);
3338
3339         /*
3340          * ArriaV has hard FIFOs that can only be initialized by incrementing
3341          * in sequencer.
3342          */
3343         vfifo_offset = CALIB_VFIFO_OFFSET;
3344         for (j = 0; j < vfifo_offset; j++)
3345                 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3346         writel(0, &phy_mgr_cmd->fifo_reset);
3347
3348         /*
3349          * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3350          * setting from generation-time constant.
3351          */
3352         gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3353         writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3354 }
3355
3356 /**
3357  * mem_calibrate() - Memory calibration entry point.
3358  *
3359  * Perform memory calibration.
3360  */
3361 static uint32_t mem_calibrate(void)
3362 {
3363         uint32_t i;
3364         uint32_t rank_bgn, sr;
3365         uint32_t write_group, write_test_bgn;
3366         uint32_t read_group, read_test_bgn;
3367         uint32_t run_groups, current_run;
3368         uint32_t failing_groups = 0;
3369         uint32_t group_failed = 0;
3370
3371         const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
3372                                 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
3373
3374         debug("%s:%d\n", __func__, __LINE__);
3375
3376         /* Initialize the data settings */
3377         gbl->error_substage = CAL_SUBSTAGE_NIL;
3378         gbl->error_stage = CAL_STAGE_NIL;
3379         gbl->error_group = 0xff;
3380         gbl->fom_in = 0;
3381         gbl->fom_out = 0;
3382
3383         /* Initialize WLAT and RLAT. */
3384         mem_init_latency();
3385
3386         /* Initialize bit slips. */
3387         mem_precharge_and_activate();
3388
3389         for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3390                 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3391                           SCC_MGR_GROUP_COUNTER_OFFSET);
3392                 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3393                 if (i == 0)
3394                         scc_mgr_set_hhp_extras();
3395
3396                 scc_set_bypass_mode(i);
3397         }
3398
3399         /* Calibration is skipped. */
3400         if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3401                 /*
3402                  * Set VFIFO and LFIFO to instant-on settings in skip
3403                  * calibration mode.
3404                  */
3405                 mem_skip_calibrate();
3406
3407                 /*
3408                  * Do not remove this line as it makes sure all of our
3409                  * decisions have been applied.
3410                  */
3411                 writel(0, &sdr_scc_mgr->update);
3412                 return 1;
3413         }
3414
3415         /* Calibration is not skipped. */
3416         for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3417                 /*
3418                  * Zero all delay chain/phase settings for all
3419                  * groups and all shadow register sets.
3420                  */
3421                 scc_mgr_zero_all();
3422
3423                 run_groups = ~param->skip_groups;
3424
3425                 for (write_group = 0, write_test_bgn = 0; write_group
3426                         < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3427                         write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3428
3429                         /* Initialize the group failure */
3430                         group_failed = 0;
3431
3432                         current_run = run_groups & ((1 <<
3433                                 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3434                         run_groups = run_groups >>
3435                                 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3436
3437                         if (current_run == 0)
3438                                 continue;
3439
3440                         writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3441                                             SCC_MGR_GROUP_COUNTER_OFFSET);
3442                         scc_mgr_zero_group(write_group, 0);
3443
3444                         for (read_group = write_group * rwdqs_ratio,
3445                              read_test_bgn = 0;
3446                              read_group < (write_group + 1) * rwdqs_ratio;
3447                              read_group++,
3448                              read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3449                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3450                                         continue;
3451
3452                                 /* Calibrate the VFIFO */
3453                                 if (rw_mgr_mem_calibrate_vfifo(read_group,
3454                                                                read_test_bgn))
3455                                         continue;
3456
3457                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3458                                         return 0;
3459
3460                                 /* The group failed, we're done. */
3461                                 goto grp_failed;
3462                         }
3463
3464                         /* Calibrate the output side */
3465                         for (rank_bgn = 0, sr = 0;
3466                              rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
3467                              rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3468                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3469                                         continue;
3470
3471                                 /* Not needed in quick mode! */
3472                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
3473                                         continue;
3474
3475                                 /*
3476                                  * Determine if this set of ranks
3477                                  * should be skipped entirely.
3478                                  */
3479                                 if (param->skip_shadow_regs[sr])
3480                                         continue;
3481
3482                                 /* Calibrate WRITEs */
3483                                 if (rw_mgr_mem_calibrate_writes(rank_bgn,
3484                                                 write_group, write_test_bgn))
3485                                         continue;
3486
3487                                 group_failed = 1;
3488                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3489                                         return 0;
3490                         }
3491
3492                         /* Some group failed, we're done. */
3493                         if (group_failed)
3494                                 goto grp_failed;
3495
3496                         for (read_group = write_group * rwdqs_ratio,
3497                              read_test_bgn = 0;
3498                              read_group < (write_group + 1) * rwdqs_ratio;
3499                              read_group++,
3500                              read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3501                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3502                                         continue;
3503
3504                                 if (rw_mgr_mem_calibrate_vfifo_end(read_group,
3505                                                                 read_test_bgn))
3506                                         continue;
3507
3508                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3509                                         return 0;
3510
3511                                 /* The group failed, we're done. */
3512                                 goto grp_failed;
3513                         }
3514
3515                         /* No group failed, continue as usual. */
3516                         continue;
3517
3518 grp_failed:             /* A group failed, increment the counter. */
3519                         failing_groups++;
3520                 }
3521
3522                 /*
3523                  * USER If there are any failing groups then report
3524                  * the failure.
3525                  */
3526                 if (failing_groups != 0)
3527                         return 0;
3528
3529                 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3530                         continue;
3531
3532                 /*
3533                  * If we're skipping groups as part of debug,
3534                  * don't calibrate LFIFO.
3535                  */
3536                 if (param->skip_groups != 0)
3537                         continue;
3538
3539                 /* Calibrate the LFIFO */
3540                 if (!rw_mgr_mem_calibrate_lfifo())
3541                         return 0;
3542         }
3543
3544         /*
3545          * Do not remove this line as it makes sure all of our decisions
3546          * have been applied.
3547          */
3548         writel(0, &sdr_scc_mgr->update);
3549         return 1;
3550 }
3551
3552 /**
3553  * run_mem_calibrate() - Perform memory calibration
3554  *
3555  * This function triggers the entire memory calibration procedure.
3556  */
3557 static int run_mem_calibrate(void)
3558 {
3559         int pass;
3560
3561         debug("%s:%d\n", __func__, __LINE__);
3562
3563         /* Reset pass/fail status shown on afi_cal_success/fail */
3564         writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3565
3566         /* Stop tracking manager. */
3567         clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3568
3569         phy_mgr_initialize();
3570         rw_mgr_mem_initialize();
3571
3572         /* Perform the actual memory calibration. */
3573         pass = mem_calibrate();
3574
3575         mem_precharge_and_activate();
3576         writel(0, &phy_mgr_cmd->fifo_reset);
3577
3578         /* Handoff. */
3579         rw_mgr_mem_handoff();
3580         /*
3581          * In Hard PHY this is a 2-bit control:
3582          * 0: AFI Mux Select
3583          * 1: DDIO Mux Select
3584          */
3585         writel(0x2, &phy_mgr_cfg->mux_sel);
3586
3587         /* Start tracking manager. */
3588         setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3589
3590         return pass;
3591 }
3592
3593 /**
3594  * debug_mem_calibrate() - Report result of memory calibration
3595  * @pass:       Value indicating whether calibration passed or failed
3596  *
3597  * This function reports the results of the memory calibration
3598  * and writes debug information into the register file.
3599  */
3600 static void debug_mem_calibrate(int pass)
3601 {
3602         uint32_t debug_info;
3603
3604         if (pass) {
3605                 printf("%s: CALIBRATION PASSED\n", __FILE__);
3606
3607                 gbl->fom_in /= 2;
3608                 gbl->fom_out /= 2;
3609
3610                 if (gbl->fom_in > 0xff)
3611                         gbl->fom_in = 0xff;
3612
3613                 if (gbl->fom_out > 0xff)
3614                         gbl->fom_out = 0xff;
3615
3616                 /* Update the FOM in the register file */
3617                 debug_info = gbl->fom_in;
3618                 debug_info |= gbl->fom_out << 8;
3619                 writel(debug_info, &sdr_reg_file->fom);
3620
3621                 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3622                 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3623         } else {
3624                 printf("%s: CALIBRATION FAILED\n", __FILE__);
3625
3626                 debug_info = gbl->error_stage;
3627                 debug_info |= gbl->error_substage << 8;
3628                 debug_info |= gbl->error_group << 16;
3629
3630                 writel(debug_info, &sdr_reg_file->failing_stage);
3631                 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3632                 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3633
3634                 /* Update the failing group/stage in the register file */
3635                 debug_info = gbl->error_stage;
3636                 debug_info |= gbl->error_substage << 8;
3637                 debug_info |= gbl->error_group << 16;
3638                 writel(debug_info, &sdr_reg_file->failing_stage);
3639         }
3640
3641         printf("%s: Calibration complete\n", __FILE__);
3642 }
3643
3644 /**
3645  * hc_initialize_rom_data() - Initialize ROM data
3646  *
3647  * Initialize ROM data.
3648  */
3649 static void hc_initialize_rom_data(void)
3650 {
3651         u32 i, addr;
3652
3653         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3654         for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3655                 writel(inst_rom_init[i], addr + (i << 2));
3656
3657         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3658         for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3659                 writel(ac_rom_init[i], addr + (i << 2));
3660 }
3661
3662 /**
3663  * initialize_reg_file() - Initialize SDR register file
3664  *
3665  * Initialize SDR register file.
3666  */
3667 static void initialize_reg_file(void)
3668 {
3669         /* Initialize the register file with the correct data */
3670         writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3671         writel(0, &sdr_reg_file->debug_data_addr);
3672         writel(0, &sdr_reg_file->cur_stage);
3673         writel(0, &sdr_reg_file->fom);
3674         writel(0, &sdr_reg_file->failing_stage);
3675         writel(0, &sdr_reg_file->debug1);
3676         writel(0, &sdr_reg_file->debug2);
3677 }
3678
3679 /**
3680  * initialize_hps_phy() - Initialize HPS PHY
3681  *
3682  * Initialize HPS PHY.
3683  */
3684 static void initialize_hps_phy(void)
3685 {
3686         uint32_t reg;
3687         /*
3688          * Tracking also gets configured here because it's in the
3689          * same register.
3690          */
3691         uint32_t trk_sample_count = 7500;
3692         uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3693         /*
3694          * Format is number of outer loops in the 16 MSB, sample
3695          * count in 16 LSB.
3696          */
3697
3698         reg = 0;
3699         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3700         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3701         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3702         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3703         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3704         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3705         /*
3706          * This field selects the intrinsic latency to RDATA_EN/FULL path.
3707          * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3708          */
3709         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3710         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3711                 trk_sample_count);
3712         writel(reg, &sdr_ctrl->phy_ctrl0);
3713
3714         reg = 0;
3715         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3716                 trk_sample_count >>
3717                 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3718         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3719                 trk_long_idle_sample_count);
3720         writel(reg, &sdr_ctrl->phy_ctrl1);
3721
3722         reg = 0;
3723         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3724                 trk_long_idle_sample_count >>
3725                 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3726         writel(reg, &sdr_ctrl->phy_ctrl2);
3727 }
3728
3729 /**
3730  * initialize_tracking() - Initialize tracking
3731  *
3732  * Initialize the register file with usable initial data.
3733  */
3734 static void initialize_tracking(void)
3735 {
3736         /*
3737          * Initialize the register file with the correct data.
3738          * Compute usable version of value in case we skip full
3739          * computation later.
3740          */
3741         writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
3742                &sdr_reg_file->dtaps_per_ptap);
3743
3744         /* trk_sample_count */
3745         writel(7500, &sdr_reg_file->trk_sample_count);
3746
3747         /* longidle outer loop [15:0] */
3748         writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
3749
3750         /*
3751          * longidle sample count [31:24]
3752          * trfc, worst case of 933Mhz 4Gb [23:16]
3753          * trcd, worst case [15:8]
3754          * vfifo wait [7:0]
3755          */
3756         writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3757                &sdr_reg_file->delays);
3758
3759         /* mux delay */
3760         writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
3761                (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
3762                &sdr_reg_file->trk_rw_mgr_addr);
3763
3764         writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
3765                &sdr_reg_file->trk_read_dqs_width);
3766
3767         /* trefi [7:0] */
3768         writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
3769                &sdr_reg_file->trk_rfsh);
3770 }
3771
3772 int sdram_calibration_full(void)
3773 {
3774         struct param_type my_param;
3775         struct gbl_type my_gbl;
3776         uint32_t pass;
3777
3778         memset(&my_param, 0, sizeof(my_param));
3779         memset(&my_gbl, 0, sizeof(my_gbl));
3780
3781         param = &my_param;
3782         gbl = &my_gbl;
3783
3784         /* Set the calibration enabled by default */
3785         gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3786         /*
3787          * Only sweep all groups (regardless of fail state) by default
3788          * Set enabled read test by default.
3789          */
3790 #if DISABLE_GUARANTEED_READ
3791         gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3792 #endif
3793         /* Initialize the register file */
3794         initialize_reg_file();
3795
3796         /* Initialize any PHY CSR */
3797         initialize_hps_phy();
3798
3799         scc_mgr_initialize();
3800
3801         initialize_tracking();
3802
3803         printf("%s: Preparing to start memory calibration\n", __FILE__);
3804
3805         debug("%s:%d\n", __func__, __LINE__);
3806         debug_cond(DLEVEL == 1,
3807                    "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3808                    RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3809                    RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3810                    RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3811                    RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3812         debug_cond(DLEVEL == 1,
3813                    "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3814                    RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3815                    RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3816                    IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3817         debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3818                    IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3819         debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3820                    IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3821                    IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3822         debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3823                    IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3824                    IO_IO_OUT2_DELAY_MAX);
3825         debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3826                    IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3827
3828         hc_initialize_rom_data();
3829
3830         /* update info for sims */
3831         reg_file_set_stage(CAL_STAGE_NIL);
3832         reg_file_set_group(0);
3833
3834         /*
3835          * Load global needed for those actions that require
3836          * some dynamic calibration support.
3837          */
3838         dyn_calib_steps = STATIC_CALIB_STEPS;
3839         /*
3840          * Load global to allow dynamic selection of delay loop settings
3841          * based on calibration mode.
3842          */
3843         if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3844                 skip_delay_mask = 0xff;
3845         else
3846                 skip_delay_mask = 0x0;
3847
3848         pass = run_mem_calibrate();
3849         debug_mem_calibrate(pass);
3850         return pass;
3851 }