drivers/ddr/fsl/ctrl_regs.c

   1 /*
   2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
   9  * Based on code from spd_sdram.c
  10  * Author: James Yang [at freescale.com]
  11  */
  12
  13 #include <common.h>
  14 #include <fsl_ddr_sdram.h>
  15
  16 #include <fsl_ddr.h>
  17 #include <fsl_immap.h>
  18 #include <asm/io.h>
  19
  20 #define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR
  21
  22 static u32 fsl_ddr_get_version(void)
  23 {
  24         struct ccsr_ddr __iomem *ddr;
  25         u32 ver_major_minor_errata;
  26
  27         ddr = (void *)_DDR_ADDR;
  28         ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8;
  29         ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8;
  30
  31         return ver_major_minor_errata;
  32 }
  33
  34 unsigned int picos_to_mclk(unsigned int picos);
  35
  36 /*
  37  * Determine Rtt value.
  38  *
  39  * This should likely be either board or controller specific.
  40  *
  41  * Rtt(nominal) - DDR2:
  42  *      0 = Rtt disabled
  43  *      1 = 75 ohm
  44  *      2 = 150 ohm
  45  *      3 = 50 ohm
  46  * Rtt(nominal) - DDR3:
  47  *      0 = Rtt disabled
  48  *      1 = 60 ohm
  49  *      2 = 120 ohm
  50  *      3 = 40 ohm
  51  *      4 = 20 ohm
  52  *      5 = 30 ohm
  53  *
  54  * FIXME: Apparently 8641 needs a value of 2
  55  * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  56  *
  57  * FIXME: There was some effort down this line earlier:
  58  *
  59  *      unsigned int i;
  60  *      for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  61  *              if (popts->dimmslot[i].num_valid_cs
  62  *                  && (popts->cs_local_opts[2*i].odt_rd_cfg
  63  *                      || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  64  *                      rtt = 2;
  65  *                      break;
  66  *              }
  67  *      }
  68  */
  69 static inline int fsl_ddr_get_rtt(void)
  70 {
  71         int rtt;
  72
  73 #if defined(CONFIG_SYS_FSL_DDR1)
  74         rtt = 0;
  75 #elif defined(CONFIG_SYS_FSL_DDR2)
  76         rtt = 3;
  77 #else
  78         rtt = 0;
  79 #endif
  80
  81         return rtt;
  82 }
  83
  84 /*
  85  * compute the CAS write latency according to DDR3 spec
  86  * CWL = 5 if tCK >= 2.5ns
  87  *       6 if 2.5ns > tCK >= 1.875ns
  88  *       7 if 1.875ns > tCK >= 1.5ns
  89  *       8 if 1.5ns > tCK >= 1.25ns
  90  *       9 if 1.25ns > tCK >= 1.07ns
  91  *       10 if 1.07ns > tCK >= 0.935ns
  92  *       11 if 0.935ns > tCK >= 0.833ns
  93  *       12 if 0.833ns > tCK >= 0.75ns
  94  */
  95 static inline unsigned int compute_cas_write_latency(void)
  96 {
  97         unsigned int cwl;
  98         const unsigned int mclk_ps = get_memory_clk_period_ps();
  99
 100         if (mclk_ps >= 2500)
 101                 cwl = 5;
 102         else if (mclk_ps >= 1875)
 103                 cwl = 6;
 104         else if (mclk_ps >= 1500)
 105                 cwl = 7;
 106         else if (mclk_ps >= 1250)
 107                 cwl = 8;
 108         else if (mclk_ps >= 1070)
 109                 cwl = 9;
 110         else if (mclk_ps >= 935)
 111                 cwl = 10;
 112         else if (mclk_ps >= 833)
 113                 cwl = 11;
 114         else if (mclk_ps >= 750)
 115                 cwl = 12;
 116         else {
 117                 cwl = 12;
 118                 printf("Warning: CWL is out of range\n");
 119         }
 120         return cwl;
 121 }
 122
 123 /* Chip Select Configuration (CSn_CONFIG) */
 124 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
 125                                const memctl_options_t *popts,
 126                                const dimm_params_t *dimm_params)
 127 {
 128         unsigned int cs_n_en = 0; /* Chip Select enable */
 129         unsigned int intlv_en = 0; /* Memory controller interleave enable */
 130         unsigned int intlv_ctl = 0; /* Interleaving control */
 131         unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
 132         unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
 133         unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
 134         unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
 135         unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
 136         unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
 137         int go_config = 0;
 138
 139         /* Compute CS_CONFIG only for existing ranks of each DIMM.  */
 140         switch (i) {
 141         case 0:
 142                 if (dimm_params[dimm_number].n_ranks > 0) {
 143                         go_config = 1;
 144                         /* These fields only available in CS0_CONFIG */
 145                         if (!popts->memctl_interleaving)
 146                                 break;
 147                         switch (popts->memctl_interleaving_mode) {
 148                         case FSL_DDR_256B_INTERLEAVING:
 149                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
 150                         case FSL_DDR_PAGE_INTERLEAVING:
 151                         case FSL_DDR_BANK_INTERLEAVING:
 152                         case FSL_DDR_SUPERBANK_INTERLEAVING:
 153                                 intlv_en = popts->memctl_interleaving;
 154                                 intlv_ctl = popts->memctl_interleaving_mode;
 155                                 break;
 156                         default:
 157                                 break;
 158                         }
 159                 }
 160                 break;
 161         case 1:
 162                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
 163                     (dimm_number == 1 && dimm_params[1].n_ranks > 0))
 164                         go_config = 1;
 165                 break;
 166         case 2:
 167                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
 168                    (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
 169                         go_config = 1;
 170                 break;
 171         case 3:
 172                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
 173                     (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
 174                     (dimm_number == 3 && dimm_params[3].n_ranks > 0))
 175                         go_config = 1;
 176                 break;
 177         default:
 178                 break;
 179         }
 180         if (go_config) {
 181                 unsigned int n_banks_per_sdram_device;
 182                 cs_n_en = 1;
 183                 ap_n_en = popts->cs_local_opts[i].auto_precharge;
 184                 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
 185                 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
 186                 n_banks_per_sdram_device
 187                         = dimm_params[dimm_number].n_banks_per_sdram_device;
 188                 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
 189                 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
 190                 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
 191         }
 192         ddr->cs[i].config = (0
 193                 | ((cs_n_en & 0x1) << 31)
 194                 | ((intlv_en & 0x3) << 29)
 195                 | ((intlv_ctl & 0xf) << 24)
 196                 | ((ap_n_en & 0x1) << 23)
 197
 198                 /* XXX: some implementation only have 1 bit starting at left */
 199                 | ((odt_rd_cfg & 0x7) << 20)
 200
 201                 /* XXX: Some implementation only have 1 bit starting at left */
 202                 | ((odt_wr_cfg & 0x7) << 16)
 203
 204                 | ((ba_bits_cs_n & 0x3) << 14)
 205                 | ((row_bits_cs_n & 0x7) << 8)
 206                 | ((col_bits_cs_n & 0x7) << 0)
 207                 );
 208         debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
 209 }
 210
 211 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
 212 /* FIXME: 8572 */
 213 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 214 {
 215         unsigned int pasr_cfg = 0;      /* Partial array self refresh config */
 216
 217         ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
 218         debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
 219 }
 220
 221 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 222
 223 #if !defined(CONFIG_SYS_FSL_DDR1)
 224 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
 225 {
 226 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
 227         if (dimm_params[0].n_ranks == 4)
 228                 return 1;
 229 #endif
 230
 231 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
 232         if ((dimm_params[0].n_ranks == 2) &&
 233                 (dimm_params[1].n_ranks == 2))
 234                 return 1;
 235
 236 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 237         if (dimm_params[0].n_ranks == 4)
 238                 return 1;
 239 #endif
 240 #endif
 241         return 0;
 242 }
 243
 244 /*
 245  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
 246  *
 247  * Avoid writing for DDR I.  The new PQ38 DDR controller
 248  * dreams up non-zero default values to be backwards compatible.
 249  */
 250 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 251                                 const memctl_options_t *popts,
 252                                 const dimm_params_t *dimm_params)
 253 {
 254         unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 255         unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
 256         /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
 257         unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
 258         unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
 259
 260         /* Active powerdown exit timing (tXARD and tXARDS). */
 261         unsigned char act_pd_exit_mclk;
 262         /* Precharge powerdown exit timing (tXP). */
 263         unsigned char pre_pd_exit_mclk;
 264         /* ODT powerdown exit timing (tAXPD). */
 265         unsigned char taxpd_mclk;
 266         /* Mode register set cycle time (tMRD). */
 267         unsigned char tmrd_mclk;
 268
 269 #ifdef CONFIG_SYS_FSL_DDR3
 270         /*
 271          * (tXARD and tXARDS). Empirical?
 272          * The DDR3 spec has not tXARD,
 273          * we use the tXP instead of it.
 274          * tXP=max(3nCK, 7.5ns) for DDR3.
 275          * spec has not the tAXPD, we use
 276          * tAXPD=1, need design to confirm.
 277          */
 278         int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
 279         unsigned int data_rate = get_ddr_freq(0);
 280         tmrd_mclk = 4;
 281         /* set the turnaround time */
 282
 283         /*
 284          * for single quad-rank DIMM and two dual-rank DIMMs
 285          * to avoid ODT overlap
 286          */
 287         if (avoid_odt_overlap(dimm_params)) {
 288                 twwt_mclk = 2;
 289                 trrt_mclk = 1;
 290         }
 291         /* for faster clock, need more time for data setup */
 292         trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
 293
 294         if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
 295                 twrt_mclk = 1;
 296
 297         if (popts->dynamic_power == 0) {        /* powerdown is not used */
 298                 act_pd_exit_mclk = 1;
 299                 pre_pd_exit_mclk = 1;
 300                 taxpd_mclk = 1;
 301         } else {
 302                 /* act_pd_exit_mclk = tXARD, see above */
 303                 act_pd_exit_mclk = picos_to_mclk(tXP);
 304                 /* Mode register MR0[A12] is '1' - fast exit */
 305                 pre_pd_exit_mclk = act_pd_exit_mclk;
 306                 taxpd_mclk = 1;
 307         }
 308 #else /* CONFIG_SYS_FSL_DDR2 */
 309         /*
 310          * (tXARD and tXARDS). Empirical?
 311          * tXARD = 2 for DDR2
 312          * tXP=2
 313          * tAXPD=8
 314          */
 315         act_pd_exit_mclk = 2;
 316         pre_pd_exit_mclk = 2;
 317         taxpd_mclk = 8;
 318         tmrd_mclk = 2;
 319 #endif
 320
 321         if (popts->trwt_override)
 322                 trwt_mclk = popts->trwt;
 323
 324         ddr->timing_cfg_0 = (0
 325                 | ((trwt_mclk & 0x3) << 30)     /* RWT */
 326                 | ((twrt_mclk & 0x3) << 28)     /* WRT */
 327                 | ((trrt_mclk & 0x3) << 26)     /* RRT */
 328                 | ((twwt_mclk & 0x3) << 24)     /* WWT */
 329                 | ((act_pd_exit_mclk & 0xf) << 20)  /* ACT_PD_EXIT */
 330                 | ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
 331                 | ((taxpd_mclk & 0xf) << 8)     /* ODT_PD_EXIT */
 332                 | ((tmrd_mclk & 0x1f) << 0)     /* MRS_CYC */
 333                 );
 334         debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 335 }
 336 #endif  /* defined(CONFIG_SYS_FSL_DDR2) */
 337
 338 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 339 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
 340                                const memctl_options_t *popts,
 341                                const common_timing_params_t *common_dimm,
 342                                unsigned int cas_latency,
 343                                unsigned int additive_latency)
 344 {
 345         /* Extended precharge to activate interval (tRP) */
 346         unsigned int ext_pretoact = 0;
 347         /* Extended Activate to precharge interval (tRAS) */
 348         unsigned int ext_acttopre = 0;
 349         /* Extended activate to read/write interval (tRCD) */
 350         unsigned int ext_acttorw = 0;
 351         /* Extended refresh recovery time (tRFC) */
 352         unsigned int ext_refrec;
 353         /* Extended MCAS latency from READ cmd */
 354         unsigned int ext_caslat = 0;
 355         /* Extended additive latency */
 356         unsigned int ext_add_lat = 0;
 357         /* Extended last data to precharge interval (tWR) */
 358         unsigned int ext_wrrec = 0;
 359         /* Control Adjust */
 360         unsigned int cntl_adj = 0;
 361
 362         ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4;
 363         ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4;
 364         ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4;
 365         ext_caslat = (2 * cas_latency - 1) >> 4;
 366         ext_add_lat = additive_latency >> 4;
 367         ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4;
 368         /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
 369         ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) +
 370                 (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
 371
 372         ddr->timing_cfg_3 = (0
 373                 | ((ext_pretoact & 0x1) << 28)
 374                 | ((ext_acttopre & 0x3) << 24)
 375                 | ((ext_acttorw & 0x1) << 22)
 376                 | ((ext_refrec & 0x1F) << 16)
 377                 | ((ext_caslat & 0x3) << 12)
 378                 | ((ext_add_lat & 0x1) << 10)
 379                 | ((ext_wrrec & 0x1) << 8)
 380                 | ((cntl_adj & 0x7) << 0)
 381                 );
 382         debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 383 }
 384
 385 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
 386 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 387                                const memctl_options_t *popts,
 388                                const common_timing_params_t *common_dimm,
 389                                unsigned int cas_latency)
 390 {
 391         /* Precharge-to-activate interval (tRP) */
 392         unsigned char pretoact_mclk;
 393         /* Activate to precharge interval (tRAS) */
 394         unsigned char acttopre_mclk;
 395         /*  Activate to read/write interval (tRCD) */
 396         unsigned char acttorw_mclk;
 397         /* CASLAT */
 398         unsigned char caslat_ctrl;
 399         /*  Refresh recovery time (tRFC) ; trfc_low */
 400         unsigned char refrec_ctrl;
 401         /* Last data to precharge minimum interval (tWR) */
 402         unsigned char wrrec_mclk;
 403         /* Activate-to-activate interval (tRRD) */
 404         unsigned char acttoact_mclk;
 405         /* Last write data pair to read command issue interval (tWTR) */
 406         unsigned char wrtord_mclk;
 407         /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
 408         static const u8 wrrec_table[] = {
 409                 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
 410
 411         pretoact_mclk = picos_to_mclk(common_dimm->trp_ps);
 412         acttopre_mclk = picos_to_mclk(common_dimm->tras_ps);
 413         acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps);
 414
 415         /*
 416          * Translate CAS Latency to a DDR controller field value:
 417          *
 418          *      CAS Lat DDR I   DDR II  Ctrl
 419          *      Clocks  SPD Bit SPD Bit Value
 420          *      ------- ------- ------- -----
 421          *      1.0     0               0001
 422          *      1.5     1               0010
 423          *      2.0     2       2       0011
 424          *      2.5     3               0100
 425          *      3.0     4       3       0101
 426          *      3.5     5               0110
 427          *      4.0             4       0111
 428          *      4.5                     1000
 429          *      5.0             5       1001
 430          */
 431 #if defined(CONFIG_SYS_FSL_DDR1)
 432         caslat_ctrl = (cas_latency + 1) & 0x07;
 433 #elif defined(CONFIG_SYS_FSL_DDR2)
 434         caslat_ctrl = 2 * cas_latency - 1;
 435 #else
 436         /*
 437          * if the CAS latency more than 8 cycle,
 438          * we need set extend bit for it at
 439          * TIMING_CFG_3[EXT_CASLAT]
 440          */
 441         caslat_ctrl = 2 * cas_latency - 1;
 442 #endif
 443
 444         refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8;
 445         wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
 446
 447         if (wrrec_mclk > 16)
 448                 printf("Error: WRREC doesn't support more than 16 clocks\n");
 449         else
 450                 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 451         if (popts->otf_burst_chop_en)
 452                 wrrec_mclk += 2;
 453
 454         acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps);
 455         /*
 456          * JEDEC has min requirement for tRRD
 457          */
 458 #if defined(CONFIG_SYS_FSL_DDR3)
 459         if (acttoact_mclk < 4)
 460                 acttoact_mclk = 4;
 461 #endif
 462         wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps);
 463         /*
 464          * JEDEC has some min requirements for tWTR
 465          */
 466 #if defined(CONFIG_SYS_FSL_DDR2)
 467         if (wrtord_mclk < 2)
 468                 wrtord_mclk = 2;
 469 #elif defined(CONFIG_SYS_FSL_DDR3)
 470         if (wrtord_mclk < 4)
 471                 wrtord_mclk = 4;
 472 #endif
 473         if (popts->otf_burst_chop_en)
 474                 wrtord_mclk += 2;
 475
 476         ddr->timing_cfg_1 = (0
 477                 | ((pretoact_mclk & 0x0F) << 28)
 478                 | ((acttopre_mclk & 0x0F) << 24)
 479                 | ((acttorw_mclk & 0xF) << 20)
 480                 | ((caslat_ctrl & 0xF) << 16)
 481                 | ((refrec_ctrl & 0xF) << 12)
 482                 | ((wrrec_mclk & 0x0F) << 8)
 483                 | ((acttoact_mclk & 0x0F) << 4)
 484                 | ((wrtord_mclk & 0x0F) << 0)
 485                 );
 486         debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 487 }
 488
 489 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
 490 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 491                                const memctl_options_t *popts,
 492                                const common_timing_params_t *common_dimm,
 493                                unsigned int cas_latency,
 494                                unsigned int additive_latency)
 495 {
 496         /* Additive latency */
 497         unsigned char add_lat_mclk;
 498         /* CAS-to-preamble override */
 499         unsigned short cpo;
 500         /* Write latency */
 501         unsigned char wr_lat;
 502         /*  Read to precharge (tRTP) */
 503         unsigned char rd_to_pre;
 504         /* Write command to write data strobe timing adjustment */
 505         unsigned char wr_data_delay;
 506         /* Minimum CKE pulse width (tCKE) */
 507         unsigned char cke_pls;
 508         /* Window for four activates (tFAW) */
 509         unsigned short four_act;
 510
 511         /* FIXME add check that this must be less than acttorw_mclk */
 512         add_lat_mclk = additive_latency;
 513         cpo = popts->cpo_override;
 514
 515 #if defined(CONFIG_SYS_FSL_DDR1)
 516         /*
 517          * This is a lie.  It should really be 1, but if it is
 518          * set to 1, bits overlap into the old controller's
 519          * otherwise unused ACSM field.  If we leave it 0, then
 520          * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
 521          */
 522         wr_lat = 0;
 523 #elif defined(CONFIG_SYS_FSL_DDR2)
 524         wr_lat = cas_latency - 1;
 525 #else
 526         wr_lat = compute_cas_write_latency();
 527 #endif
 528
 529         rd_to_pre = picos_to_mclk(common_dimm->trtp_ps);
 530         /*
 531          * JEDEC has some min requirements for tRTP
 532          */
 533 #if defined(CONFIG_SYS_FSL_DDR2)
 534         if (rd_to_pre  < 2)
 535                 rd_to_pre  = 2;
 536 #elif defined(CONFIG_SYS_FSL_DDR3)
 537         if (rd_to_pre < 4)
 538                 rd_to_pre = 4;
 539 #endif
 540         if (popts->otf_burst_chop_en)
 541                 rd_to_pre += 2; /* according to UM */
 542
 543         wr_data_delay = popts->write_data_delay;
 544         cke_pls = picos_to_mclk(popts->tcke_clock_pulse_width_ps);
 545         four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps);
 546
 547         ddr->timing_cfg_2 = (0
 548                 | ((add_lat_mclk & 0xf) << 28)
 549                 | ((cpo & 0x1f) << 23)
 550                 | ((wr_lat & 0xf) << 19)
 551                 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 552                 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 553                 | ((cke_pls & 0x7) << 6)
 554                 | ((four_act & 0x3f) << 0)
 555                 );
 556         debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 557 }
 558
 559 /* DDR SDRAM Register Control Word */
 560 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
 561                                const memctl_options_t *popts,
 562                                const common_timing_params_t *common_dimm)
 563 {
 564         if (common_dimm->all_dimms_registered &&
 565             !common_dimm->all_dimms_unbuffered) {
 566                 if (popts->rcw_override) {
 567                         ddr->ddr_sdram_rcw_1 = popts->rcw_1;
 568                         ddr->ddr_sdram_rcw_2 = popts->rcw_2;
 569                 } else {
 570                         ddr->ddr_sdram_rcw_1 =
 571                                 common_dimm->rcw[0] << 28 | \
 572                                 common_dimm->rcw[1] << 24 | \
 573                                 common_dimm->rcw[2] << 20 | \
 574                                 common_dimm->rcw[3] << 16 | \
 575                                 common_dimm->rcw[4] << 12 | \
 576                                 common_dimm->rcw[5] << 8 | \
 577                                 common_dimm->rcw[6] << 4 | \
 578                                 common_dimm->rcw[7];
 579                         ddr->ddr_sdram_rcw_2 =
 580                                 common_dimm->rcw[8] << 28 | \
 581                                 common_dimm->rcw[9] << 24 | \
 582                                 common_dimm->rcw[10] << 20 | \
 583                                 common_dimm->rcw[11] << 16 | \
 584                                 common_dimm->rcw[12] << 12 | \
 585                                 common_dimm->rcw[13] << 8 | \
 586                                 common_dimm->rcw[14] << 4 | \
 587                                 common_dimm->rcw[15];
 588                 }
 589                 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
 590                 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
 591         }
 592 }
 593
 594 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
 595 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 596                                const memctl_options_t *popts,
 597                                const common_timing_params_t *common_dimm)
 598 {
 599         unsigned int mem_en;            /* DDR SDRAM interface logic enable */
 600         unsigned int sren;              /* Self refresh enable (during sleep) */
 601         unsigned int ecc_en;            /* ECC enable. */
 602         unsigned int rd_en;             /* Registered DIMM enable */
 603         unsigned int sdram_type;        /* Type of SDRAM */
 604         unsigned int dyn_pwr;           /* Dynamic power management mode */
 605         unsigned int dbw;               /* DRAM dta bus width */
 606         unsigned int eight_be = 0;      /* 8-beat burst enable, DDR2 is zero */
 607         unsigned int ncap = 0;          /* Non-concurrent auto-precharge */
 608         unsigned int threet_en;         /* Enable 3T timing */
 609         unsigned int twot_en;           /* Enable 2T timing */
 610         unsigned int ba_intlv_ctl;      /* Bank (CS) interleaving control */
 611         unsigned int x32_en = 0;        /* x32 enable */
 612         unsigned int pchb8 = 0;         /* precharge bit 8 enable */
 613         unsigned int hse;               /* Global half strength override */
 614         unsigned int mem_halt = 0;      /* memory controller halt */
 615         unsigned int bi = 0;            /* Bypass initialization */
 616
 617         mem_en = 1;
 618         sren = popts->self_refresh_in_sleep;
 619         if (common_dimm->all_dimms_ecc_capable) {
 620                 /* Allow setting of ECC only if all DIMMs are ECC. */
 621                 ecc_en = popts->ecc_mode;
 622         } else {
 623                 ecc_en = 0;
 624         }
 625
 626         if (common_dimm->all_dimms_registered &&
 627             !common_dimm->all_dimms_unbuffered) {
 628                 rd_en = 1;
 629                 twot_en = 0;
 630         } else {
 631                 rd_en = 0;
 632                 twot_en = popts->twot_en;
 633         }
 634
 635         sdram_type = CONFIG_FSL_SDRAM_TYPE;
 636
 637         dyn_pwr = popts->dynamic_power;
 638         dbw = popts->data_bus_width;
 639         /* 8-beat burst enable DDR-III case
 640          * we must clear it when use the on-the-fly mode,
 641          * must set it when use the 32-bits bus mode.
 642          */
 643         if (sdram_type == SDRAM_TYPE_DDR3) {
 644                 if (popts->burst_length == DDR_BL8)
 645                         eight_be = 1;
 646                 if (popts->burst_length == DDR_OTF)
 647                         eight_be = 0;
 648                 if (dbw == 0x1)
 649                         eight_be = 1;
 650         }
 651
 652         threet_en = popts->threet_en;
 653         ba_intlv_ctl = popts->ba_intlv_ctl;
 654         hse = popts->half_strength_driver_enable;
 655
 656         ddr->ddr_sdram_cfg = (0
 657                         | ((mem_en & 0x1) << 31)
 658                         | ((sren & 0x1) << 30)
 659                         | ((ecc_en & 0x1) << 29)
 660                         | ((rd_en & 0x1) << 28)
 661                         | ((sdram_type & 0x7) << 24)
 662                         | ((dyn_pwr & 0x1) << 21)
 663                         | ((dbw & 0x3) << 19)
 664                         | ((eight_be & 0x1) << 18)
 665                         | ((ncap & 0x1) << 17)
 666                         | ((threet_en & 0x1) << 16)
 667                         | ((twot_en & 0x1) << 15)
 668                         | ((ba_intlv_ctl & 0x7F) << 8)
 669                         | ((x32_en & 0x1) << 5)
 670                         | ((pchb8 & 0x1) << 4)
 671                         | ((hse & 0x1) << 3)
 672                         | ((mem_halt & 0x1) << 1)
 673                         | ((bi & 0x1) << 0)
 674                         );
 675         debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 676 }
 677
 678 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
 679 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 680                                const memctl_options_t *popts,
 681                                const unsigned int unq_mrs_en)
 682 {
 683         unsigned int frc_sr = 0;        /* Force self refresh */
 684         unsigned int sr_ie = 0;         /* Self-refresh interrupt enable */
 685         unsigned int dll_rst_dis;       /* DLL reset disable */
 686         unsigned int dqs_cfg;           /* DQS configuration */
 687         unsigned int odt_cfg = 0;       /* ODT configuration */
 688         unsigned int num_pr;            /* Number of posted refreshes */
 689         unsigned int slow = 0;          /* DDR will be run less than 1250 */
 690         unsigned int x4_en = 0;         /* x4 DRAM enable */
 691         unsigned int obc_cfg;           /* On-The-Fly Burst Chop Cfg */
 692         unsigned int ap_en;             /* Address Parity Enable */
 693         unsigned int d_init;            /* DRAM data initialization */
 694         unsigned int rcw_en = 0;        /* Register Control Word Enable */
 695         unsigned int md_en = 0;         /* Mirrored DIMM Enable */
 696         unsigned int qd_en = 0;         /* quad-rank DIMM Enable */
 697         int i;
 698
 699         dll_rst_dis = 1;        /* Make this configurable */
 700         dqs_cfg = popts->dqs_config;
 701         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 702                 if (popts->cs_local_opts[i].odt_rd_cfg
 703                         || popts->cs_local_opts[i].odt_wr_cfg) {
 704                         odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
 705                         break;
 706                 }
 707         }
 708
 709         num_pr = 1;     /* Make this configurable */
 710
 711         /*
 712          * 8572 manual says
 713          *     {TIMING_CFG_1[PRETOACT]
 714          *      + [DDR_SDRAM_CFG_2[NUM_PR]
 715          *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
 716          *      << DDR_SDRAM_INTERVAL[REFINT]
 717          */
 718 #if defined(CONFIG_SYS_FSL_DDR3)
 719         obc_cfg = popts->otf_burst_chop_en;
 720 #else
 721         obc_cfg = 0;
 722 #endif
 723
 724 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
 725         slow = get_ddr_freq(0) < 1249000000;
 726 #endif
 727
 728         if (popts->registered_dimm_en) {
 729                 rcw_en = 1;
 730                 ap_en = popts->ap_en;
 731         } else {
 732                 ap_en = 0;
 733         }
 734
 735         x4_en = popts->x4_en ? 1 : 0;
 736
 737 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 738         /* Use the DDR controller to auto initialize memory. */
 739         d_init = popts->ecc_init_using_memctl;
 740         ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 741         debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 742 #else
 743         /* Memory will be initialized via DMA, or not at all. */
 744         d_init = 0;
 745 #endif
 746
 747 #if defined(CONFIG_SYS_FSL_DDR3)
 748         md_en = popts->mirrored_dimm;
 749 #endif
 750         qd_en = popts->quad_rank_present ? 1 : 0;
 751         ddr->ddr_sdram_cfg_2 = (0
 752                 | ((frc_sr & 0x1) << 31)
 753                 | ((sr_ie & 0x1) << 30)
 754                 | ((dll_rst_dis & 0x1) << 29)
 755                 | ((dqs_cfg & 0x3) << 26)
 756                 | ((odt_cfg & 0x3) << 21)
 757                 | ((num_pr & 0xf) << 12)
 758                 | ((slow & 1) << 11)
 759                 | (x4_en << 10)
 760                 | (qd_en << 9)
 761                 | (unq_mrs_en << 8)
 762                 | ((obc_cfg & 0x1) << 6)
 763                 | ((ap_en & 0x1) << 5)
 764                 | ((d_init & 0x1) << 4)
 765                 | ((rcw_en & 0x1) << 2)
 766                 | ((md_en & 0x1) << 0)
 767                 );
 768         debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
 769 }
 770
 771 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 772 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 773                                 const memctl_options_t *popts,
 774                                 const common_timing_params_t *common_dimm,
 775                                 const unsigned int unq_mrs_en)
 776 {
 777         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 778         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 779
 780 #if defined(CONFIG_SYS_FSL_DDR3)
 781         int i;
 782         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
 783         unsigned int srt = 0;   /* self-refresh temerature, normal range */
 784         unsigned int asr = 0;   /* auto self-refresh disable */
 785         unsigned int cwl = compute_cas_write_latency() - 5;
 786         unsigned int pasr = 0;  /* partial array self refresh disable */
 787
 788         if (popts->rtt_override)
 789                 rtt_wr = popts->rtt_wr_override_value;
 790         else
 791                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
 792
 793         if (common_dimm->extended_op_srt)
 794                 srt = common_dimm->extended_op_srt;
 795
 796         esdmode2 = (0
 797                 | ((rtt_wr & 0x3) << 9)
 798                 | ((srt & 0x1) << 7)
 799                 | ((asr & 0x1) << 6)
 800                 | ((cwl & 0x7) << 3)
 801                 | ((pasr & 0x7) << 0));
 802 #endif
 803         ddr->ddr_sdram_mode_2 = (0
 804                                  | ((esdmode2 & 0xFFFF) << 16)
 805                                  | ((esdmode3 & 0xFFFF) << 0)
 806                                  );
 807         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
 808
 809 #ifdef CONFIG_SYS_FSL_DDR3
 810         if (unq_mrs_en) {       /* unique mode registers are supported */
 811                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 812                         if (popts->rtt_override)
 813                                 rtt_wr = popts->rtt_wr_override_value;
 814                         else
 815                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
 816
 817                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
 818                         esdmode2 |= (rtt_wr & 0x3) << 9;
 819                         switch (i) {
 820                         case 1:
 821                                 ddr->ddr_sdram_mode_4 = (0
 822                                         | ((esdmode2 & 0xFFFF) << 16)
 823                                         | ((esdmode3 & 0xFFFF) << 0)
 824                                         );
 825                                 break;
 826                         case 2:
 827                                 ddr->ddr_sdram_mode_6 = (0
 828                                         | ((esdmode2 & 0xFFFF) << 16)
 829                                         | ((esdmode3 & 0xFFFF) << 0)
 830                                         );
 831                                 break;
 832                         case 3:
 833                                 ddr->ddr_sdram_mode_8 = (0
 834                                         | ((esdmode2 & 0xFFFF) << 16)
 835                                         | ((esdmode3 & 0xFFFF) << 0)
 836                                         );
 837                                 break;
 838                         }
 839                 }
 840                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
 841                         ddr->ddr_sdram_mode_4);
 842                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
 843                         ddr->ddr_sdram_mode_6);
 844                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
 845                         ddr->ddr_sdram_mode_8);
 846         }
 847 #endif
 848 }
 849
 850 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
 851 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
 852                                const memctl_options_t *popts,
 853                                const common_timing_params_t *common_dimm)
 854 {
 855         unsigned int refint;    /* Refresh interval */
 856         unsigned int bstopre;   /* Precharge interval */
 857
 858         refint = picos_to_mclk(common_dimm->refresh_rate_ps);
 859
 860         bstopre = popts->bstopre;
 861
 862         /* refint field used 0x3FFF in earlier controllers */
 863         ddr->ddr_sdram_interval = (0
 864                                    | ((refint & 0xFFFF) << 16)
 865                                    | ((bstopre & 0x3FFF) << 0)
 866                                    );
 867         debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
 868 }
 869
 870 #if defined(CONFIG_SYS_FSL_DDR3)
 871 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
 872 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 873                                const memctl_options_t *popts,
 874                                const common_timing_params_t *common_dimm,
 875                                unsigned int cas_latency,
 876                                unsigned int additive_latency,
 877                                const unsigned int unq_mrs_en)
 878 {
 879         unsigned short esdmode;         /* Extended SDRAM mode */
 880         unsigned short sdmode;          /* SDRAM mode */
 881
 882         /* Mode Register - MR1 */
 883         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
 884         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
 885         unsigned int rtt;
 886         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
 887         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
 888         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
 889         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
 890                                                        1=Disable (Test/Debug) */
 891
 892         /* Mode Register - MR0 */
 893         unsigned int dll_on;    /* DLL control for precharge PD, 0=off, 1=on */
 894         unsigned int wr = 0;    /* Write Recovery */
 895         unsigned int dll_rst;   /* DLL Reset */
 896         unsigned int mode;      /* Normal=0 or Test=1 */
 897         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
 898         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
 899         unsigned int bt;
 900         unsigned int bl;        /* BL: Burst Length */
 901
 902         unsigned int wr_mclk;
 903         /*
 904          * DDR_SDRAM_MODE doesn't support 9,11,13,15
 905          * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
 906          * for this table
 907          */
 908         static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
 909
 910         const unsigned int mclk_ps = get_memory_clk_period_ps();
 911         int i;
 912
 913         if (popts->rtt_override)
 914                 rtt = popts->rtt_override_value;
 915         else
 916                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
 917
 918         if (additive_latency == (cas_latency - 1))
 919                 al = 1;
 920         if (additive_latency == (cas_latency - 2))
 921                 al = 2;
 922
 923         if (popts->quad_rank_present)
 924                 dic = 1;        /* output driver impedance 240/7 ohm */
 925
 926         /*
 927          * The esdmode value will also be used for writing
 928          * MR1 during write leveling for DDR3, although the
 929          * bits specifically related to the write leveling
 930          * scheme will be handled automatically by the DDR
 931          * controller. so we set the wrlvl_en = 0 here.
 932          */
 933         esdmode = (0
 934                 | ((qoff & 0x1) << 12)
 935                 | ((tdqs_en & 0x1) << 11)
 936                 | ((rtt & 0x4) << 7)   /* rtt field is split */
 937                 | ((wrlvl_en & 0x1) << 7)
 938                 | ((rtt & 0x2) << 5)   /* rtt field is split */
 939                 | ((dic & 0x2) << 4)   /* DIC field is split */
 940                 | ((al & 0x3) << 3)
 941                 | ((rtt & 0x1) << 2)  /* rtt field is split */
 942                 | ((dic & 0x1) << 1)   /* DIC field is split */
 943                 | ((dll_en & 0x1) << 0)
 944                 );
 945
 946         /*
 947          * DLL control for precharge PD
 948          * 0=slow exit DLL off (tXPDLL)
 949          * 1=fast exit DLL on (tXP)
 950          */
 951         dll_on = 1;
 952
 953         wr_mclk = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps;
 954         if (wr_mclk <= 16) {
 955                 wr = wr_table[wr_mclk - 5];
 956         } else {
 957                 printf("Error: unsupported write recovery for mode register "
 958                        "wr_mclk = %d\n", wr_mclk);
 959         }
 960
 961         dll_rst = 0;    /* dll no reset */
 962         mode = 0;       /* normal mode */
 963
 964         /* look up table to get the cas latency bits */
 965         if (cas_latency >= 5 && cas_latency <= 16) {
 966                 unsigned char cas_latency_table[] = {
 967                         0x2,    /* 5 clocks */
 968                         0x4,    /* 6 clocks */
 969                         0x6,    /* 7 clocks */
 970                         0x8,    /* 8 clocks */
 971                         0xa,    /* 9 clocks */
 972                         0xc,    /* 10 clocks */
 973                         0xe,    /* 11 clocks */
 974                         0x1,    /* 12 clocks */
 975                         0x3,    /* 13 clocks */
 976                         0x5,    /* 14 clocks */
 977                         0x7,    /* 15 clocks */
 978                         0x9,    /* 16 clocks */
 979                 };
 980                 caslat = cas_latency_table[cas_latency - 5];
 981         } else {
 982                 printf("Error: unsupported cas latency for mode register\n");
 983         }
 984
 985         bt = 0; /* Nibble sequential */
 986
 987         switch (popts->burst_length) {
 988         case DDR_BL8:
 989                 bl = 0;
 990                 break;
 991         case DDR_OTF:
 992                 bl = 1;
 993                 break;
 994         case DDR_BC4:
 995                 bl = 2;
 996                 break;
 997         default:
 998                 printf("Error: invalid burst length of %u specified. "
 999                         " Defaulting to on-the-fly BC4 or BL8 beats.\n",
1000                         popts->burst_length);
1001                 bl = 1;
1002                 break;
1003         }
1004
1005         sdmode = (0
1006                   | ((dll_on & 0x1) << 12)
1007                   | ((wr & 0x7) << 9)
1008                   | ((dll_rst & 0x1) << 8)
1009                   | ((mode & 0x1) << 7)
1010                   | (((caslat >> 1) & 0x7) << 4)
1011                   | ((bt & 0x1) << 3)
1012                   | ((caslat & 1) << 2)
1013                   | ((bl & 0x3) << 0)
1014                   );
1015
1016         ddr->ddr_sdram_mode = (0
1017                                | ((esdmode & 0xFFFF) << 16)
1018                                | ((sdmode & 0xFFFF) << 0)
1019                                );
1020
1021         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1022
1023         if (unq_mrs_en) {       /* unique mode registers are supported */
1024                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1025                         if (popts->rtt_override)
1026                                 rtt = popts->rtt_override_value;
1027                         else
1028                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1029
1030                         esdmode &= 0xFDBB;      /* clear bit 9,6,2 */
1031                         esdmode |= (0
1032                                 | ((rtt & 0x4) << 7)   /* rtt field is split */
1033                                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1034                                 | ((rtt & 0x1) << 2)  /* rtt field is split */
1035                                 );
1036                         switch (i) {
1037                         case 1:
1038                                 ddr->ddr_sdram_mode_3 = (0
1039                                        | ((esdmode & 0xFFFF) << 16)
1040                                        | ((sdmode & 0xFFFF) << 0)
1041                                        );
1042                                 break;
1043                         case 2:
1044                                 ddr->ddr_sdram_mode_5 = (0
1045                                        | ((esdmode & 0xFFFF) << 16)
1046                                        | ((sdmode & 0xFFFF) << 0)
1047                                        );
1048                                 break;
1049                         case 3:
1050                                 ddr->ddr_sdram_mode_7 = (0
1051                                        | ((esdmode & 0xFFFF) << 16)
1052                                        | ((sdmode & 0xFFFF) << 0)
1053                                        );
1054                                 break;
1055                         }
1056                 }
1057                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1058                         ddr->ddr_sdram_mode_3);
1059                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1060                         ddr->ddr_sdram_mode_5);
1061                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1062                         ddr->ddr_sdram_mode_5);
1063         }
1064 }
1065
1066 #else /* !CONFIG_SYS_FSL_DDR3 */
1067
1068 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1069 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1070                                const memctl_options_t *popts,
1071                                const common_timing_params_t *common_dimm,
1072                                unsigned int cas_latency,
1073                                unsigned int additive_latency,
1074                                const unsigned int unq_mrs_en)
1075 {
1076         unsigned short esdmode;         /* Extended SDRAM mode */
1077         unsigned short sdmode;          /* SDRAM mode */
1078
1079         /*
1080          * FIXME: This ought to be pre-calculated in a
1081          * technology-specific routine,
1082          * e.g. compute_DDR2_mode_register(), and then the
1083          * sdmode and esdmode passed in as part of common_dimm.
1084          */
1085
1086         /* Extended Mode Register */
1087         unsigned int mrs = 0;           /* Mode Register Set */
1088         unsigned int outputs = 0;       /* 0=Enabled, 1=Disabled */
1089         unsigned int rdqs_en = 0;       /* RDQS Enable: 0=no, 1=yes */
1090         unsigned int dqs_en = 0;        /* DQS# Enable: 0=enable, 1=disable */
1091         unsigned int ocd = 0;           /* 0x0=OCD not supported,
1092                                            0x7=OCD default state */
1093         unsigned int rtt;
1094         unsigned int al;                /* Posted CAS# additive latency (AL) */
1095         unsigned int ods = 0;           /* Output Drive Strength:
1096                                                 0 = Full strength (18ohm)
1097                                                 1 = Reduced strength (4ohm) */
1098         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1099                                                        1=Disable (Test/Debug) */
1100
1101         /* Mode Register (MR) */
1102         unsigned int mr;        /* Mode Register Definition */
1103         unsigned int pd;        /* Power-Down Mode */
1104         unsigned int wr;        /* Write Recovery */
1105         unsigned int dll_res;   /* DLL Reset */
1106         unsigned int mode;      /* Normal=0 or Test=1 */
1107         unsigned int caslat = 0;/* CAS# latency */
1108         /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1109         unsigned int bt;
1110         unsigned int bl;        /* BL: Burst Length */
1111
1112 #if defined(CONFIG_SYS_FSL_DDR2)
1113         const unsigned int mclk_ps = get_memory_clk_period_ps();
1114 #endif
1115         dqs_en = !popts->dqs_config;
1116         rtt = fsl_ddr_get_rtt();
1117
1118         al = additive_latency;
1119
1120         esdmode = (0
1121                 | ((mrs & 0x3) << 14)
1122                 | ((outputs & 0x1) << 12)
1123                 | ((rdqs_en & 0x1) << 11)
1124                 | ((dqs_en & 0x1) << 10)
1125                 | ((ocd & 0x7) << 7)
1126                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1127                 | ((al & 0x7) << 3)
1128                 | ((rtt & 0x1) << 2)   /* rtt field is split */
1129                 | ((ods & 0x1) << 1)
1130                 | ((dll_en & 0x1) << 0)
1131                 );
1132
1133         mr = 0;          /* FIXME: CHECKME */
1134
1135         /*
1136          * 0 = Fast Exit (Normal)
1137          * 1 = Slow Exit (Low Power)
1138          */
1139         pd = 0;
1140
1141 #if defined(CONFIG_SYS_FSL_DDR1)
1142         wr = 0;       /* Historical */
1143 #elif defined(CONFIG_SYS_FSL_DDR2)
1144         wr = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps - 1;
1145 #endif
1146         dll_res = 0;
1147         mode = 0;
1148
1149 #if defined(CONFIG_SYS_FSL_DDR1)
1150         if (1 <= cas_latency && cas_latency <= 4) {
1151                 unsigned char mode_caslat_table[4] = {
1152                         0x5,    /* 1.5 clocks */
1153                         0x2,    /* 2.0 clocks */
1154                         0x6,    /* 2.5 clocks */
1155                         0x3     /* 3.0 clocks */
1156                 };
1157                 caslat = mode_caslat_table[cas_latency - 1];
1158         } else {
1159                 printf("Warning: unknown cas_latency %d\n", cas_latency);
1160         }
1161 #elif defined(CONFIG_SYS_FSL_DDR2)
1162         caslat = cas_latency;
1163 #endif
1164         bt = 0;
1165
1166         switch (popts->burst_length) {
1167         case DDR_BL4:
1168                 bl = 2;
1169                 break;
1170         case DDR_BL8:
1171                 bl = 3;
1172                 break;
1173         default:
1174                 printf("Error: invalid burst length of %u specified. "
1175                         " Defaulting to 4 beats.\n",
1176                         popts->burst_length);
1177                 bl = 2;
1178                 break;
1179         }
1180
1181         sdmode = (0
1182                   | ((mr & 0x3) << 14)
1183                   | ((pd & 0x1) << 12)
1184                   | ((wr & 0x7) << 9)
1185                   | ((dll_res & 0x1) << 8)
1186                   | ((mode & 0x1) << 7)
1187                   | ((caslat & 0x7) << 4)
1188                   | ((bt & 0x1) << 3)
1189                   | ((bl & 0x7) << 0)
1190                   );
1191
1192         ddr->ddr_sdram_mode = (0
1193                                | ((esdmode & 0xFFFF) << 16)
1194                                | ((sdmode & 0xFFFF) << 0)
1195                                );
1196         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1197 }
1198 #endif
1199
1200 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1201 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1202 {
1203         unsigned int init_value;        /* Initialization value */
1204
1205 #ifdef CONFIG_MEM_INIT_VALUE
1206         init_value = CONFIG_MEM_INIT_VALUE;
1207 #else
1208         init_value = 0xDEADBEEF;
1209 #endif
1210         ddr->ddr_data_init = init_value;
1211 }
1212
1213 /*
1214  * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1215  * The old controller on the 8540/60 doesn't have this register.
1216  * Hope it's OK to set it (to 0) anyway.
1217  */
1218 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1219                                          const memctl_options_t *popts)
1220 {
1221         unsigned int clk_adjust;        /* Clock adjust */
1222
1223         clk_adjust = popts->clk_adjust;
1224         ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
1225         debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1226 }
1227
1228 /* DDR Initialization Address (DDR_INIT_ADDR) */
1229 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1230 {
1231         unsigned int init_addr = 0;     /* Initialization address */
1232
1233         ddr->ddr_init_addr = init_addr;
1234 }
1235
1236 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1237 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1238 {
1239         unsigned int uia = 0;   /* Use initialization address */
1240         unsigned int init_ext_addr = 0; /* Initialization address */
1241
1242         ddr->ddr_init_ext_addr = (0
1243                                   | ((uia & 0x1) << 31)
1244                                   | (init_ext_addr & 0xF)
1245                                   );
1246 }
1247
1248 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1249 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1250                                 const memctl_options_t *popts)
1251 {
1252         unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1253         unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1254         unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1255         unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1256         unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1257
1258 #if defined(CONFIG_SYS_FSL_DDR3)
1259         if (popts->burst_length == DDR_BL8) {
1260                 /* We set BL/2 for fixed BL8 */
1261                 rrt = 0;        /* BL/2 clocks */
1262                 wwt = 0;        /* BL/2 clocks */
1263         } else {
1264                 /* We need to set BL/2 + 2 to BC4 and OTF */
1265                 rrt = 2;        /* BL/2 + 2 clocks */
1266                 wwt = 2;        /* BL/2 + 2 clocks */
1267         }
1268         dll_lock = 1;   /* tDLLK = 512 clocks from spec */
1269 #endif
1270         ddr->timing_cfg_4 = (0
1271                              | ((rwt & 0xf) << 28)
1272                              | ((wrt & 0xf) << 24)
1273                              | ((rrt & 0xf) << 20)
1274                              | ((wwt & 0xf) << 16)
1275                              | (dll_lock & 0x3)
1276                              );
1277         debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1278 }
1279
1280 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1281 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1282 {
1283         unsigned int rodt_on = 0;       /* Read to ODT on */
1284         unsigned int rodt_off = 0;      /* Read to ODT off */
1285         unsigned int wodt_on = 0;       /* Write to ODT on */
1286         unsigned int wodt_off = 0;      /* Write to ODT off */
1287
1288 #if defined(CONFIG_SYS_FSL_DDR3)
1289         /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1290         rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
1291         rodt_off = 4;   /*  4 clocks */
1292         wodt_on = 1;    /*  1 clocks */
1293         wodt_off = 4;   /*  4 clocks */
1294 #endif
1295
1296         ddr->timing_cfg_5 = (0
1297                              | ((rodt_on & 0x1f) << 24)
1298                              | ((rodt_off & 0x7) << 20)
1299                              | ((wodt_on & 0x1f) << 12)
1300                              | ((wodt_off & 0x7) << 8)
1301                              );
1302         debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1303 }
1304
1305 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
1306 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
1307 {
1308         unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1309         /* Normal Operation Full Calibration Time (tZQoper) */
1310         unsigned int zqoper = 0;
1311         /* Normal Operation Short Calibration Time (tZQCS) */
1312         unsigned int zqcs = 0;
1313
1314         if (zq_en) {
1315                 zqinit = 9;     /* 512 clocks */
1316                 zqoper = 8;     /* 256 clocks */
1317                 zqcs = 6;       /* 64 clocks */
1318         }
1319
1320         ddr->ddr_zq_cntl = (0
1321                             | ((zq_en & 0x1) << 31)
1322                             | ((zqinit & 0xF) << 24)
1323                             | ((zqoper & 0xF) << 16)
1324                             | ((zqcs & 0xF) << 8)
1325                             );
1326         debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
1327 }
1328
1329 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
1330 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1331                                 const memctl_options_t *popts)
1332 {
1333         /*
1334          * First DQS pulse rising edge after margining mode
1335          * is programmed (tWL_MRD)
1336          */
1337         unsigned int wrlvl_mrd = 0;
1338         /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1339         unsigned int wrlvl_odten = 0;
1340         /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1341         unsigned int wrlvl_dqsen = 0;
1342         /* WRLVL_SMPL: Write leveling sample time */
1343         unsigned int wrlvl_smpl = 0;
1344         /* WRLVL_WLR: Write leveling repeition time */
1345         unsigned int wrlvl_wlr = 0;
1346         /* WRLVL_START: Write leveling start time */
1347         unsigned int wrlvl_start = 0;
1348
1349         /* suggest enable write leveling for DDR3 due to fly-by topology */
1350         if (wrlvl_en) {
1351                 /* tWL_MRD min = 40 nCK, we set it 64 */
1352                 wrlvl_mrd = 0x6;
1353                 /* tWL_ODTEN 128 */
1354                 wrlvl_odten = 0x7;
1355                 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1356                 wrlvl_dqsen = 0x5;
1357                 /*
1358                  * Write leveling sample time at least need 6 clocks
1359                  * higher than tWLO to allow enough time for progagation
1360                  * delay and sampling the prime data bits.
1361                  */
1362                 wrlvl_smpl = 0xf;
1363                 /*
1364                  * Write leveling repetition time
1365                  * at least tWLO + 6 clocks clocks
1366                  * we set it 64
1367                  */
1368                 wrlvl_wlr = 0x6;
1369                 /*
1370                  * Write leveling start time
1371                  * The value use for the DQS_ADJUST for the first sample
1372                  * when write leveling is enabled. It probably needs to be
1373                  * overriden per platform.
1374                  */
1375                 wrlvl_start = 0x8;
1376                 /*
1377                  * Override the write leveling sample and start time
1378                  * according to specific board
1379                  */
1380                 if (popts->wrlvl_override) {
1381                         wrlvl_smpl = popts->wrlvl_sample;
1382                         wrlvl_start = popts->wrlvl_start;
1383                 }
1384         }
1385
1386         ddr->ddr_wrlvl_cntl = (0
1387                                | ((wrlvl_en & 0x1) << 31)
1388                                | ((wrlvl_mrd & 0x7) << 24)
1389                                | ((wrlvl_odten & 0x7) << 20)
1390                                | ((wrlvl_dqsen & 0x7) << 16)
1391                                | ((wrlvl_smpl & 0xf) << 12)
1392                                | ((wrlvl_wlr & 0x7) << 8)
1393                                | ((wrlvl_start & 0x1F) << 0)
1394                                );
1395         debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
1396         ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
1397         debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
1398         ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
1399         debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
1400
1401 }
1402
1403 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
1404 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
1405 {
1406         /* Self Refresh Idle Threshold */
1407         ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1408 }
1409
1410 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1411 {
1412         if (popts->addr_hash) {
1413                 ddr->ddr_eor = 0x40000000;      /* address hash enable */
1414                 puts("Address hashing enabled.\n");
1415         }
1416 }
1417
1418 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1419 {
1420         ddr->ddr_cdr1 = popts->ddr_cdr1;
1421         debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
1422 }
1423
1424 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1425 {
1426         ddr->ddr_cdr2 = popts->ddr_cdr2;
1427         debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
1428 }
1429
1430 unsigned int
1431 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1432 {
1433         unsigned int res = 0;
1434
1435         /*
1436          * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1437          * not set at the same time.
1438          */
1439         if (ddr->ddr_sdram_cfg & 0x10000000
1440             && ddr->ddr_sdram_cfg & 0x00008000) {
1441                 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1442                                 " should not be set at the same time.\n");
1443                 res++;
1444         }
1445
1446         return res;
1447 }
1448
1449 unsigned int
1450 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1451                                fsl_ddr_cfg_regs_t *ddr,
1452                                const common_timing_params_t *common_dimm,
1453                                const dimm_params_t *dimm_params,
1454                                unsigned int dbw_cap_adj,
1455                                unsigned int size_only)
1456 {
1457         unsigned int i;
1458         unsigned int cas_latency;
1459         unsigned int additive_latency;
1460         unsigned int sr_it;
1461         unsigned int zq_en;
1462         unsigned int wrlvl_en;
1463         unsigned int ip_rev = 0;
1464         unsigned int unq_mrs_en = 0;
1465         int cs_en = 1;
1466
1467         memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1468
1469         if (common_dimm == NULL) {
1470                 printf("Error: subset DIMM params struct null pointer\n");
1471                 return 1;
1472         }
1473
1474         /*
1475          * Process overrides first.
1476          *
1477          * FIXME: somehow add dereated caslat to this
1478          */
1479         cas_latency = (popts->cas_latency_override)
1480                 ? popts->cas_latency_override_value
1481                 : common_dimm->lowest_common_SPD_caslat;
1482
1483         additive_latency = (popts->additive_latency_override)
1484                 ? popts->additive_latency_override_value
1485                 : common_dimm->additive_latency;
1486
1487         sr_it = (popts->auto_self_refresh_en)
1488                 ? popts->sr_it
1489                 : 0;
1490         /* ZQ calibration */
1491         zq_en = (popts->zq_en) ? 1 : 0;
1492         /* write leveling */
1493         wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
1494
1495         /* Chip Select Memory Bounds (CSn_BNDS) */
1496         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1497                 unsigned long long ea, sa;
1498                 unsigned int cs_per_dimm
1499                         = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
1500                 unsigned int dimm_number
1501                         = i / cs_per_dimm;
1502                 unsigned long long rank_density
1503                         = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
1504
1505                 if (dimm_params[dimm_number].n_ranks == 0) {
1506                         debug("Skipping setup of CS%u "
1507                                 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
1508                         continue;
1509                 }
1510                 if (popts->memctl_interleaving) {
1511                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1512                         case FSL_DDR_CS0_CS1_CS2_CS3:
1513                                 break;
1514                         case FSL_DDR_CS0_CS1:
1515                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1516                                 if (i > 1)
1517                                         cs_en = 0;
1518                                 break;
1519                         case FSL_DDR_CS2_CS3:
1520                         default:
1521                                 if (i > 0)
1522                                         cs_en = 0;
1523                                 break;
1524                         }
1525                         sa = common_dimm->base_address;
1526                         ea = sa + common_dimm->total_mem - 1;
1527                 } else if (!popts->memctl_interleaving) {
1528                         /*
1529                          * If memory interleaving between controllers is NOT
1530                          * enabled, the starting address for each memory
1531                          * controller is distinct.  However, because rank
1532                          * interleaving is enabled, the starting and ending
1533                          * addresses of the total memory on that memory
1534                          * controller needs to be programmed into its
1535                          * respective CS0_BNDS.
1536                          */
1537                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1538                         case FSL_DDR_CS0_CS1_CS2_CS3:
1539                                 sa = common_dimm->base_address;
1540                                 ea = sa + common_dimm->total_mem - 1;
1541                                 break;
1542                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1543                                 if ((i >= 2) && (dimm_number == 0)) {
1544                                         sa = dimm_params[dimm_number].base_address +
1545                                               2 * rank_density;
1546                                         ea = sa + 2 * rank_density - 1;
1547                                 } else {
1548                                         sa = dimm_params[dimm_number].base_address;
1549                                         ea = sa + 2 * rank_density - 1;
1550                                 }
1551                                 break;
1552                         case FSL_DDR_CS0_CS1:
1553                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1554                                         sa = dimm_params[dimm_number].base_address;
1555                                         ea = sa + rank_density - 1;
1556                                         if (i != 1)
1557                                                 sa += (i % cs_per_dimm) * rank_density;
1558                                         ea += (i % cs_per_dimm) * rank_density;
1559                                 } else {
1560                                         sa = 0;
1561                                         ea = 0;
1562                                 }
1563                                 if (i == 0)
1564                                         ea += rank_density;
1565                                 break;
1566                         case FSL_DDR_CS2_CS3:
1567                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1568                                         sa = dimm_params[dimm_number].base_address;
1569                                         ea = sa + rank_density - 1;
1570                                         if (i != 3)
1571                                                 sa += (i % cs_per_dimm) * rank_density;
1572                                         ea += (i % cs_per_dimm) * rank_density;
1573                                 } else {
1574                                         sa = 0;
1575                                         ea = 0;
1576                                 }
1577                                 if (i == 2)
1578                                         ea += (rank_density >> dbw_cap_adj);
1579                                 break;
1580                         default:  /* No bank(chip-select) interleaving */
1581                                 sa = dimm_params[dimm_number].base_address;
1582                                 ea = sa + rank_density - 1;
1583                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1584                                         sa += (i % cs_per_dimm) * rank_density;
1585                                         ea += (i % cs_per_dimm) * rank_density;
1586                                 } else {
1587                                         sa = 0;
1588                                         ea = 0;
1589                                 }
1590                                 break;
1591                         }
1592                 }
1593
1594                 sa >>= 24;
1595                 ea >>= 24;
1596
1597                 if (cs_en) {
1598                         ddr->cs[i].bnds = (0
1599                                 | ((sa & 0xffff) << 16) /* starting address */
1600                                 | ((ea & 0xffff) << 0)  /* ending address */
1601                                 );
1602                 } else {
1603                         /* setting bnds to 0xffffffff for inactive CS */
1604                         ddr->cs[i].bnds = 0xffffffff;
1605                 }
1606
1607                 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1608                 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1609                 set_csn_config_2(i, ddr);
1610         }
1611
1612         /*
1613          * In the case we only need to compute the ddr sdram size, we only need
1614          * to set csn registers, so return from here.
1615          */
1616         if (size_only)
1617                 return 0;
1618
1619         set_ddr_eor(ddr, popts);
1620
1621 #if !defined(CONFIG_SYS_FSL_DDR1)
1622         set_timing_cfg_0(ddr, popts, dimm_params);
1623 #endif
1624
1625         set_timing_cfg_3(ddr, popts, common_dimm, cas_latency,
1626                          additive_latency);
1627         set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
1628         set_timing_cfg_2(ddr, popts, common_dimm,
1629                                 cas_latency, additive_latency);
1630
1631         set_ddr_cdr1(ddr, popts);
1632         set_ddr_cdr2(ddr, popts);
1633         set_ddr_sdram_cfg(ddr, popts, common_dimm);
1634         ip_rev = fsl_ddr_get_version();
1635         if (ip_rev > 0x40400)
1636                 unq_mrs_en = 1;
1637
1638         set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
1639         set_ddr_sdram_mode(ddr, popts, common_dimm,
1640                                 cas_latency, additive_latency, unq_mrs_en);
1641         set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en);
1642         set_ddr_sdram_interval(ddr, popts, common_dimm);
1643         set_ddr_data_init(ddr);
1644         set_ddr_sdram_clk_cntl(ddr, popts);
1645         set_ddr_init_addr(ddr);
1646         set_ddr_init_ext_addr(ddr);
1647         set_timing_cfg_4(ddr, popts);
1648         set_timing_cfg_5(ddr, cas_latency);
1649
1650         set_ddr_zq_cntl(ddr, zq_en);
1651         set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
1652
1653         set_ddr_sr_cntr(ddr, sr_it);
1654
1655         set_ddr_sdram_rcw(ddr, popts, common_dimm);
1656
1657 #ifdef CONFIG_SYS_FSL_DDR_EMU
1658         /* disble DDR training for emulator */
1659         ddr->debug[2] = 0x00000400;
1660         ddr->debug[4] = 0xff800000;
1661 #endif
1662         return check_fsl_memctl_config_regs(ddr);
1663 }