drivers/ddr/fsl/ctrl_regs.c

   1 /*
   2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
   9  * Based on code from spd_sdram.c
  10  * Author: James Yang [at freescale.com]
  11  */
  12
  13 #include <common.h>
  14 #include <fsl_ddr_sdram.h>
  15
  16 #include <fsl_ddr.h>
  17 #include <fsl_immap.h>
  18 #include <asm/io.h>
  19
  20 #define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR
  21
  22 static u32 fsl_ddr_get_version(void)
  23 {
  24         struct ccsr_ddr __iomem *ddr;
  25         u32 ver_major_minor_errata;
  26
  27         ddr = (void *)_DDR_ADDR;
  28         ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8;
  29         ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8;
  30
  31         return ver_major_minor_errata;
  32 }
  33
  34 unsigned int picos_to_mclk(unsigned int picos);
  35
  36 /*
  37  * Determine Rtt value.
  38  *
  39  * This should likely be either board or controller specific.
  40  *
  41  * Rtt(nominal) - DDR2:
  42  *      0 = Rtt disabled
  43  *      1 = 75 ohm
  44  *      2 = 150 ohm
  45  *      3 = 50 ohm
  46  * Rtt(nominal) - DDR3:
  47  *      0 = Rtt disabled
  48  *      1 = 60 ohm
  49  *      2 = 120 ohm
  50  *      3 = 40 ohm
  51  *      4 = 20 ohm
  52  *      5 = 30 ohm
  53  *
  54  * FIXME: Apparently 8641 needs a value of 2
  55  * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  56  *
  57  * FIXME: There was some effort down this line earlier:
  58  *
  59  *      unsigned int i;
  60  *      for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  61  *              if (popts->dimmslot[i].num_valid_cs
  62  *                  && (popts->cs_local_opts[2*i].odt_rd_cfg
  63  *                      || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  64  *                      rtt = 2;
  65  *                      break;
  66  *              }
  67  *      }
  68  */
  69 static inline int fsl_ddr_get_rtt(void)
  70 {
  71         int rtt;
  72
  73 #if defined(CONFIG_SYS_FSL_DDR1)
  74         rtt = 0;
  75 #elif defined(CONFIG_SYS_FSL_DDR2)
  76         rtt = 3;
  77 #else
  78         rtt = 0;
  79 #endif
  80
  81         return rtt;
  82 }
  83
  84 /*
  85  * compute the CAS write latency according to DDR3 spec
  86  * CWL = 5 if tCK >= 2.5ns
  87  *       6 if 2.5ns > tCK >= 1.875ns
  88  *       7 if 1.875ns > tCK >= 1.5ns
  89  *       8 if 1.5ns > tCK >= 1.25ns
  90  *       9 if 1.25ns > tCK >= 1.07ns
  91  *       10 if 1.07ns > tCK >= 0.935ns
  92  *       11 if 0.935ns > tCK >= 0.833ns
  93  *       12 if 0.833ns > tCK >= 0.75ns
  94  */
  95 static inline unsigned int compute_cas_write_latency(void)
  96 {
  97         unsigned int cwl;
  98         const unsigned int mclk_ps = get_memory_clk_period_ps();
  99
 100         if (mclk_ps >= 2500)
 101                 cwl = 5;
 102         else if (mclk_ps >= 1875)
 103                 cwl = 6;
 104         else if (mclk_ps >= 1500)
 105                 cwl = 7;
 106         else if (mclk_ps >= 1250)
 107                 cwl = 8;
 108         else if (mclk_ps >= 1070)
 109                 cwl = 9;
 110         else if (mclk_ps >= 935)
 111                 cwl = 10;
 112         else if (mclk_ps >= 833)
 113                 cwl = 11;
 114         else if (mclk_ps >= 750)
 115                 cwl = 12;
 116         else {
 117                 cwl = 12;
 118                 printf("Warning: CWL is out of range\n");
 119         }
 120         return cwl;
 121 }
 122
 123 /* Chip Select Configuration (CSn_CONFIG) */
 124 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
 125                                const memctl_options_t *popts,
 126                                const dimm_params_t *dimm_params)
 127 {
 128         unsigned int cs_n_en = 0; /* Chip Select enable */
 129         unsigned int intlv_en = 0; /* Memory controller interleave enable */
 130         unsigned int intlv_ctl = 0; /* Interleaving control */
 131         unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
 132         unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
 133         unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
 134         unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
 135         unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
 136         unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
 137         int go_config = 0;
 138
 139         /* Compute CS_CONFIG only for existing ranks of each DIMM.  */
 140         switch (i) {
 141         case 0:
 142                 if (dimm_params[dimm_number].n_ranks > 0) {
 143                         go_config = 1;
 144                         /* These fields only available in CS0_CONFIG */
 145                         if (!popts->memctl_interleaving)
 146                                 break;
 147                         switch (popts->memctl_interleaving_mode) {
 148                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
 149                         case FSL_DDR_PAGE_INTERLEAVING:
 150                         case FSL_DDR_BANK_INTERLEAVING:
 151                         case FSL_DDR_SUPERBANK_INTERLEAVING:
 152                                 intlv_en = popts->memctl_interleaving;
 153                                 intlv_ctl = popts->memctl_interleaving_mode;
 154                                 break;
 155                         default:
 156                                 break;
 157                         }
 158                 }
 159                 break;
 160         case 1:
 161                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
 162                     (dimm_number == 1 && dimm_params[1].n_ranks > 0))
 163                         go_config = 1;
 164                 break;
 165         case 2:
 166                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
 167                    (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
 168                         go_config = 1;
 169                 break;
 170         case 3:
 171                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
 172                     (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
 173                     (dimm_number == 3 && dimm_params[3].n_ranks > 0))
 174                         go_config = 1;
 175                 break;
 176         default:
 177                 break;
 178         }
 179         if (go_config) {
 180                 unsigned int n_banks_per_sdram_device;
 181                 cs_n_en = 1;
 182                 ap_n_en = popts->cs_local_opts[i].auto_precharge;
 183                 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
 184                 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
 185                 n_banks_per_sdram_device
 186                         = dimm_params[dimm_number].n_banks_per_sdram_device;
 187                 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
 188                 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
 189                 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
 190         }
 191         ddr->cs[i].config = (0
 192                 | ((cs_n_en & 0x1) << 31)
 193                 | ((intlv_en & 0x3) << 29)
 194                 | ((intlv_ctl & 0xf) << 24)
 195                 | ((ap_n_en & 0x1) << 23)
 196
 197                 /* XXX: some implementation only have 1 bit starting at left */
 198                 | ((odt_rd_cfg & 0x7) << 20)
 199
 200                 /* XXX: Some implementation only have 1 bit starting at left */
 201                 | ((odt_wr_cfg & 0x7) << 16)
 202
 203                 | ((ba_bits_cs_n & 0x3) << 14)
 204                 | ((row_bits_cs_n & 0x7) << 8)
 205                 | ((col_bits_cs_n & 0x7) << 0)
 206                 );
 207         debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
 208 }
 209
 210 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
 211 /* FIXME: 8572 */
 212 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 213 {
 214         unsigned int pasr_cfg = 0;      /* Partial array self refresh config */
 215
 216         ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
 217         debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
 218 }
 219
 220 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 221
 222 #if !defined(CONFIG_SYS_FSL_DDR1)
 223 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
 224 {
 225 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
 226         if (dimm_params[0].n_ranks == 4)
 227                 return 1;
 228 #endif
 229
 230 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
 231         if ((dimm_params[0].n_ranks == 2) &&
 232                 (dimm_params[1].n_ranks == 2))
 233                 return 1;
 234
 235 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 236         if (dimm_params[0].n_ranks == 4)
 237                 return 1;
 238 #endif
 239 #endif
 240         return 0;
 241 }
 242
 243 /*
 244  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
 245  *
 246  * Avoid writing for DDR I.  The new PQ38 DDR controller
 247  * dreams up non-zero default values to be backwards compatible.
 248  */
 249 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 250                                 const memctl_options_t *popts,
 251                                 const dimm_params_t *dimm_params)
 252 {
 253         unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 254         unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
 255         /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
 256         unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
 257         unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
 258
 259         /* Active powerdown exit timing (tXARD and tXARDS). */
 260         unsigned char act_pd_exit_mclk;
 261         /* Precharge powerdown exit timing (tXP). */
 262         unsigned char pre_pd_exit_mclk;
 263         /* ODT powerdown exit timing (tAXPD). */
 264         unsigned char taxpd_mclk;
 265         /* Mode register set cycle time (tMRD). */
 266         unsigned char tmrd_mclk;
 267
 268 #ifdef CONFIG_SYS_FSL_DDR3
 269         /*
 270          * (tXARD and tXARDS). Empirical?
 271          * The DDR3 spec has not tXARD,
 272          * we use the tXP instead of it.
 273          * tXP=max(3nCK, 7.5ns) for DDR3.
 274          * spec has not the tAXPD, we use
 275          * tAXPD=1, need design to confirm.
 276          */
 277         int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
 278         unsigned int data_rate = get_ddr_freq(0);
 279         tmrd_mclk = 4;
 280         /* set the turnaround time */
 281
 282         /*
 283          * for single quad-rank DIMM and two dual-rank DIMMs
 284          * to avoid ODT overlap
 285          */
 286         if (avoid_odt_overlap(dimm_params)) {
 287                 twwt_mclk = 2;
 288                 trrt_mclk = 1;
 289         }
 290         /* for faster clock, need more time for data setup */
 291         trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
 292
 293         if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
 294                 twrt_mclk = 1;
 295
 296         if (popts->dynamic_power == 0) {        /* powerdown is not used */
 297                 act_pd_exit_mclk = 1;
 298                 pre_pd_exit_mclk = 1;
 299                 taxpd_mclk = 1;
 300         } else {
 301                 /* act_pd_exit_mclk = tXARD, see above */
 302                 act_pd_exit_mclk = picos_to_mclk(tXP);
 303                 /* Mode register MR0[A12] is '1' - fast exit */
 304                 pre_pd_exit_mclk = act_pd_exit_mclk;
 305                 taxpd_mclk = 1;
 306         }
 307 #else /* CONFIG_SYS_FSL_DDR2 */
 308         /*
 309          * (tXARD and tXARDS). Empirical?
 310          * tXARD = 2 for DDR2
 311          * tXP=2
 312          * tAXPD=8
 313          */
 314         act_pd_exit_mclk = 2;
 315         pre_pd_exit_mclk = 2;
 316         taxpd_mclk = 8;
 317         tmrd_mclk = 2;
 318 #endif
 319
 320         if (popts->trwt_override)
 321                 trwt_mclk = popts->trwt;
 322
 323         ddr->timing_cfg_0 = (0
 324                 | ((trwt_mclk & 0x3) << 30)     /* RWT */
 325                 | ((twrt_mclk & 0x3) << 28)     /* WRT */
 326                 | ((trrt_mclk & 0x3) << 26)     /* RRT */
 327                 | ((twwt_mclk & 0x3) << 24)     /* WWT */
 328                 | ((act_pd_exit_mclk & 0xf) << 20)  /* ACT_PD_EXIT */
 329                 | ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
 330                 | ((taxpd_mclk & 0xf) << 8)     /* ODT_PD_EXIT */
 331                 | ((tmrd_mclk & 0x1f) << 0)     /* MRS_CYC */
 332                 );
 333         debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 334 }
 335 #endif  /* defined(CONFIG_SYS_FSL_DDR2) */
 336
 337 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 338 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
 339                                const memctl_options_t *popts,
 340                                const common_timing_params_t *common_dimm,
 341                                unsigned int cas_latency,
 342                                unsigned int additive_latency)
 343 {
 344         /* Extended precharge to activate interval (tRP) */
 345         unsigned int ext_pretoact = 0;
 346         /* Extended Activate to precharge interval (tRAS) */
 347         unsigned int ext_acttopre = 0;
 348         /* Extended activate to read/write interval (tRCD) */
 349         unsigned int ext_acttorw = 0;
 350         /* Extended refresh recovery time (tRFC) */
 351         unsigned int ext_refrec;
 352         /* Extended MCAS latency from READ cmd */
 353         unsigned int ext_caslat = 0;
 354         /* Extended additive latency */
 355         unsigned int ext_add_lat = 0;
 356         /* Extended last data to precharge interval (tWR) */
 357         unsigned int ext_wrrec = 0;
 358         /* Control Adjust */
 359         unsigned int cntl_adj = 0;
 360
 361         ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4;
 362         ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4;
 363         ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4;
 364         ext_caslat = (2 * cas_latency - 1) >> 4;
 365         ext_add_lat = additive_latency >> 4;
 366         ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4;
 367         /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
 368         ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) +
 369                 (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
 370
 371         ddr->timing_cfg_3 = (0
 372                 | ((ext_pretoact & 0x1) << 28)
 373                 | ((ext_acttopre & 0x3) << 24)
 374                 | ((ext_acttorw & 0x1) << 22)
 375                 | ((ext_refrec & 0x1F) << 16)
 376                 | ((ext_caslat & 0x3) << 12)
 377                 | ((ext_add_lat & 0x1) << 10)
 378                 | ((ext_wrrec & 0x1) << 8)
 379                 | ((cntl_adj & 0x7) << 0)
 380                 );
 381         debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 382 }
 383
 384 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
 385 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 386                                const memctl_options_t *popts,
 387                                const common_timing_params_t *common_dimm,
 388                                unsigned int cas_latency)
 389 {
 390         /* Precharge-to-activate interval (tRP) */
 391         unsigned char pretoact_mclk;
 392         /* Activate to precharge interval (tRAS) */
 393         unsigned char acttopre_mclk;
 394         /*  Activate to read/write interval (tRCD) */
 395         unsigned char acttorw_mclk;
 396         /* CASLAT */
 397         unsigned char caslat_ctrl;
 398         /*  Refresh recovery time (tRFC) ; trfc_low */
 399         unsigned char refrec_ctrl;
 400         /* Last data to precharge minimum interval (tWR) */
 401         unsigned char wrrec_mclk;
 402         /* Activate-to-activate interval (tRRD) */
 403         unsigned char acttoact_mclk;
 404         /* Last write data pair to read command issue interval (tWTR) */
 405         unsigned char wrtord_mclk;
 406         /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
 407         static const u8 wrrec_table[] = {
 408                 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
 409
 410         pretoact_mclk = picos_to_mclk(common_dimm->trp_ps);
 411         acttopre_mclk = picos_to_mclk(common_dimm->tras_ps);
 412         acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps);
 413
 414         /*
 415          * Translate CAS Latency to a DDR controller field value:
 416          *
 417          *      CAS Lat DDR I   DDR II  Ctrl
 418          *      Clocks  SPD Bit SPD Bit Value
 419          *      ------- ------- ------- -----
 420          *      1.0     0               0001
 421          *      1.5     1               0010
 422          *      2.0     2       2       0011
 423          *      2.5     3               0100
 424          *      3.0     4       3       0101
 425          *      3.5     5               0110
 426          *      4.0             4       0111
 427          *      4.5                     1000
 428          *      5.0             5       1001
 429          */
 430 #if defined(CONFIG_SYS_FSL_DDR1)
 431         caslat_ctrl = (cas_latency + 1) & 0x07;
 432 #elif defined(CONFIG_SYS_FSL_DDR2)
 433         caslat_ctrl = 2 * cas_latency - 1;
 434 #else
 435         /*
 436          * if the CAS latency more than 8 cycle,
 437          * we need set extend bit for it at
 438          * TIMING_CFG_3[EXT_CASLAT]
 439          */
 440         caslat_ctrl = 2 * cas_latency - 1;
 441 #endif
 442
 443         refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8;
 444         wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
 445
 446         if (wrrec_mclk > 16)
 447                 printf("Error: WRREC doesn't support more than 16 clocks\n");
 448         else
 449                 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 450         if (popts->otf_burst_chop_en)
 451                 wrrec_mclk += 2;
 452
 453         acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps);
 454         /*
 455          * JEDEC has min requirement for tRRD
 456          */
 457 #if defined(CONFIG_SYS_FSL_DDR3)
 458         if (acttoact_mclk < 4)
 459                 acttoact_mclk = 4;
 460 #endif
 461         wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps);
 462         /*
 463          * JEDEC has some min requirements for tWTR
 464          */
 465 #if defined(CONFIG_SYS_FSL_DDR2)
 466         if (wrtord_mclk < 2)
 467                 wrtord_mclk = 2;
 468 #elif defined(CONFIG_SYS_FSL_DDR3)
 469         if (wrtord_mclk < 4)
 470                 wrtord_mclk = 4;
 471 #endif
 472         if (popts->otf_burst_chop_en)
 473                 wrtord_mclk += 2;
 474
 475         ddr->timing_cfg_1 = (0
 476                 | ((pretoact_mclk & 0x0F) << 28)
 477                 | ((acttopre_mclk & 0x0F) << 24)
 478                 | ((acttorw_mclk & 0xF) << 20)
 479                 | ((caslat_ctrl & 0xF) << 16)
 480                 | ((refrec_ctrl & 0xF) << 12)
 481                 | ((wrrec_mclk & 0x0F) << 8)
 482                 | ((acttoact_mclk & 0x0F) << 4)
 483                 | ((wrtord_mclk & 0x0F) << 0)
 484                 );
 485         debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 486 }
 487
 488 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
 489 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 490                                const memctl_options_t *popts,
 491                                const common_timing_params_t *common_dimm,
 492                                unsigned int cas_latency,
 493                                unsigned int additive_latency)
 494 {
 495         /* Additive latency */
 496         unsigned char add_lat_mclk;
 497         /* CAS-to-preamble override */
 498         unsigned short cpo;
 499         /* Write latency */
 500         unsigned char wr_lat;
 501         /*  Read to precharge (tRTP) */
 502         unsigned char rd_to_pre;
 503         /* Write command to write data strobe timing adjustment */
 504         unsigned char wr_data_delay;
 505         /* Minimum CKE pulse width (tCKE) */
 506         unsigned char cke_pls;
 507         /* Window for four activates (tFAW) */
 508         unsigned short four_act;
 509
 510         /* FIXME add check that this must be less than acttorw_mclk */
 511         add_lat_mclk = additive_latency;
 512         cpo = popts->cpo_override;
 513
 514 #if defined(CONFIG_SYS_FSL_DDR1)
 515         /*
 516          * This is a lie.  It should really be 1, but if it is
 517          * set to 1, bits overlap into the old controller's
 518          * otherwise unused ACSM field.  If we leave it 0, then
 519          * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
 520          */
 521         wr_lat = 0;
 522 #elif defined(CONFIG_SYS_FSL_DDR2)
 523         wr_lat = cas_latency - 1;
 524 #else
 525         wr_lat = compute_cas_write_latency();
 526 #endif
 527
 528         rd_to_pre = picos_to_mclk(common_dimm->trtp_ps);
 529         /*
 530          * JEDEC has some min requirements for tRTP
 531          */
 532 #if defined(CONFIG_SYS_FSL_DDR2)
 533         if (rd_to_pre  < 2)
 534                 rd_to_pre  = 2;
 535 #elif defined(CONFIG_SYS_FSL_DDR3)
 536         if (rd_to_pre < 4)
 537                 rd_to_pre = 4;
 538 #endif
 539         if (popts->otf_burst_chop_en)
 540                 rd_to_pre += 2; /* according to UM */
 541
 542         wr_data_delay = popts->write_data_delay;
 543         cke_pls = picos_to_mclk(popts->tcke_clock_pulse_width_ps);
 544         four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps);
 545
 546         ddr->timing_cfg_2 = (0
 547                 | ((add_lat_mclk & 0xf) << 28)
 548                 | ((cpo & 0x1f) << 23)
 549                 | ((wr_lat & 0xf) << 19)
 550                 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 551                 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 552                 | ((cke_pls & 0x7) << 6)
 553                 | ((four_act & 0x3f) << 0)
 554                 );
 555         debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 556 }
 557
 558 /* DDR SDRAM Register Control Word */
 559 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
 560                                const memctl_options_t *popts,
 561                                const common_timing_params_t *common_dimm)
 562 {
 563         if (common_dimm->all_dimms_registered &&
 564             !common_dimm->all_dimms_unbuffered) {
 565                 if (popts->rcw_override) {
 566                         ddr->ddr_sdram_rcw_1 = popts->rcw_1;
 567                         ddr->ddr_sdram_rcw_2 = popts->rcw_2;
 568                 } else {
 569                         ddr->ddr_sdram_rcw_1 =
 570                                 common_dimm->rcw[0] << 28 | \
 571                                 common_dimm->rcw[1] << 24 | \
 572                                 common_dimm->rcw[2] << 20 | \
 573                                 common_dimm->rcw[3] << 16 | \
 574                                 common_dimm->rcw[4] << 12 | \
 575                                 common_dimm->rcw[5] << 8 | \
 576                                 common_dimm->rcw[6] << 4 | \
 577                                 common_dimm->rcw[7];
 578                         ddr->ddr_sdram_rcw_2 =
 579                                 common_dimm->rcw[8] << 28 | \
 580                                 common_dimm->rcw[9] << 24 | \
 581                                 common_dimm->rcw[10] << 20 | \
 582                                 common_dimm->rcw[11] << 16 | \
 583                                 common_dimm->rcw[12] << 12 | \
 584                                 common_dimm->rcw[13] << 8 | \
 585                                 common_dimm->rcw[14] << 4 | \
 586                                 common_dimm->rcw[15];
 587                 }
 588                 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
 589                 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
 590         }
 591 }
 592
 593 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
 594 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 595                                const memctl_options_t *popts,
 596                                const common_timing_params_t *common_dimm)
 597 {
 598         unsigned int mem_en;            /* DDR SDRAM interface logic enable */
 599         unsigned int sren;              /* Self refresh enable (during sleep) */
 600         unsigned int ecc_en;            /* ECC enable. */
 601         unsigned int rd_en;             /* Registered DIMM enable */
 602         unsigned int sdram_type;        /* Type of SDRAM */
 603         unsigned int dyn_pwr;           /* Dynamic power management mode */
 604         unsigned int dbw;               /* DRAM dta bus width */
 605         unsigned int eight_be = 0;      /* 8-beat burst enable, DDR2 is zero */
 606         unsigned int ncap = 0;          /* Non-concurrent auto-precharge */
 607         unsigned int threet_en;         /* Enable 3T timing */
 608         unsigned int twot_en;           /* Enable 2T timing */
 609         unsigned int ba_intlv_ctl;      /* Bank (CS) interleaving control */
 610         unsigned int x32_en = 0;        /* x32 enable */
 611         unsigned int pchb8 = 0;         /* precharge bit 8 enable */
 612         unsigned int hse;               /* Global half strength override */
 613         unsigned int mem_halt = 0;      /* memory controller halt */
 614         unsigned int bi = 0;            /* Bypass initialization */
 615
 616         mem_en = 1;
 617         sren = popts->self_refresh_in_sleep;
 618         if (common_dimm->all_dimms_ecc_capable) {
 619                 /* Allow setting of ECC only if all DIMMs are ECC. */
 620                 ecc_en = popts->ecc_mode;
 621         } else {
 622                 ecc_en = 0;
 623         }
 624
 625         if (common_dimm->all_dimms_registered &&
 626             !common_dimm->all_dimms_unbuffered) {
 627                 rd_en = 1;
 628                 twot_en = 0;
 629         } else {
 630                 rd_en = 0;
 631                 twot_en = popts->twot_en;
 632         }
 633
 634         sdram_type = CONFIG_FSL_SDRAM_TYPE;
 635
 636         dyn_pwr = popts->dynamic_power;
 637         dbw = popts->data_bus_width;
 638         /* 8-beat burst enable DDR-III case
 639          * we must clear it when use the on-the-fly mode,
 640          * must set it when use the 32-bits bus mode.
 641          */
 642         if (sdram_type == SDRAM_TYPE_DDR3) {
 643                 if (popts->burst_length == DDR_BL8)
 644                         eight_be = 1;
 645                 if (popts->burst_length == DDR_OTF)
 646                         eight_be = 0;
 647                 if (dbw == 0x1)
 648                         eight_be = 1;
 649         }
 650
 651         threet_en = popts->threet_en;
 652         ba_intlv_ctl = popts->ba_intlv_ctl;
 653         hse = popts->half_strength_driver_enable;
 654
 655         ddr->ddr_sdram_cfg = (0
 656                         | ((mem_en & 0x1) << 31)
 657                         | ((sren & 0x1) << 30)
 658                         | ((ecc_en & 0x1) << 29)
 659                         | ((rd_en & 0x1) << 28)
 660                         | ((sdram_type & 0x7) << 24)
 661                         | ((dyn_pwr & 0x1) << 21)
 662                         | ((dbw & 0x3) << 19)
 663                         | ((eight_be & 0x1) << 18)
 664                         | ((ncap & 0x1) << 17)
 665                         | ((threet_en & 0x1) << 16)
 666                         | ((twot_en & 0x1) << 15)
 667                         | ((ba_intlv_ctl & 0x7F) << 8)
 668                         | ((x32_en & 0x1) << 5)
 669                         | ((pchb8 & 0x1) << 4)
 670                         | ((hse & 0x1) << 3)
 671                         | ((mem_halt & 0x1) << 1)
 672                         | ((bi & 0x1) << 0)
 673                         );
 674         debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 675 }
 676
 677 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
 678 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 679                                const memctl_options_t *popts,
 680                                const unsigned int unq_mrs_en)
 681 {
 682         unsigned int frc_sr = 0;        /* Force self refresh */
 683         unsigned int sr_ie = 0;         /* Self-refresh interrupt enable */
 684         unsigned int dll_rst_dis;       /* DLL reset disable */
 685         unsigned int dqs_cfg;           /* DQS configuration */
 686         unsigned int odt_cfg = 0;       /* ODT configuration */
 687         unsigned int num_pr;            /* Number of posted refreshes */
 688         unsigned int slow = 0;          /* DDR will be run less than 1250 */
 689         unsigned int x4_en = 0;         /* x4 DRAM enable */
 690         unsigned int obc_cfg;           /* On-The-Fly Burst Chop Cfg */
 691         unsigned int ap_en;             /* Address Parity Enable */
 692         unsigned int d_init;            /* DRAM data initialization */
 693         unsigned int rcw_en = 0;        /* Register Control Word Enable */
 694         unsigned int md_en = 0;         /* Mirrored DIMM Enable */
 695         unsigned int qd_en = 0;         /* quad-rank DIMM Enable */
 696         int i;
 697
 698         dll_rst_dis = 1;        /* Make this configurable */
 699         dqs_cfg = popts->dqs_config;
 700         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 701                 if (popts->cs_local_opts[i].odt_rd_cfg
 702                         || popts->cs_local_opts[i].odt_wr_cfg) {
 703                         odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
 704                         break;
 705                 }
 706         }
 707
 708         num_pr = 1;     /* Make this configurable */
 709
 710         /*
 711          * 8572 manual says
 712          *     {TIMING_CFG_1[PRETOACT]
 713          *      + [DDR_SDRAM_CFG_2[NUM_PR]
 714          *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
 715          *      << DDR_SDRAM_INTERVAL[REFINT]
 716          */
 717 #if defined(CONFIG_SYS_FSL_DDR3)
 718         obc_cfg = popts->otf_burst_chop_en;
 719 #else
 720         obc_cfg = 0;
 721 #endif
 722
 723 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
 724         slow = get_ddr_freq(0) < 1249000000;
 725 #endif
 726
 727         if (popts->registered_dimm_en) {
 728                 rcw_en = 1;
 729                 ap_en = popts->ap_en;
 730         } else {
 731                 ap_en = 0;
 732         }
 733
 734         x4_en = popts->x4_en ? 1 : 0;
 735
 736 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 737         /* Use the DDR controller to auto initialize memory. */
 738         d_init = popts->ecc_init_using_memctl;
 739         ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 740         debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 741 #else
 742         /* Memory will be initialized via DMA, or not at all. */
 743         d_init = 0;
 744 #endif
 745
 746 #if defined(CONFIG_SYS_FSL_DDR3)
 747         md_en = popts->mirrored_dimm;
 748 #endif
 749         qd_en = popts->quad_rank_present ? 1 : 0;
 750         ddr->ddr_sdram_cfg_2 = (0
 751                 | ((frc_sr & 0x1) << 31)
 752                 | ((sr_ie & 0x1) << 30)
 753                 | ((dll_rst_dis & 0x1) << 29)
 754                 | ((dqs_cfg & 0x3) << 26)
 755                 | ((odt_cfg & 0x3) << 21)
 756                 | ((num_pr & 0xf) << 12)
 757                 | ((slow & 1) << 11)
 758                 | (x4_en << 10)
 759                 | (qd_en << 9)
 760                 | (unq_mrs_en << 8)
 761                 | ((obc_cfg & 0x1) << 6)
 762                 | ((ap_en & 0x1) << 5)
 763                 | ((d_init & 0x1) << 4)
 764                 | ((rcw_en & 0x1) << 2)
 765                 | ((md_en & 0x1) << 0)
 766                 );
 767         debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
 768 }
 769
 770 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 771 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 772                                 const memctl_options_t *popts,
 773                                 const common_timing_params_t *common_dimm,
 774                                 const unsigned int unq_mrs_en)
 775 {
 776         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 777         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 778
 779 #if defined(CONFIG_SYS_FSL_DDR3)
 780         int i;
 781         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
 782         unsigned int srt = 0;   /* self-refresh temerature, normal range */
 783         unsigned int asr = 0;   /* auto self-refresh disable */
 784         unsigned int cwl = compute_cas_write_latency() - 5;
 785         unsigned int pasr = 0;  /* partial array self refresh disable */
 786
 787         if (popts->rtt_override)
 788                 rtt_wr = popts->rtt_wr_override_value;
 789         else
 790                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
 791
 792         if (common_dimm->extended_op_srt)
 793                 srt = common_dimm->extended_op_srt;
 794
 795         esdmode2 = (0
 796                 | ((rtt_wr & 0x3) << 9)
 797                 | ((srt & 0x1) << 7)
 798                 | ((asr & 0x1) << 6)
 799                 | ((cwl & 0x7) << 3)
 800                 | ((pasr & 0x7) << 0));
 801 #endif
 802         ddr->ddr_sdram_mode_2 = (0
 803                                  | ((esdmode2 & 0xFFFF) << 16)
 804                                  | ((esdmode3 & 0xFFFF) << 0)
 805                                  );
 806         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
 807
 808 #ifdef CONFIG_SYS_FSL_DDR3
 809         if (unq_mrs_en) {       /* unique mode registers are supported */
 810                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 811                         if (popts->rtt_override)
 812                                 rtt_wr = popts->rtt_wr_override_value;
 813                         else
 814                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
 815
 816                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
 817                         esdmode2 |= (rtt_wr & 0x3) << 9;
 818                         switch (i) {
 819                         case 1:
 820                                 ddr->ddr_sdram_mode_4 = (0
 821                                         | ((esdmode2 & 0xFFFF) << 16)
 822                                         | ((esdmode3 & 0xFFFF) << 0)
 823                                         );
 824                                 break;
 825                         case 2:
 826                                 ddr->ddr_sdram_mode_6 = (0
 827                                         | ((esdmode2 & 0xFFFF) << 16)
 828                                         | ((esdmode3 & 0xFFFF) << 0)
 829                                         );
 830                                 break;
 831                         case 3:
 832                                 ddr->ddr_sdram_mode_8 = (0
 833                                         | ((esdmode2 & 0xFFFF) << 16)
 834                                         | ((esdmode3 & 0xFFFF) << 0)
 835                                         );
 836                                 break;
 837                         }
 838                 }
 839                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
 840                         ddr->ddr_sdram_mode_4);
 841                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
 842                         ddr->ddr_sdram_mode_6);
 843                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
 844                         ddr->ddr_sdram_mode_8);
 845         }
 846 #endif
 847 }
 848
 849 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
 850 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
 851                                const memctl_options_t *popts,
 852                                const common_timing_params_t *common_dimm)
 853 {
 854         unsigned int refint;    /* Refresh interval */
 855         unsigned int bstopre;   /* Precharge interval */
 856
 857         refint = picos_to_mclk(common_dimm->refresh_rate_ps);
 858
 859         bstopre = popts->bstopre;
 860
 861         /* refint field used 0x3FFF in earlier controllers */
 862         ddr->ddr_sdram_interval = (0
 863                                    | ((refint & 0xFFFF) << 16)
 864                                    | ((bstopre & 0x3FFF) << 0)
 865                                    );
 866         debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
 867 }
 868
 869 #if defined(CONFIG_SYS_FSL_DDR3)
 870 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
 871 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 872                                const memctl_options_t *popts,
 873                                const common_timing_params_t *common_dimm,
 874                                unsigned int cas_latency,
 875                                unsigned int additive_latency,
 876                                const unsigned int unq_mrs_en)
 877 {
 878         unsigned short esdmode;         /* Extended SDRAM mode */
 879         unsigned short sdmode;          /* SDRAM mode */
 880
 881         /* Mode Register - MR1 */
 882         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
 883         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
 884         unsigned int rtt;
 885         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
 886         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
 887         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
 888         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
 889                                                        1=Disable (Test/Debug) */
 890
 891         /* Mode Register - MR0 */
 892         unsigned int dll_on;    /* DLL control for precharge PD, 0=off, 1=on */
 893         unsigned int wr = 0;    /* Write Recovery */
 894         unsigned int dll_rst;   /* DLL Reset */
 895         unsigned int mode;      /* Normal=0 or Test=1 */
 896         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
 897         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
 898         unsigned int bt;
 899         unsigned int bl;        /* BL: Burst Length */
 900
 901         unsigned int wr_mclk;
 902         /*
 903          * DDR_SDRAM_MODE doesn't support 9,11,13,15
 904          * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
 905          * for this table
 906          */
 907         static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
 908
 909         const unsigned int mclk_ps = get_memory_clk_period_ps();
 910         int i;
 911
 912         if (popts->rtt_override)
 913                 rtt = popts->rtt_override_value;
 914         else
 915                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
 916
 917         if (additive_latency == (cas_latency - 1))
 918                 al = 1;
 919         if (additive_latency == (cas_latency - 2))
 920                 al = 2;
 921
 922         if (popts->quad_rank_present)
 923                 dic = 1;        /* output driver impedance 240/7 ohm */
 924
 925         /*
 926          * The esdmode value will also be used for writing
 927          * MR1 during write leveling for DDR3, although the
 928          * bits specifically related to the write leveling
 929          * scheme will be handled automatically by the DDR
 930          * controller. so we set the wrlvl_en = 0 here.
 931          */
 932         esdmode = (0
 933                 | ((qoff & 0x1) << 12)
 934                 | ((tdqs_en & 0x1) << 11)
 935                 | ((rtt & 0x4) << 7)   /* rtt field is split */
 936                 | ((wrlvl_en & 0x1) << 7)
 937                 | ((rtt & 0x2) << 5)   /* rtt field is split */
 938                 | ((dic & 0x2) << 4)   /* DIC field is split */
 939                 | ((al & 0x3) << 3)
 940                 | ((rtt & 0x1) << 2)  /* rtt field is split */
 941                 | ((dic & 0x1) << 1)   /* DIC field is split */
 942                 | ((dll_en & 0x1) << 0)
 943                 );
 944
 945         /*
 946          * DLL control for precharge PD
 947          * 0=slow exit DLL off (tXPDLL)
 948          * 1=fast exit DLL on (tXP)
 949          */
 950         dll_on = 1;
 951
 952         wr_mclk = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps;
 953         if (wr_mclk <= 16) {
 954                 wr = wr_table[wr_mclk - 5];
 955         } else {
 956                 printf("Error: unsupported write recovery for mode register "
 957                        "wr_mclk = %d\n", wr_mclk);
 958         }
 959
 960         dll_rst = 0;    /* dll no reset */
 961         mode = 0;       /* normal mode */
 962
 963         /* look up table to get the cas latency bits */
 964         if (cas_latency >= 5 && cas_latency <= 16) {
 965                 unsigned char cas_latency_table[] = {
 966                         0x2,    /* 5 clocks */
 967                         0x4,    /* 6 clocks */
 968                         0x6,    /* 7 clocks */
 969                         0x8,    /* 8 clocks */
 970                         0xa,    /* 9 clocks */
 971                         0xc,    /* 10 clocks */
 972                         0xe,    /* 11 clocks */
 973                         0x1,    /* 12 clocks */
 974                         0x3,    /* 13 clocks */
 975                         0x5,    /* 14 clocks */
 976                         0x7,    /* 15 clocks */
 977                         0x9,    /* 16 clocks */
 978                 };
 979                 caslat = cas_latency_table[cas_latency - 5];
 980         } else {
 981                 printf("Error: unsupported cas latency for mode register\n");
 982         }
 983
 984         bt = 0; /* Nibble sequential */
 985
 986         switch (popts->burst_length) {
 987         case DDR_BL8:
 988                 bl = 0;
 989                 break;
 990         case DDR_OTF:
 991                 bl = 1;
 992                 break;
 993         case DDR_BC4:
 994                 bl = 2;
 995                 break;
 996         default:
 997                 printf("Error: invalid burst length of %u specified. "
 998                         " Defaulting to on-the-fly BC4 or BL8 beats.\n",
 999                         popts->burst_length);
1000                 bl = 1;
1001                 break;
1002         }
1003
1004         sdmode = (0
1005                   | ((dll_on & 0x1) << 12)
1006                   | ((wr & 0x7) << 9)
1007                   | ((dll_rst & 0x1) << 8)
1008                   | ((mode & 0x1) << 7)
1009                   | (((caslat >> 1) & 0x7) << 4)
1010                   | ((bt & 0x1) << 3)
1011                   | ((caslat & 1) << 2)
1012                   | ((bl & 0x3) << 0)
1013                   );
1014
1015         ddr->ddr_sdram_mode = (0
1016                                | ((esdmode & 0xFFFF) << 16)
1017                                | ((sdmode & 0xFFFF) << 0)
1018                                );
1019
1020         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1021
1022         if (unq_mrs_en) {       /* unique mode registers are supported */
1023                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1024                         if (popts->rtt_override)
1025                                 rtt = popts->rtt_override_value;
1026                         else
1027                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1028
1029                         esdmode &= 0xFDBB;      /* clear bit 9,6,2 */
1030                         esdmode |= (0
1031                                 | ((rtt & 0x4) << 7)   /* rtt field is split */
1032                                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1033                                 | ((rtt & 0x1) << 2)  /* rtt field is split */
1034                                 );
1035                         switch (i) {
1036                         case 1:
1037                                 ddr->ddr_sdram_mode_3 = (0
1038                                        | ((esdmode & 0xFFFF) << 16)
1039                                        | ((sdmode & 0xFFFF) << 0)
1040                                        );
1041                                 break;
1042                         case 2:
1043                                 ddr->ddr_sdram_mode_5 = (0
1044                                        | ((esdmode & 0xFFFF) << 16)
1045                                        | ((sdmode & 0xFFFF) << 0)
1046                                        );
1047                                 break;
1048                         case 3:
1049                                 ddr->ddr_sdram_mode_7 = (0
1050                                        | ((esdmode & 0xFFFF) << 16)
1051                                        | ((sdmode & 0xFFFF) << 0)
1052                                        );
1053                                 break;
1054                         }
1055                 }
1056                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1057                         ddr->ddr_sdram_mode_3);
1058                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1059                         ddr->ddr_sdram_mode_5);
1060                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1061                         ddr->ddr_sdram_mode_5);
1062         }
1063 }
1064
1065 #else /* !CONFIG_SYS_FSL_DDR3 */
1066
1067 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1068 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1069                                const memctl_options_t *popts,
1070                                const common_timing_params_t *common_dimm,
1071                                unsigned int cas_latency,
1072                                unsigned int additive_latency,
1073                                const unsigned int unq_mrs_en)
1074 {
1075         unsigned short esdmode;         /* Extended SDRAM mode */
1076         unsigned short sdmode;          /* SDRAM mode */
1077
1078         /*
1079          * FIXME: This ought to be pre-calculated in a
1080          * technology-specific routine,
1081          * e.g. compute_DDR2_mode_register(), and then the
1082          * sdmode and esdmode passed in as part of common_dimm.
1083          */
1084
1085         /* Extended Mode Register */
1086         unsigned int mrs = 0;           /* Mode Register Set */
1087         unsigned int outputs = 0;       /* 0=Enabled, 1=Disabled */
1088         unsigned int rdqs_en = 0;       /* RDQS Enable: 0=no, 1=yes */
1089         unsigned int dqs_en = 0;        /* DQS# Enable: 0=enable, 1=disable */
1090         unsigned int ocd = 0;           /* 0x0=OCD not supported,
1091                                            0x7=OCD default state */
1092         unsigned int rtt;
1093         unsigned int al;                /* Posted CAS# additive latency (AL) */
1094         unsigned int ods = 0;           /* Output Drive Strength:
1095                                                 0 = Full strength (18ohm)
1096                                                 1 = Reduced strength (4ohm) */
1097         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1098                                                        1=Disable (Test/Debug) */
1099
1100         /* Mode Register (MR) */
1101         unsigned int mr;        /* Mode Register Definition */
1102         unsigned int pd;        /* Power-Down Mode */
1103         unsigned int wr;        /* Write Recovery */
1104         unsigned int dll_res;   /* DLL Reset */
1105         unsigned int mode;      /* Normal=0 or Test=1 */
1106         unsigned int caslat = 0;/* CAS# latency */
1107         /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1108         unsigned int bt;
1109         unsigned int bl;        /* BL: Burst Length */
1110
1111 #if defined(CONFIG_SYS_FSL_DDR2)
1112         const unsigned int mclk_ps = get_memory_clk_period_ps();
1113 #endif
1114         dqs_en = !popts->dqs_config;
1115         rtt = fsl_ddr_get_rtt();
1116
1117         al = additive_latency;
1118
1119         esdmode = (0
1120                 | ((mrs & 0x3) << 14)
1121                 | ((outputs & 0x1) << 12)
1122                 | ((rdqs_en & 0x1) << 11)
1123                 | ((dqs_en & 0x1) << 10)
1124                 | ((ocd & 0x7) << 7)
1125                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1126                 | ((al & 0x7) << 3)
1127                 | ((rtt & 0x1) << 2)   /* rtt field is split */
1128                 | ((ods & 0x1) << 1)
1129                 | ((dll_en & 0x1) << 0)
1130                 );
1131
1132         mr = 0;          /* FIXME: CHECKME */
1133
1134         /*
1135          * 0 = Fast Exit (Normal)
1136          * 1 = Slow Exit (Low Power)
1137          */
1138         pd = 0;
1139
1140 #if defined(CONFIG_SYS_FSL_DDR1)
1141         wr = 0;       /* Historical */
1142 #elif defined(CONFIG_SYS_FSL_DDR2)
1143         wr = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps - 1;
1144 #endif
1145         dll_res = 0;
1146         mode = 0;
1147
1148 #if defined(CONFIG_SYS_FSL_DDR1)
1149         if (1 <= cas_latency && cas_latency <= 4) {
1150                 unsigned char mode_caslat_table[4] = {
1151                         0x5,    /* 1.5 clocks */
1152                         0x2,    /* 2.0 clocks */
1153                         0x6,    /* 2.5 clocks */
1154                         0x3     /* 3.0 clocks */
1155                 };
1156                 caslat = mode_caslat_table[cas_latency - 1];
1157         } else {
1158                 printf("Warning: unknown cas_latency %d\n", cas_latency);
1159         }
1160 #elif defined(CONFIG_SYS_FSL_DDR2)
1161         caslat = cas_latency;
1162 #endif
1163         bt = 0;
1164
1165         switch (popts->burst_length) {
1166         case DDR_BL4:
1167                 bl = 2;
1168                 break;
1169         case DDR_BL8:
1170                 bl = 3;
1171                 break;
1172         default:
1173                 printf("Error: invalid burst length of %u specified. "
1174                         " Defaulting to 4 beats.\n",
1175                         popts->burst_length);
1176                 bl = 2;
1177                 break;
1178         }
1179
1180         sdmode = (0
1181                   | ((mr & 0x3) << 14)
1182                   | ((pd & 0x1) << 12)
1183                   | ((wr & 0x7) << 9)
1184                   | ((dll_res & 0x1) << 8)
1185                   | ((mode & 0x1) << 7)
1186                   | ((caslat & 0x7) << 4)
1187                   | ((bt & 0x1) << 3)
1188                   | ((bl & 0x7) << 0)
1189                   );
1190
1191         ddr->ddr_sdram_mode = (0
1192                                | ((esdmode & 0xFFFF) << 16)
1193                                | ((sdmode & 0xFFFF) << 0)
1194                                );
1195         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1196 }
1197 #endif
1198
1199 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1200 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1201 {
1202         unsigned int init_value;        /* Initialization value */
1203
1204 #ifdef CONFIG_MEM_INIT_VALUE
1205         init_value = CONFIG_MEM_INIT_VALUE;
1206 #else
1207         init_value = 0xDEADBEEF;
1208 #endif
1209         ddr->ddr_data_init = init_value;
1210 }
1211
1212 /*
1213  * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1214  * The old controller on the 8540/60 doesn't have this register.
1215  * Hope it's OK to set it (to 0) anyway.
1216  */
1217 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1218                                          const memctl_options_t *popts)
1219 {
1220         unsigned int clk_adjust;        /* Clock adjust */
1221
1222         clk_adjust = popts->clk_adjust;
1223         ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
1224         debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1225 }
1226
1227 /* DDR Initialization Address (DDR_INIT_ADDR) */
1228 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1229 {
1230         unsigned int init_addr = 0;     /* Initialization address */
1231
1232         ddr->ddr_init_addr = init_addr;
1233 }
1234
1235 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1236 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1237 {
1238         unsigned int uia = 0;   /* Use initialization address */
1239         unsigned int init_ext_addr = 0; /* Initialization address */
1240
1241         ddr->ddr_init_ext_addr = (0
1242                                   | ((uia & 0x1) << 31)
1243                                   | (init_ext_addr & 0xF)
1244                                   );
1245 }
1246
1247 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1248 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1249                                 const memctl_options_t *popts)
1250 {
1251         unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1252         unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1253         unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1254         unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1255         unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1256
1257 #if defined(CONFIG_SYS_FSL_DDR3)
1258         if (popts->burst_length == DDR_BL8) {
1259                 /* We set BL/2 for fixed BL8 */
1260                 rrt = 0;        /* BL/2 clocks */
1261                 wwt = 0;        /* BL/2 clocks */
1262         } else {
1263                 /* We need to set BL/2 + 2 to BC4 and OTF */
1264                 rrt = 2;        /* BL/2 + 2 clocks */
1265                 wwt = 2;        /* BL/2 + 2 clocks */
1266         }
1267         dll_lock = 1;   /* tDLLK = 512 clocks from spec */
1268 #endif
1269         ddr->timing_cfg_4 = (0
1270                              | ((rwt & 0xf) << 28)
1271                              | ((wrt & 0xf) << 24)
1272                              | ((rrt & 0xf) << 20)
1273                              | ((wwt & 0xf) << 16)
1274                              | (dll_lock & 0x3)
1275                              );
1276         debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1277 }
1278
1279 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1280 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1281 {
1282         unsigned int rodt_on = 0;       /* Read to ODT on */
1283         unsigned int rodt_off = 0;      /* Read to ODT off */
1284         unsigned int wodt_on = 0;       /* Write to ODT on */
1285         unsigned int wodt_off = 0;      /* Write to ODT off */
1286
1287 #if defined(CONFIG_SYS_FSL_DDR3)
1288         /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1289         rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
1290         rodt_off = 4;   /*  4 clocks */
1291         wodt_on = 1;    /*  1 clocks */
1292         wodt_off = 4;   /*  4 clocks */
1293 #endif
1294
1295         ddr->timing_cfg_5 = (0
1296                              | ((rodt_on & 0x1f) << 24)
1297                              | ((rodt_off & 0x7) << 20)
1298                              | ((wodt_on & 0x1f) << 12)
1299                              | ((wodt_off & 0x7) << 8)
1300                              );
1301         debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1302 }
1303
1304 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
1305 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
1306 {
1307         unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1308         /* Normal Operation Full Calibration Time (tZQoper) */
1309         unsigned int zqoper = 0;
1310         /* Normal Operation Short Calibration Time (tZQCS) */
1311         unsigned int zqcs = 0;
1312
1313         if (zq_en) {
1314                 zqinit = 9;     /* 512 clocks */
1315                 zqoper = 8;     /* 256 clocks */
1316                 zqcs = 6;       /* 64 clocks */
1317         }
1318
1319         ddr->ddr_zq_cntl = (0
1320                             | ((zq_en & 0x1) << 31)
1321                             | ((zqinit & 0xF) << 24)
1322                             | ((zqoper & 0xF) << 16)
1323                             | ((zqcs & 0xF) << 8)
1324                             );
1325         debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
1326 }
1327
1328 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
1329 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1330                                 const memctl_options_t *popts)
1331 {
1332         /*
1333          * First DQS pulse rising edge after margining mode
1334          * is programmed (tWL_MRD)
1335          */
1336         unsigned int wrlvl_mrd = 0;
1337         /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1338         unsigned int wrlvl_odten = 0;
1339         /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1340         unsigned int wrlvl_dqsen = 0;
1341         /* WRLVL_SMPL: Write leveling sample time */
1342         unsigned int wrlvl_smpl = 0;
1343         /* WRLVL_WLR: Write leveling repeition time */
1344         unsigned int wrlvl_wlr = 0;
1345         /* WRLVL_START: Write leveling start time */
1346         unsigned int wrlvl_start = 0;
1347
1348         /* suggest enable write leveling for DDR3 due to fly-by topology */
1349         if (wrlvl_en) {
1350                 /* tWL_MRD min = 40 nCK, we set it 64 */
1351                 wrlvl_mrd = 0x6;
1352                 /* tWL_ODTEN 128 */
1353                 wrlvl_odten = 0x7;
1354                 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1355                 wrlvl_dqsen = 0x5;
1356                 /*
1357                  * Write leveling sample time at least need 6 clocks
1358                  * higher than tWLO to allow enough time for progagation
1359                  * delay and sampling the prime data bits.
1360                  */
1361                 wrlvl_smpl = 0xf;
1362                 /*
1363                  * Write leveling repetition time
1364                  * at least tWLO + 6 clocks clocks
1365                  * we set it 64
1366                  */
1367                 wrlvl_wlr = 0x6;
1368                 /*
1369                  * Write leveling start time
1370                  * The value use for the DQS_ADJUST for the first sample
1371                  * when write leveling is enabled. It probably needs to be
1372                  * overriden per platform.
1373                  */
1374                 wrlvl_start = 0x8;
1375                 /*
1376                  * Override the write leveling sample and start time
1377                  * according to specific board
1378                  */
1379                 if (popts->wrlvl_override) {
1380                         wrlvl_smpl = popts->wrlvl_sample;
1381                         wrlvl_start = popts->wrlvl_start;
1382                 }
1383         }
1384
1385         ddr->ddr_wrlvl_cntl = (0
1386                                | ((wrlvl_en & 0x1) << 31)
1387                                | ((wrlvl_mrd & 0x7) << 24)
1388                                | ((wrlvl_odten & 0x7) << 20)
1389                                | ((wrlvl_dqsen & 0x7) << 16)
1390                                | ((wrlvl_smpl & 0xf) << 12)
1391                                | ((wrlvl_wlr & 0x7) << 8)
1392                                | ((wrlvl_start & 0x1F) << 0)
1393                                );
1394         debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
1395         ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
1396         debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
1397         ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
1398         debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
1399
1400 }
1401
1402 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
1403 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
1404 {
1405         /* Self Refresh Idle Threshold */
1406         ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1407 }
1408
1409 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1410 {
1411         if (popts->addr_hash) {
1412                 ddr->ddr_eor = 0x40000000;      /* address hash enable */
1413                 puts("Address hashing enabled.\n");
1414         }
1415 }
1416
1417 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1418 {
1419         ddr->ddr_cdr1 = popts->ddr_cdr1;
1420         debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
1421 }
1422
1423 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1424 {
1425         ddr->ddr_cdr2 = popts->ddr_cdr2;
1426         debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
1427 }
1428
1429 unsigned int
1430 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1431 {
1432         unsigned int res = 0;
1433
1434         /*
1435          * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1436          * not set at the same time.
1437          */
1438         if (ddr->ddr_sdram_cfg & 0x10000000
1439             && ddr->ddr_sdram_cfg & 0x00008000) {
1440                 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1441                                 " should not be set at the same time.\n");
1442                 res++;
1443         }
1444
1445         return res;
1446 }
1447
1448 unsigned int
1449 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1450                                fsl_ddr_cfg_regs_t *ddr,
1451                                const common_timing_params_t *common_dimm,
1452                                const dimm_params_t *dimm_params,
1453                                unsigned int dbw_cap_adj,
1454                                unsigned int size_only)
1455 {
1456         unsigned int i;
1457         unsigned int cas_latency;
1458         unsigned int additive_latency;
1459         unsigned int sr_it;
1460         unsigned int zq_en;
1461         unsigned int wrlvl_en;
1462         unsigned int ip_rev = 0;
1463         unsigned int unq_mrs_en = 0;
1464         int cs_en = 1;
1465
1466         memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1467
1468         if (common_dimm == NULL) {
1469                 printf("Error: subset DIMM params struct null pointer\n");
1470                 return 1;
1471         }
1472
1473         /*
1474          * Process overrides first.
1475          *
1476          * FIXME: somehow add dereated caslat to this
1477          */
1478         cas_latency = (popts->cas_latency_override)
1479                 ? popts->cas_latency_override_value
1480                 : common_dimm->lowest_common_SPD_caslat;
1481
1482         additive_latency = (popts->additive_latency_override)
1483                 ? popts->additive_latency_override_value
1484                 : common_dimm->additive_latency;
1485
1486         sr_it = (popts->auto_self_refresh_en)
1487                 ? popts->sr_it
1488                 : 0;
1489         /* ZQ calibration */
1490         zq_en = (popts->zq_en) ? 1 : 0;
1491         /* write leveling */
1492         wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
1493
1494         /* Chip Select Memory Bounds (CSn_BNDS) */
1495         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1496                 unsigned long long ea, sa;
1497                 unsigned int cs_per_dimm
1498                         = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
1499                 unsigned int dimm_number
1500                         = i / cs_per_dimm;
1501                 unsigned long long rank_density
1502                         = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
1503
1504                 if (dimm_params[dimm_number].n_ranks == 0) {
1505                         debug("Skipping setup of CS%u "
1506                                 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
1507                         continue;
1508                 }
1509                 if (popts->memctl_interleaving) {
1510                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1511                         case FSL_DDR_CS0_CS1_CS2_CS3:
1512                                 break;
1513                         case FSL_DDR_CS0_CS1:
1514                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1515                                 if (i > 1)
1516                                         cs_en = 0;
1517                                 break;
1518                         case FSL_DDR_CS2_CS3:
1519                         default:
1520                                 if (i > 0)
1521                                         cs_en = 0;
1522                                 break;
1523                         }
1524                         sa = common_dimm->base_address;
1525                         ea = sa + common_dimm->total_mem - 1;
1526                 } else if (!popts->memctl_interleaving) {
1527                         /*
1528                          * If memory interleaving between controllers is NOT
1529                          * enabled, the starting address for each memory
1530                          * controller is distinct.  However, because rank
1531                          * interleaving is enabled, the starting and ending
1532                          * addresses of the total memory on that memory
1533                          * controller needs to be programmed into its
1534                          * respective CS0_BNDS.
1535                          */
1536                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1537                         case FSL_DDR_CS0_CS1_CS2_CS3:
1538                                 sa = common_dimm->base_address;
1539                                 ea = sa + common_dimm->total_mem - 1;
1540                                 break;
1541                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1542                                 if ((i >= 2) && (dimm_number == 0)) {
1543                                         sa = dimm_params[dimm_number].base_address +
1544                                               2 * rank_density;
1545                                         ea = sa + 2 * rank_density - 1;
1546                                 } else {
1547                                         sa = dimm_params[dimm_number].base_address;
1548                                         ea = sa + 2 * rank_density - 1;
1549                                 }
1550                                 break;
1551                         case FSL_DDR_CS0_CS1:
1552                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1553                                         sa = dimm_params[dimm_number].base_address;
1554                                         ea = sa + rank_density - 1;
1555                                         if (i != 1)
1556                                                 sa += (i % cs_per_dimm) * rank_density;
1557                                         ea += (i % cs_per_dimm) * rank_density;
1558                                 } else {
1559                                         sa = 0;
1560                                         ea = 0;
1561                                 }
1562                                 if (i == 0)
1563                                         ea += rank_density;
1564                                 break;
1565                         case FSL_DDR_CS2_CS3:
1566                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1567                                         sa = dimm_params[dimm_number].base_address;
1568                                         ea = sa + rank_density - 1;
1569                                         if (i != 3)
1570                                                 sa += (i % cs_per_dimm) * rank_density;
1571                                         ea += (i % cs_per_dimm) * rank_density;
1572                                 } else {
1573                                         sa = 0;
1574                                         ea = 0;
1575                                 }
1576                                 if (i == 2)
1577                                         ea += (rank_density >> dbw_cap_adj);
1578                                 break;
1579                         default:  /* No bank(chip-select) interleaving */
1580                                 sa = dimm_params[dimm_number].base_address;
1581                                 ea = sa + rank_density - 1;
1582                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1583                                         sa += (i % cs_per_dimm) * rank_density;
1584                                         ea += (i % cs_per_dimm) * rank_density;
1585                                 } else {
1586                                         sa = 0;
1587                                         ea = 0;
1588                                 }
1589                                 break;
1590                         }
1591                 }
1592
1593                 sa >>= 24;
1594                 ea >>= 24;
1595
1596                 if (cs_en) {
1597                         ddr->cs[i].bnds = (0
1598                                 | ((sa & 0xffff) << 16) /* starting address */
1599                                 | ((ea & 0xffff) << 0)  /* ending address */
1600                                 );
1601                 } else {
1602                         /* setting bnds to 0xffffffff for inactive CS */
1603                         ddr->cs[i].bnds = 0xffffffff;
1604                 }
1605
1606                 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1607                 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1608                 set_csn_config_2(i, ddr);
1609         }
1610
1611         /*
1612          * In the case we only need to compute the ddr sdram size, we only need
1613          * to set csn registers, so return from here.
1614          */
1615         if (size_only)
1616                 return 0;
1617
1618         set_ddr_eor(ddr, popts);
1619
1620 #if !defined(CONFIG_SYS_FSL_DDR1)
1621         set_timing_cfg_0(ddr, popts, dimm_params);
1622 #endif
1623
1624         set_timing_cfg_3(ddr, popts, common_dimm, cas_latency,
1625                          additive_latency);
1626         set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
1627         set_timing_cfg_2(ddr, popts, common_dimm,
1628                                 cas_latency, additive_latency);
1629
1630         set_ddr_cdr1(ddr, popts);
1631         set_ddr_cdr2(ddr, popts);
1632         set_ddr_sdram_cfg(ddr, popts, common_dimm);
1633         ip_rev = fsl_ddr_get_version();
1634         if (ip_rev > 0x40400)
1635                 unq_mrs_en = 1;
1636
1637         set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
1638         set_ddr_sdram_mode(ddr, popts, common_dimm,
1639                                 cas_latency, additive_latency, unq_mrs_en);
1640         set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en);
1641         set_ddr_sdram_interval(ddr, popts, common_dimm);
1642         set_ddr_data_init(ddr);
1643         set_ddr_sdram_clk_cntl(ddr, popts);
1644         set_ddr_init_addr(ddr);
1645         set_ddr_init_ext_addr(ddr);
1646         set_timing_cfg_4(ddr, popts);
1647         set_timing_cfg_5(ddr, cas_latency);
1648
1649         set_ddr_zq_cntl(ddr, zq_en);
1650         set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
1651
1652         set_ddr_sr_cntr(ddr, sr_it);
1653
1654         set_ddr_sdram_rcw(ddr, popts, common_dimm);
1655
1656 #ifdef CONFIG_SYS_FSL_DDR_EMU
1657         /* disble DDR training for emulator */
1658         ddr->debug[2] = 0x00000400;
1659         ddr->debug[4] = 0xff800000;
1660 #endif
1661         return check_fsl_memctl_config_regs(ddr);
1662 }