drivers/ddr/fsl/main.c

   1 /*
   2  * Copyright 2008-2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
  11  * Based on code from spd_sdram.c
  12  * Author: James Yang [at freescale.com]
  13  */
  14
  15 #include <common.h>
  16 #include <i2c.h>
  17 #include <fsl_ddr_sdram.h>
  18 #include <fsl_ddr.h>
  19
  20 /*
  21  * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
  22  * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
  23  * all Power SoCs. But it could be different for ARM SoCs. For example,
  24  * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
  25  * 0x00_8000_0000 ~ 0x00_ffff_ffff
  26  * 0x80_8000_0000 ~ 0xff_ffff_ffff
  27  */
  28 #ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
  29 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
  30 #endif
  31
  32 #ifdef CONFIG_PPC
  33 #include <asm/fsl_law.h>
  34
  35 void fsl_ddr_set_lawbar(
  36                 const common_timing_params_t *memctl_common_params,
  37                 unsigned int memctl_interleaved,
  38                 unsigned int ctrl_num);
  39 #endif
  40
  41 void fsl_ddr_set_intl3r(const unsigned int granule_size);
  42 #if defined(SPD_EEPROM_ADDRESS) || \
  43     defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
  44     defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
  45 #if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  46 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  47         [0][0] = SPD_EEPROM_ADDRESS,
  48 };
  49 #elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  50 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  51         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  52         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  53 };
  54 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  55 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  56         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  57         [1][0] = SPD_EEPROM_ADDRESS2,   /* controller 2 */
  58 };
  59 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  60 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  61         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  62         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  63         [1][0] = SPD_EEPROM_ADDRESS3,   /* controller 2 */
  64         [1][1] = SPD_EEPROM_ADDRESS4,   /* controller 2 */
  65 };
  66 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  67 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  68         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  69         [1][0] = SPD_EEPROM_ADDRESS2,   /* controller 2 */
  70         [2][0] = SPD_EEPROM_ADDRESS3,   /* controller 3 */
  71 };
  72 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  73 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  74         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  75         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  76         [1][0] = SPD_EEPROM_ADDRESS3,   /* controller 2 */
  77         [1][1] = SPD_EEPROM_ADDRESS4,   /* controller 2 */
  78         [2][0] = SPD_EEPROM_ADDRESS5,   /* controller 3 */
  79         [2][1] = SPD_EEPROM_ADDRESS6,   /* controller 3 */
  80 };
  81
  82 #endif
  83
  84 #define SPD_SPA0_ADDRESS        0x36
  85 #define SPD_SPA1_ADDRESS        0x37
  86
  87 static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
  88 {
  89         int ret;
  90 #ifdef CONFIG_SYS_FSL_DDR4
  91         uint8_t dummy = 0;
  92 #endif
  93
  94         i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
  95
  96 #ifdef CONFIG_SYS_FSL_DDR4
  97         /*
  98          * DDR4 SPD has 384 to 512 bytes
  99          * To access the lower 256 bytes, we need to set EE page address to 0
 100          * To access the upper 256 bytes, we need to set EE page address to 1
 101          * See Jedec standar No. 21-C for detail
 102          */
 103         i2c_write(SPD_SPA0_ADDRESS, 0, 1, &dummy, 1);
 104         ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 256);
 105         if (!ret) {
 106                 i2c_write(SPD_SPA1_ADDRESS, 0, 1, &dummy, 1);
 107                 ret = i2c_read(i2c_address, 0, 1,
 108                                (uchar *)((ulong)spd + 256),
 109                                min(256, sizeof(generic_spd_eeprom_t) - 256));
 110         }
 111 #else
 112         ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
 113                                 sizeof(generic_spd_eeprom_t));
 114 #endif
 115
 116         if (ret) {
 117                 if (i2c_address ==
 118 #ifdef SPD_EEPROM_ADDRESS
 119                                 SPD_EEPROM_ADDRESS
 120 #elif defined(SPD_EEPROM_ADDRESS1)
 121                                 SPD_EEPROM_ADDRESS1
 122 #endif
 123                                 ) {
 124                         printf("DDR: failed to read SPD from address %u\n",
 125                                 i2c_address);
 126                 } else {
 127                         debug("DDR: failed to read SPD from address %u\n",
 128                                 i2c_address);
 129                 }
 130                 memset(spd, 0, sizeof(generic_spd_eeprom_t));
 131         }
 132 }
 133
 134 __attribute__((weak, alias("__get_spd")))
 135 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
 136
 137 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 138                       unsigned int ctrl_num)
 139 {
 140         unsigned int i;
 141         unsigned int i2c_address = 0;
 142
 143         if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
 144                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
 145                 return;
 146         }
 147
 148         for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
 149                 i2c_address = spd_i2c_addr[ctrl_num][i];
 150                 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
 151         }
 152 }
 153 #else
 154 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 155                       unsigned int ctrl_num)
 156 {
 157 }
 158 #endif /* SPD_EEPROM_ADDRESSx */
 159
 160 /*
 161  * ASSUMPTIONS:
 162  *    - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
 163  *    - Same memory data bus width on all controllers
 164  *
 165  * NOTES:
 166  *
 167  * The memory controller and associated documentation use confusing
 168  * terminology when referring to the orgranization of DRAM.
 169  *
 170  * Here is a terminology translation table:
 171  *
 172  * memory controller/documention  |industry   |this code  |signals
 173  * -------------------------------|-----------|-----------|-----------------
 174  * physical bank/bank             |rank       |rank       |chip select (CS)
 175  * logical bank/sub-bank          |bank       |bank       |bank address (BA)
 176  * page/row                       |row        |page       |row address
 177  * ???                            |column     |column     |column address
 178  *
 179  * The naming confusion is further exacerbated by the descriptions of the
 180  * memory controller interleaving feature, where accesses are interleaved
 181  * _BETWEEN_ two seperate memory controllers.  This is configured only in
 182  * CS0_CONFIG[INTLV_CTL] of each memory controller.
 183  *
 184  * memory controller documentation | number of chip selects
 185  *                                 | per memory controller supported
 186  * --------------------------------|-----------------------------------------
 187  * cache line interleaving         | 1 (CS0 only)
 188  * page interleaving               | 1 (CS0 only)
 189  * bank interleaving               | 1 (CS0 only)
 190  * superbank interleraving         | depends on bank (chip select)
 191  *                                 |   interleraving [rank interleaving]
 192  *                                 |   mode used on every memory controller
 193  *
 194  * Even further confusing is the existence of the interleaving feature
 195  * _WITHIN_ each memory controller.  The feature is referred to in
 196  * documentation as chip select interleaving or bank interleaving,
 197  * although it is configured in the DDR_SDRAM_CFG field.
 198  *
 199  * Name of field                | documentation name    | this code
 200  * -----------------------------|-----------------------|------------------
 201  * DDR_SDRAM_CFG[BA_INTLV_CTL]  | Bank (chip select)    | rank interleaving
 202  *                              |  interleaving
 203  */
 204
 205 const char *step_string_tbl[] = {
 206         "STEP_GET_SPD",
 207         "STEP_COMPUTE_DIMM_PARMS",
 208         "STEP_COMPUTE_COMMON_PARMS",
 209         "STEP_GATHER_OPTS",
 210         "STEP_ASSIGN_ADDRESSES",
 211         "STEP_COMPUTE_REGS",
 212         "STEP_PROGRAM_REGS",
 213         "STEP_ALL"
 214 };
 215
 216 const char * step_to_string(unsigned int step) {
 217
 218         unsigned int s = __ilog2(step);
 219
 220         if ((1 << s) != step)
 221                 return step_string_tbl[7];
 222
 223         return step_string_tbl[s];
 224 }
 225
 226 static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
 227                           unsigned int dbw_cap_adj[])
 228 {
 229         int i, j;
 230         unsigned long long total_mem, current_mem_base, total_ctlr_mem;
 231         unsigned long long rank_density, ctlr_density = 0;
 232
 233         /*
 234          * If a reduced data width is requested, but the SPD
 235          * specifies a physically wider device, adjust the
 236          * computed dimm capacities accordingly before
 237          * assigning addresses.
 238          */
 239         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 240                 unsigned int found = 0;
 241
 242                 switch (pinfo->memctl_opts[i].data_bus_width) {
 243                 case 2:
 244                         /* 16-bit */
 245                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 246                                 unsigned int dw;
 247                                 if (!pinfo->dimm_params[i][j].n_ranks)
 248                                         continue;
 249                                 dw = pinfo->dimm_params[i][j].primary_sdram_width;
 250                                 if ((dw == 72 || dw == 64)) {
 251                                         dbw_cap_adj[i] = 2;
 252                                         break;
 253                                 } else if ((dw == 40 || dw == 32)) {
 254                                         dbw_cap_adj[i] = 1;
 255                                         break;
 256                                 }
 257                         }
 258                         break;
 259
 260                 case 1:
 261                         /* 32-bit */
 262                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 263                                 unsigned int dw;
 264                                 dw = pinfo->dimm_params[i][j].data_width;
 265                                 if (pinfo->dimm_params[i][j].n_ranks
 266                                     && (dw == 72 || dw == 64)) {
 267                                         /*
 268                                          * FIXME: can't really do it
 269                                          * like this because this just
 270                                          * further reduces the memory
 271                                          */
 272                                         found = 1;
 273                                         break;
 274                                 }
 275                         }
 276                         if (found) {
 277                                 dbw_cap_adj[i] = 1;
 278                         }
 279                         break;
 280
 281                 case 0:
 282                         /* 64-bit */
 283                         break;
 284
 285                 default:
 286                         printf("unexpected data bus width "
 287                                 "specified controller %u\n", i);
 288                         return 1;
 289                 }
 290                 debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
 291         }
 292
 293         current_mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
 294         total_mem = 0;
 295         if (pinfo->memctl_opts[0].memctl_interleaving) {
 296                 rank_density = pinfo->dimm_params[0][0].rank_density >>
 297                                         dbw_cap_adj[0];
 298                 switch (pinfo->memctl_opts[0].ba_intlv_ctl &
 299                                         FSL_DDR_CS0_CS1_CS2_CS3) {
 300                 case FSL_DDR_CS0_CS1_CS2_CS3:
 301                         ctlr_density = 4 * rank_density;
 302                         break;
 303                 case FSL_DDR_CS0_CS1:
 304                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 305                         ctlr_density = 2 * rank_density;
 306                         break;
 307                 case FSL_DDR_CS2_CS3:
 308                 default:
 309                         ctlr_density = rank_density;
 310                         break;
 311                 }
 312                 debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
 313                         rank_density, ctlr_density);
 314                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 315                         if (pinfo->memctl_opts[i].memctl_interleaving) {
 316                                 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
 317                                 case FSL_DDR_256B_INTERLEAVING:
 318                                 case FSL_DDR_CACHE_LINE_INTERLEAVING:
 319                                 case FSL_DDR_PAGE_INTERLEAVING:
 320                                 case FSL_DDR_BANK_INTERLEAVING:
 321                                 case FSL_DDR_SUPERBANK_INTERLEAVING:
 322                                         total_ctlr_mem = 2 * ctlr_density;
 323                                         break;
 324                                 case FSL_DDR_3WAY_1KB_INTERLEAVING:
 325                                 case FSL_DDR_3WAY_4KB_INTERLEAVING:
 326                                 case FSL_DDR_3WAY_8KB_INTERLEAVING:
 327                                         total_ctlr_mem = 3 * ctlr_density;
 328                                         break;
 329                                 case FSL_DDR_4WAY_1KB_INTERLEAVING:
 330                                 case FSL_DDR_4WAY_4KB_INTERLEAVING:
 331                                 case FSL_DDR_4WAY_8KB_INTERLEAVING:
 332                                         total_ctlr_mem = 4 * ctlr_density;
 333                                         break;
 334                                 default:
 335                                         panic("Unknown interleaving mode");
 336                                 }
 337                                 pinfo->common_timing_params[i].base_address =
 338                                                         current_mem_base;
 339                                 pinfo->common_timing_params[i].total_mem =
 340                                                         total_ctlr_mem;
 341                                 total_mem = current_mem_base + total_ctlr_mem;
 342                                 debug("ctrl %d base 0x%llx\n", i, current_mem_base);
 343                                 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 344                         } else {
 345                                 /* when 3rd controller not interleaved */
 346                                 current_mem_base = total_mem;
 347                                 total_ctlr_mem = 0;
 348                                 pinfo->common_timing_params[i].base_address =
 349                                                         current_mem_base;
 350                                 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 351                                         unsigned long long cap =
 352                                                 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
 353                                         pinfo->dimm_params[i][j].base_address =
 354                                                 current_mem_base;
 355                                         debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
 356                                         current_mem_base += cap;
 357                                         total_ctlr_mem += cap;
 358                                 }
 359                                 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 360                                 pinfo->common_timing_params[i].total_mem =
 361                                                         total_ctlr_mem;
 362                                 total_mem += total_ctlr_mem;
 363                         }
 364                 }
 365         } else {
 366                 /*
 367                  * Simple linear assignment if memory
 368                  * controllers are not interleaved.
 369                  */
 370                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 371                         total_ctlr_mem = 0;
 372                         pinfo->common_timing_params[i].base_address =
 373                                                 current_mem_base;
 374                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 375                                 /* Compute DIMM base addresses. */
 376                                 unsigned long long cap =
 377                                         pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
 378                                 pinfo->dimm_params[i][j].base_address =
 379                                         current_mem_base;
 380                                 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
 381                                 current_mem_base += cap;
 382                                 total_ctlr_mem += cap;
 383                         }
 384                         debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 385                         pinfo->common_timing_params[i].total_mem =
 386                                                         total_ctlr_mem;
 387                         total_mem += total_ctlr_mem;
 388                 }
 389         }
 390         debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
 391
 392         return total_mem;
 393 }
 394
 395 /* Use weak function to allow board file to override the address assignment */
 396 __attribute__((weak, alias("__step_assign_addresses")))
 397 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
 398                           unsigned int dbw_cap_adj[]);
 399
 400 unsigned long long
 401 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 402                                        unsigned int size_only)
 403 {
 404         unsigned int i, j;
 405         unsigned long long total_mem = 0;
 406         int assert_reset;
 407
 408         fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
 409         common_timing_params_t *timing_params = pinfo->common_timing_params;
 410         assert_reset = board_need_mem_reset();
 411
 412         /* data bus width capacity adjust shift amount */
 413         unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
 414
 415         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 416                 dbw_capacity_adjust[i] = 0;
 417         }
 418
 419         debug("starting at step %u (%s)\n",
 420               start_step, step_to_string(start_step));
 421
 422         switch (start_step) {
 423         case STEP_GET_SPD:
 424 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
 425                 /* STEP 1:  Gather all DIMM SPD data */
 426                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 427                         fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
 428                 }
 429
 430         case STEP_COMPUTE_DIMM_PARMS:
 431                 /* STEP 2:  Compute DIMM parameters from SPD data */
 432
 433                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 434                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 435                                 unsigned int retval;
 436                                 generic_spd_eeprom_t *spd =
 437                                         &(pinfo->spd_installed_dimms[i][j]);
 438                                 dimm_params_t *pdimm =
 439                                         &(pinfo->dimm_params[i][j]);
 440
 441                                 retval = compute_dimm_parameters(spd, pdimm, i);
 442 #ifdef CONFIG_SYS_DDR_RAW_TIMING
 443                                 if (!i && !j && retval) {
 444                                         printf("SPD error on controller %d! "
 445                                         "Trying fallback to raw timing "
 446                                         "calculation\n", i);
 447                                         fsl_ddr_get_dimm_params(pdimm, i, j);
 448                                 }
 449 #else
 450                                 if (retval == 2) {
 451                                         printf("Error: compute_dimm_parameters"
 452                                         " non-zero returned FATAL value "
 453                                         "for memctl=%u dimm=%u\n", i, j);
 454                                         return 0;
 455                                 }
 456 #endif
 457                                 if (retval) {
 458                                         debug("Warning: compute_dimm_parameters"
 459                                         " non-zero return value for memctl=%u "
 460                                         "dimm=%u\n", i, j);
 461                                 }
 462                         }
 463                 }
 464
 465 #elif defined(CONFIG_SYS_DDR_RAW_TIMING)
 466         case STEP_COMPUTE_DIMM_PARMS:
 467                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 468                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 469                                 dimm_params_t *pdimm =
 470                                         &(pinfo->dimm_params[i][j]);
 471                                 fsl_ddr_get_dimm_params(pdimm, i, j);
 472                         }
 473                 }
 474                 debug("Filling dimm parameters from board specific file\n");
 475 #endif
 476         case STEP_COMPUTE_COMMON_PARMS:
 477                 /*
 478                  * STEP 3: Compute a common set of timing parameters
 479                  * suitable for all of the DIMMs on each memory controller
 480                  */
 481                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 482                         debug("Computing lowest common DIMM"
 483                                 " parameters for memctl=%u\n", i);
 484                         compute_lowest_common_dimm_parameters(
 485                                 pinfo->dimm_params[i],
 486                                 &timing_params[i],
 487                                 CONFIG_DIMM_SLOTS_PER_CTLR);
 488                 }
 489
 490         case STEP_GATHER_OPTS:
 491                 /* STEP 4:  Gather configuration requirements from user */
 492                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 493                         debug("Reloading memory controller "
 494                                 "configuration options for memctl=%u\n", i);
 495                         /*
 496                          * This "reloads" the memory controller options
 497                          * to defaults.  If the user "edits" an option,
 498                          * next_step points to the step after this,
 499                          * which is currently STEP_ASSIGN_ADDRESSES.
 500                          */
 501                         populate_memctl_options(
 502                                         timing_params[i].all_dimms_registered,
 503                                         &pinfo->memctl_opts[i],
 504                                         pinfo->dimm_params[i], i);
 505                         /*
 506                          * For RDIMMs, JEDEC spec requires clocks to be stable
 507                          * before reset signal is deasserted. For the boards
 508                          * using fixed parameters, this function should be
 509                          * be called from board init file.
 510                          */
 511                         if (timing_params[i].all_dimms_registered)
 512                                 assert_reset = 1;
 513                 }
 514                 if (assert_reset) {
 515                         debug("Asserting mem reset\n");
 516                         board_assert_mem_reset();
 517                 }
 518
 519         case STEP_ASSIGN_ADDRESSES:
 520                 /* STEP 5:  Assign addresses to chip selects */
 521                 check_interleaving_options(pinfo);
 522                 total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
 523
 524         case STEP_COMPUTE_REGS:
 525                 /* STEP 6:  compute controller register values */
 526                 debug("FSL Memory ctrl register computation\n");
 527                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 528                         if (timing_params[i].ndimms_present == 0) {
 529                                 memset(&ddr_reg[i], 0,
 530                                         sizeof(fsl_ddr_cfg_regs_t));
 531                                 continue;
 532                         }
 533
 534                         compute_fsl_memctl_config_regs(
 535                                         &pinfo->memctl_opts[i],
 536                                         &ddr_reg[i], &timing_params[i],
 537                                         pinfo->dimm_params[i],
 538                                         dbw_capacity_adjust[i],
 539                                         size_only);
 540                 }
 541
 542         default:
 543                 break;
 544         }
 545
 546         {
 547                 /*
 548                  * Compute the amount of memory available just by
 549                  * looking for the highest valid CSn_BNDS value.
 550                  * This allows us to also experiment with using
 551                  * only CS0 when using dual-rank DIMMs.
 552                  */
 553                 unsigned int max_end = 0;
 554
 555                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 556                         for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
 557                                 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
 558                                 if (reg->cs[j].config & 0x80000000) {
 559                                         unsigned int end;
 560                                         /*
 561                                          * 0xfffffff is a special value we put
 562                                          * for unused bnds
 563                                          */
 564                                         if (reg->cs[j].bnds == 0xffffffff)
 565                                                 continue;
 566                                         end = reg->cs[j].bnds & 0xffff;
 567                                         if (end > max_end) {
 568                                                 max_end = end;
 569                                         }
 570                                 }
 571                         }
 572                 }
 573
 574                 total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
 575                             0xFFFFFFULL) - CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
 576         }
 577
 578         return total_mem;
 579 }
 580
 581 /*
 582  * fsl_ddr_sdram() -- this is the main function to be called by
 583  *      initdram() in the board file.
 584  *
 585  * It returns amount of memory configured in bytes.
 586  */
 587 phys_size_t fsl_ddr_sdram(void)
 588 {
 589         unsigned int i;
 590 #ifdef CONFIG_PPC
 591         unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
 592 #endif
 593         unsigned long long total_memory;
 594         fsl_ddr_info_t info;
 595         int deassert_reset;
 596
 597         /* Reset info structure. */
 598         memset(&info, 0, sizeof(fsl_ddr_info_t));
 599
 600         /* Compute it once normally. */
 601 #ifdef CONFIG_FSL_DDR_INTERACTIVE
 602         if (tstc() && (getc() == 'd')) {        /* we got a key press of 'd' */
 603                 total_memory = fsl_ddr_interactive(&info, 0);
 604         } else if (fsl_ddr_interactive_env_var_exists()) {
 605                 total_memory = fsl_ddr_interactive(&info, 1);
 606         } else
 607 #endif
 608                 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
 609
 610         /* setup 3-way interleaving before enabling DDRC */
 611         if (info.memctl_opts[0].memctl_interleaving) {
 612                 switch (info.memctl_opts[0].memctl_interleaving_mode) {
 613                 case FSL_DDR_3WAY_1KB_INTERLEAVING:
 614                 case FSL_DDR_3WAY_4KB_INTERLEAVING:
 615                 case FSL_DDR_3WAY_8KB_INTERLEAVING:
 616                         fsl_ddr_set_intl3r(
 617                                 info.memctl_opts[0].memctl_interleaving_mode);
 618                         break;
 619                 default:
 620                         break;
 621                 }
 622         }
 623
 624         /*
 625          * Program configuration registers.
 626          * JEDEC specs requires clocks to be stable before deasserting reset
 627          * for RDIMMs. Clocks start after chip select is enabled and clock
 628          * control register is set. During step 1, all controllers have their
 629          * registers set but not enabled. Step 2 proceeds after deasserting
 630          * reset through board FPGA or GPIO.
 631          * For non-registered DIMMs, initialization can go through but it is
 632          * also OK to follow the same flow.
 633          */
 634         deassert_reset = board_need_mem_reset();
 635         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 636                 if (info.common_timing_params[i].all_dimms_registered)
 637                         deassert_reset = 1;
 638         }
 639         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 640                 debug("Programming controller %u\n", i);
 641                 if (info.common_timing_params[i].ndimms_present == 0) {
 642                         debug("No dimms present on controller %u; "
 643                                         "skipping programming\n", i);
 644                         continue;
 645                 }
 646                 /*
 647                  * The following call with step = 1 returns before enabling
 648                  * the controller. It has to finish with step = 2 later.
 649                  */
 650                 fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i,
 651                                         deassert_reset ? 1 : 0);
 652         }
 653         if (deassert_reset) {
 654                 /* Use board FPGA or GPIO to deassert reset signal */
 655                 debug("Deasserting mem reset\n");
 656                 board_deassert_mem_reset();
 657                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 658                         /* Call with step = 2 to continue initialization */
 659                         fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]),
 660                                                 i, 2);
 661                 }
 662         }
 663
 664 #ifdef CONFIG_PPC
 665         /* program LAWs */
 666         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 667                 if (info.memctl_opts[i].memctl_interleaving) {
 668                         switch (info.memctl_opts[i].memctl_interleaving_mode) {
 669                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
 670                         case FSL_DDR_PAGE_INTERLEAVING:
 671                         case FSL_DDR_BANK_INTERLEAVING:
 672                         case FSL_DDR_SUPERBANK_INTERLEAVING:
 673                                 if (i == 0) {
 674                                         law_memctl = LAW_TRGT_IF_DDR_INTRLV;
 675                                         fsl_ddr_set_lawbar(&info.common_timing_params[i],
 676                                                 law_memctl, i);
 677                                 } else if (i == 2) {
 678                                         law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
 679                                         fsl_ddr_set_lawbar(&info.common_timing_params[i],
 680                                                 law_memctl, i);
 681                                 }
 682                                 break;
 683                         case FSL_DDR_3WAY_1KB_INTERLEAVING:
 684                         case FSL_DDR_3WAY_4KB_INTERLEAVING:
 685                         case FSL_DDR_3WAY_8KB_INTERLEAVING:
 686                                 law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
 687                                 if (i == 0) {
 688                                         fsl_ddr_set_lawbar(&info.common_timing_params[i],
 689                                                 law_memctl, i);
 690                                 }
 691                                 break;
 692                         case FSL_DDR_4WAY_1KB_INTERLEAVING:
 693                         case FSL_DDR_4WAY_4KB_INTERLEAVING:
 694                         case FSL_DDR_4WAY_8KB_INTERLEAVING:
 695                                 law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
 696                                 if (i == 0)
 697                                         fsl_ddr_set_lawbar(&info.common_timing_params[i],
 698                                                 law_memctl, i);
 699                                 /* place holder for future 4-way interleaving */
 700                                 break;
 701                         default:
 702                                 break;
 703                         }
 704                 } else {
 705                         switch (i) {
 706                         case 0:
 707                                 law_memctl = LAW_TRGT_IF_DDR_1;
 708                                 break;
 709                         case 1:
 710                                 law_memctl = LAW_TRGT_IF_DDR_2;
 711                                 break;
 712                         case 2:
 713                                 law_memctl = LAW_TRGT_IF_DDR_3;
 714                                 break;
 715                         case 3:
 716                                 law_memctl = LAW_TRGT_IF_DDR_4;
 717                                 break;
 718                         default:
 719                                 break;
 720                         }
 721                         fsl_ddr_set_lawbar(&info.common_timing_params[i],
 722                                         law_memctl, i);
 723                 }
 724         }
 725 #endif
 726
 727         debug("total_memory by %s = %llu\n", __func__, total_memory);
 728
 729 #if !defined(CONFIG_PHYS_64BIT)
 730         /* Check for 4G or more.  Bad. */
 731         if (total_memory >= (1ull << 32)) {
 732                 puts("Detected ");
 733                 print_size(total_memory, " of memory\n");
 734                 printf("       This U-Boot only supports < 4G of DDR\n");
 735                 printf("       You could rebuild it with CONFIG_PHYS_64BIT\n");
 736                 printf("       "); /* re-align to match init_func_ram print */
 737                 total_memory = CONFIG_MAX_MEM_MAPPED;
 738         }
 739 #endif
 740
 741         return total_memory;
 742 }
 743
 744 /*
 745  * fsl_ddr_sdram_size() - This function only returns the size of the total
 746  * memory without setting ddr control registers.
 747  */
 748 phys_size_t
 749 fsl_ddr_sdram_size(void)
 750 {
 751         fsl_ddr_info_t  info;
 752         unsigned long long total_memory = 0;
 753
 754         memset(&info, 0 , sizeof(fsl_ddr_info_t));
 755
 756         /* Compute it once normally. */
 757         total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
 758
 759         return total_memory;
 760 }