drivers/fpga/zynqpl.c

   1 /*
   2  * (C) Copyright 2012-2013, Xilinx, Michal Simek
   3  *
   4  * (C) Copyright 2012
   5  * Joe Hershberger <joe.hershberger@ni.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/io.h>
  12 #include <fs.h>
  13 #include <zynqpl.h>
  14 #include <linux/sizes.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/sys_proto.h>
  17
  18 #define DEVCFG_CTRL_PCFG_PROG_B         0x40000000
  19 #define DEVCFG_ISR_FATAL_ERROR_MASK     0x00740040
  20 #define DEVCFG_ISR_ERROR_FLAGS_MASK     0x00340840
  21 #define DEVCFG_ISR_RX_FIFO_OV           0x00040000
  22 #define DEVCFG_ISR_DMA_DONE             0x00002000
  23 #define DEVCFG_ISR_PCFG_DONE            0x00000004
  24 #define DEVCFG_STATUS_DMA_CMD_Q_F       0x80000000
  25 #define DEVCFG_STATUS_DMA_CMD_Q_E       0x40000000
  26 #define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000
  27 #define DEVCFG_STATUS_PCFG_INIT         0x00000010
  28 #define DEVCFG_MCTRL_PCAP_LPBK          0x00000010
  29 #define DEVCFG_MCTRL_RFIFO_FLUSH        0x00000002
  30 #define DEVCFG_MCTRL_WFIFO_FLUSH        0x00000001
  31
  32 #ifndef CONFIG_SYS_FPGA_WAIT
  33 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100  /* 10 ms */
  34 #endif
  35
  36 #ifndef CONFIG_SYS_FPGA_PROG_TIME
  37 #define CONFIG_SYS_FPGA_PROG_TIME       (CONFIG_SYS_HZ * 4) /* 4 s */
  38 #endif
  39
  40 static int zynq_info(xilinx_desc *desc)
  41 {
  42         return FPGA_SUCCESS;
  43 }
  44
  45 #define DUMMY_WORD      0xffffffff
  46
  47 /* Xilinx binary format header */
  48 static const u32 bin_format[] = {
  49         DUMMY_WORD, /* Dummy words */
  50         DUMMY_WORD,
  51         DUMMY_WORD,
  52         DUMMY_WORD,
  53         DUMMY_WORD,
  54         DUMMY_WORD,
  55         DUMMY_WORD,
  56         DUMMY_WORD,
  57         0x000000bb, /* Sync word */
  58         0x11220044, /* Sync word */
  59         DUMMY_WORD,
  60         DUMMY_WORD,
  61         0xaa995566, /* Sync word */
  62 };
  63
  64 #define SWAP_NO         1
  65 #define SWAP_DONE       2
  66
  67 /*
  68  * Load the whole word from unaligned buffer
  69  * Keep in your mind that it is byte loading on little-endian system
  70  */
  71 static u32 load_word(const void *buf, u32 swap)
  72 {
  73         u32 word = 0;
  74         u8 *bitc = (u8 *)buf;
  75         int p;
  76
  77         if (swap == SWAP_NO) {
  78                 for (p = 0; p < 4; p++) {
  79                         word <<= 8;
  80                         word |= bitc[p];
  81                 }
  82         } else {
  83                 for (p = 3; p >= 0; p--) {
  84                         word <<= 8;
  85                         word |= bitc[p];
  86                 }
  87         }
  88
  89         return word;
  90 }
  91
  92 static u32 check_header(const void *buf)
  93 {
  94         u32 i, pattern;
  95         int swap = SWAP_NO;
  96         u32 *test = (u32 *)buf;
  97
  98         debug("%s: Let's check bitstream header\n", __func__);
  99
 100         /* Checking that passing bin is not a bitstream */
 101         for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
 102                 pattern = load_word(&test[i], swap);
 103
 104                 /*
 105                  * Bitstreams in binary format are swapped
 106                  * compare to regular bistream.
 107                  * Do not swap dummy word but if swap is done assume
 108                  * that parsing buffer is binary format
 109                  */
 110                 if ((__swab32(pattern) != DUMMY_WORD) &&
 111                     (__swab32(pattern) == bin_format[i])) {
 112                         pattern = __swab32(pattern);
 113                         swap = SWAP_DONE;
 114                         debug("%s: data swapped - let's swap\n", __func__);
 115                 }
 116
 117                 debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i,
 118                       (u32)&test[i], pattern, bin_format[i]);
 119                 if (pattern != bin_format[i]) {
 120                         debug("%s: Bitstream is not recognized\n", __func__);
 121                         return 0;
 122                 }
 123         }
 124         debug("%s: Found bitstream header at %x %s swapinng\n", __func__,
 125               (u32)buf, swap == SWAP_NO ? "without" : "with");
 126
 127         return swap;
 128 }
 129
 130 static void *check_data(u8 *buf, size_t bsize, u32 *swap)
 131 {
 132         u32 word, p = 0; /* possition */
 133
 134         /* Because buf doesn't need to be aligned let's read it by chars */
 135         for (p = 0; p < bsize; p++) {
 136                 word = load_word(&buf[p], SWAP_NO);
 137                 debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]);
 138
 139                 /* Find the first bitstream dummy word */
 140                 if (word == DUMMY_WORD) {
 141                         debug("%s: Found dummy word at position %x/%x\n",
 142                               __func__, p, (u32)&buf[p]);
 143                         *swap = check_header(&buf[p]);
 144                         if (*swap) {
 145                                 /* FIXME add full bitstream checking here */
 146                                 return &buf[p];
 147                         }
 148                 }
 149                 /* Loop can be huge - support CTRL + C */
 150                 if (ctrlc())
 151                         return NULL;
 152         }
 153         return NULL;
 154 }
 155
 156 static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen)
 157 {
 158         unsigned long ts;
 159         u32 isr_status;
 160
 161         /* Set up the transfer */
 162         writel((u32)srcbuf, &devcfg_base->dma_src_addr);
 163         writel(dstbuf, &devcfg_base->dma_dst_addr);
 164         writel(srclen, &devcfg_base->dma_src_len);
 165         writel(dstlen, &devcfg_base->dma_dst_len);
 166
 167         isr_status = readl(&devcfg_base->int_sts);
 168
 169         /* Polling the PCAP_INIT status for Set */
 170         ts = get_timer(0);
 171         while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
 172                 if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
 173                         debug("%s: Error: isr = 0x%08X\n", __func__,
 174                               isr_status);
 175                         debug("%s: Write count = 0x%08X\n", __func__,
 176                               readl(&devcfg_base->write_count));
 177                         debug("%s: Read count = 0x%08X\n", __func__,
 178                               readl(&devcfg_base->read_count));
 179
 180                         return FPGA_FAIL;
 181                 }
 182                 if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
 183                         printf("%s: Timeout wait for DMA to complete\n",
 184                                __func__);
 185                         return FPGA_FAIL;
 186                 }
 187                 isr_status = readl(&devcfg_base->int_sts);
 188         }
 189
 190         debug("%s: DMA transfer is done\n", __func__);
 191
 192         /* Clear out the DMA status */
 193         writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
 194
 195         return FPGA_SUCCESS;
 196 }
 197
 198 static int zynq_dma_xfer_init(bitstream_type bstype)
 199 {
 200         u32 status, control, isr_status;
 201         unsigned long ts;
 202
 203         /* Clear loopback bit */
 204         clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
 205
 206         if (bstype != BIT_PARTIAL) {
 207                 zynq_slcr_devcfg_disable();
 208
 209                 /* Setting PCFG_PROG_B signal to high */
 210                 control = readl(&devcfg_base->ctrl);
 211                 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
 212                 /* Setting PCFG_PROG_B signal to low */
 213                 writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
 214
 215                 /* Polling the PCAP_INIT status for Reset */
 216                 ts = get_timer(0);
 217                 while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
 218                         if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
 219                                 printf("%s: Timeout wait for INIT to clear\n",
 220                                        __func__);
 221                                 return FPGA_FAIL;
 222                         }
 223                 }
 224
 225                 /* Setting PCFG_PROG_B signal to high */
 226                 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
 227
 228                 /* Polling the PCAP_INIT status for Set */
 229                 ts = get_timer(0);
 230                 while (!(readl(&devcfg_base->status) &
 231                         DEVCFG_STATUS_PCFG_INIT)) {
 232                         if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
 233                                 printf("%s: Timeout wait for INIT to set\n",
 234                                        __func__);
 235                                 return FPGA_FAIL;
 236                         }
 237                 }
 238         }
 239
 240         isr_status = readl(&devcfg_base->int_sts);
 241
 242         /* Clear it all, so if Boot ROM comes back, it can proceed */
 243         writel(0xFFFFFFFF, &devcfg_base->int_sts);
 244
 245         if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) {
 246                 debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status);
 247
 248                 /* If RX FIFO overflow, need to flush RX FIFO first */
 249                 if (isr_status & DEVCFG_ISR_RX_FIFO_OV) {
 250                         writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl);
 251                         writel(0xFFFFFFFF, &devcfg_base->int_sts);
 252                 }
 253                 return FPGA_FAIL;
 254         }
 255
 256         status = readl(&devcfg_base->status);
 257
 258         debug("%s: Status = 0x%08X\n", __func__, status);
 259
 260         if (status & DEVCFG_STATUS_DMA_CMD_Q_F) {
 261                 debug("%s: Error: device busy\n", __func__);
 262                 return FPGA_FAIL;
 263         }
 264
 265         debug("%s: Device ready\n", __func__);
 266
 267         if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) {
 268                 if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) {
 269                         /* Error state, transfer cannot occur */
 270                         debug("%s: ISR indicates error\n", __func__);
 271                         return FPGA_FAIL;
 272                 } else {
 273                         /* Clear out the status */
 274                         writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
 275                 }
 276         }
 277
 278         if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) {
 279                 /* Clear the count of completed DMA transfers */
 280                 writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status);
 281         }
 282
 283         return FPGA_SUCCESS;
 284 }
 285
 286 static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap)
 287 {
 288         u32 *new_buf;
 289         u32 i;
 290
 291         if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
 292                 new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
 293
 294                 /*
 295                  * This might be dangerous but permits to flash if
 296                  * ARCH_DMA_MINALIGN is greater than header size
 297                  */
 298                 if (new_buf > buf) {
 299                         debug("%s: Aligned buffer is after buffer start\n",
 300                               __func__);
 301                         new_buf -= ARCH_DMA_MINALIGN;
 302                 }
 303                 printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
 304                        (u32)buf, (u32)new_buf, swap);
 305
 306                 for (i = 0; i < (len/4); i++)
 307                         new_buf[i] = load_word(&buf[i], swap);
 308
 309                 buf = new_buf;
 310         } else if (swap != SWAP_DONE) {
 311                 /* For bitstream which are aligned */
 312                 u32 *new_buf = (u32 *)buf;
 313
 314                 printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
 315                        swap);
 316
 317                 for (i = 0; i < (len/4); i++)
 318                         new_buf[i] = load_word(&buf[i], swap);
 319         }
 320
 321         return buf;
 322 }
 323
 324 static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
 325                                    size_t bsize, u32 blocksize, u32 *swap,
 326                                    bitstream_type *bstype)
 327 {
 328         u32 *buf_start;
 329         u32 diff;
 330
 331         buf_start = check_data((u8 *)buf, blocksize, swap);
 332
 333         if (!buf_start)
 334                 return FPGA_FAIL;
 335
 336         /* Check if data is postpone from start */
 337         diff = (u32)buf_start - (u32)buf;
 338         if (diff) {
 339                 printf("%s: Bitstream is not validated yet (diff %x)\n",
 340                        __func__, diff);
 341                 return FPGA_FAIL;
 342         }
 343
 344         if ((u32)buf < SZ_1M) {
 345                 printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
 346                        __func__, (u32)buf);
 347                 return FPGA_FAIL;
 348         }
 349
 350         if (zynq_dma_xfer_init(*bstype))
 351                 return FPGA_FAIL;
 352
 353         return 0;
 354 }
 355
 356 static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize,
 357                      bitstream_type bstype)
 358 {
 359         unsigned long ts; /* Timestamp */
 360         u32 isr_status, swap;
 361
 362         /*
 363          * send bsize inplace of blocksize as it was not a bitstream
 364          * in chunks
 365          */
 366         if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap,
 367                                     &bstype))
 368                 return FPGA_FAIL;
 369
 370         buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap);
 371
 372         debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
 373         debug("%s: Size = %zu\n", __func__, bsize);
 374
 375         /* flush(clean & invalidate) d-cache range buf */
 376         flush_dcache_range((u32)buf, (u32)buf +
 377                            roundup(bsize, ARCH_DMA_MINALIGN));
 378
 379         if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
 380                 return FPGA_FAIL;
 381
 382         isr_status = readl(&devcfg_base->int_sts);
 383         /* Check FPGA configuration completion */
 384         ts = get_timer(0);
 385         while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
 386                 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
 387                         printf("%s: Timeout wait for FPGA to config\n",
 388                                __func__);
 389                         return FPGA_FAIL;
 390                 }
 391                 isr_status = readl(&devcfg_base->int_sts);
 392         }
 393
 394         debug("%s: FPGA config done\n", __func__);
 395
 396         if (bstype != BIT_PARTIAL)
 397                 zynq_slcr_devcfg_enable();
 398
 399         return FPGA_SUCCESS;
 400 }
 401
 402 #if defined(CONFIG_CMD_FPGA_LOADFS)
 403 static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
 404                        fpga_fs_info *fsinfo)
 405 {
 406         unsigned long ts; /* Timestamp */
 407         u32 isr_status, swap;
 408         u32 partialbit = 0;
 409         loff_t blocksize, actread;
 410         loff_t pos = 0;
 411         int fstype;
 412         char *interface, *dev_part, *filename;
 413
 414         blocksize = fsinfo->blocksize;
 415         interface = fsinfo->interface;
 416         dev_part = fsinfo->dev_part;
 417         filename = fsinfo->filename;
 418         fstype = fsinfo->fstype;
 419
 420         if (fs_set_blk_dev(interface, dev_part, fstype))
 421                 return FPGA_FAIL;
 422
 423         if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
 424                 return FPGA_FAIL;
 425
 426         if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap,
 427                                     &partialbit))
 428                 return FPGA_FAIL;
 429
 430         dcache_disable();
 431
 432         do {
 433                 buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
 434
 435                 if (zynq_dma_transfer((u32)buf | 1, blocksize >> 2,
 436                                       0xffffffff, 0))
 437                         return FPGA_FAIL;
 438
 439                 bsize -= blocksize;
 440                 pos   += blocksize;
 441
 442                 if (fs_set_blk_dev(interface, dev_part, fstype))
 443                         return FPGA_FAIL;
 444
 445                 if (bsize > blocksize) {
 446                         if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
 447                                 return FPGA_FAIL;
 448                 } else {
 449                         if (fs_read(filename, (u32) buf, pos, bsize, &actread) < 0)
 450                                 return FPGA_FAIL;
 451                 }
 452         } while (bsize > blocksize);
 453
 454         buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
 455
 456         if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
 457                 return FPGA_FAIL;
 458
 459         dcache_enable();
 460
 461         isr_status = readl(&devcfg_base->int_sts);
 462
 463         /* Check FPGA configuration completion */
 464         ts = get_timer(0);
 465         while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
 466                 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
 467                         printf("%s: Timeout wait for FPGA to config\n",
 468                                __func__);
 469                         return FPGA_FAIL;
 470                 }
 471                 isr_status = readl(&devcfg_base->int_sts);
 472         }
 473
 474         debug("%s: FPGA config done\n", __func__);
 475
 476         if (!partialbit)
 477                 zynq_slcr_devcfg_enable();
 478
 479         return FPGA_SUCCESS;
 480 }
 481 #endif
 482
 483 static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 484 {
 485         return FPGA_FAIL;
 486 }
 487
 488 struct xilinx_fpga_op zynq_op = {
 489         .load = zynq_load,
 490 #if defined(CONFIG_CMD_FPGA_LOADFS)
 491         .loadfs = zynq_loadfs,
 492 #endif
 493         .dump = zynq_dump,
 494         .info = zynq_info,
 495 };