drivers/i2c/davinci_i2c.c

   1 /*
   2  * TI DaVinci (TMS320DM644x) I2C driver.
   3  *
   4  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   5  *
   6  * --------------------------------------------------------
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <i2c.h>
  29 #include <asm/arch/hardware.h>
  30 #include <asm/arch/i2c_defs.h>
  31
  32 #define CHECK_NACK() \
  33         do {\
  34                 if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\
  35                         REG(I2C_CON) = 0;\
  36                         return(1);\
  37                 }\
  38         } while (0)
  39
  40
  41 static int wait_for_bus(void)
  42 {
  43         int     stat, timeout;
  44
  45         REG(I2C_STAT) = 0xffff;
  46
  47         for (timeout = 0; timeout < 10; timeout++) {
  48                 if (!((stat = REG(I2C_STAT)) & I2C_STAT_BB)) {
  49                         REG(I2C_STAT) = 0xffff;
  50                         return(0);
  51                 }
  52
  53                 REG(I2C_STAT) = stat;
  54                 udelay(50000);
  55         }
  56
  57         REG(I2C_STAT) = 0xffff;
  58         return(1);
  59 }
  60
  61
  62 static int poll_i2c_irq(int mask)
  63 {
  64         int     stat, timeout;
  65
  66         for (timeout = 0; timeout < 10; timeout++) {
  67                 udelay(1000);
  68                 stat = REG(I2C_STAT);
  69                 if (stat & mask) {
  70                         return(stat);
  71                 }
  72         }
  73
  74         REG(I2C_STAT) = 0xffff;
  75         return(stat | I2C_TIMEOUT);
  76 }
  77
  78
  79 void flush_rx(void)
  80 {
  81         int     dummy;
  82
  83         while (1) {
  84                 if (!(REG(I2C_STAT) & I2C_STAT_RRDY))
  85                         break;
  86
  87                 dummy = REG(I2C_DRR);
  88                 REG(I2C_STAT) = I2C_STAT_RRDY;
  89                 udelay(1000);
  90         }
  91 }
  92
  93
  94 void i2c_init(int speed, int slaveadd)
  95 {
  96         u_int32_t       div, psc;
  97
  98         if (REG(I2C_CON) & I2C_CON_EN) {
  99                 REG(I2C_CON) = 0;
 100                 udelay (50000);
 101         }
 102
 103         psc = 2;
 104         div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */
 105         REG(I2C_PSC) = psc;                     /* 27MHz / (2 + 1) = 9MHz */
 106         REG(I2C_SCLL) = (div * 50) / 100;       /* 50% Duty */
 107         REG(I2C_SCLH) = div - REG(I2C_SCLL);
 108
 109         REG(I2C_OA) = slaveadd;
 110         REG(I2C_CNT) = 0;
 111
 112         /* Interrupts must be enabled or I2C module won't work */
 113         REG(I2C_IE) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE |
 114                 I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE;
 115
 116         /* Now enable I2C controller (get it out of reset) */
 117         REG(I2C_CON) = I2C_CON_EN;
 118
 119         udelay(1000);
 120 }
 121
 122 int i2c_set_bus_speed(unsigned int speed)
 123 {
 124         i2c_init(speed, CONFIG_SYS_I2C_SLAVE);
 125         return 0;
 126 }
 127
 128 int i2c_probe(u_int8_t chip)
 129 {
 130         int     rc = 1;
 131
 132         if (chip == REG(I2C_OA)) {
 133                 return(rc);
 134         }
 135
 136         REG(I2C_CON) = 0;
 137         if (wait_for_bus()) {return(1);}
 138
 139         /* try to read one byte from current (or only) address */
 140         REG(I2C_CNT) = 1;
 141         REG(I2C_SA) = chip;
 142         REG(I2C_CON) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP);
 143         udelay (50000);
 144
 145         if (!(REG(I2C_STAT) & I2C_STAT_NACK)) {
 146                 rc = 0;
 147                 flush_rx();
 148                 REG(I2C_STAT) = 0xffff;
 149         } else {
 150                 REG(I2C_STAT) = 0xffff;
 151                 REG(I2C_CON) |= I2C_CON_STP;
 152                 udelay(20000);
 153                 if (wait_for_bus()) {return(1);}
 154         }
 155
 156         flush_rx();
 157         REG(I2C_STAT) = 0xffff;
 158         REG(I2C_CNT) = 0;
 159         return(rc);
 160 }
 161
 162
 163 int i2c_read(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len)
 164 {
 165         u_int32_t       tmp;
 166         int             i;
 167
 168         if ((alen < 0) || (alen > 2)) {
 169                 printf("%s(): bogus address length %x\n", __FUNCTION__, alen);
 170                 return(1);
 171         }
 172
 173         if (wait_for_bus()) {return(1);}
 174
 175         if (alen != 0) {
 176                 /* Start address phase */
 177                 tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX;
 178                 REG(I2C_CNT) = alen;
 179                 REG(I2C_SA) = chip;
 180                 REG(I2C_CON) = tmp;
 181
 182                 tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
 183
 184                 CHECK_NACK();
 185
 186                 switch (alen) {
 187                         case 2:
 188                                 /* Send address MSByte */
 189                                 if (tmp & I2C_STAT_XRDY) {
 190                                         REG(I2C_DXR) = (addr >> 8) & 0xff;
 191                                 } else {
 192                                         REG(I2C_CON) = 0;
 193                                         return(1);
 194                                 }
 195
 196                                 tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
 197
 198                                 CHECK_NACK();
 199                                 /* No break, fall through */
 200                         case 1:
 201                                 /* Send address LSByte */
 202                                 if (tmp & I2C_STAT_XRDY) {
 203                                         REG(I2C_DXR) = addr & 0xff;
 204                                 } else {
 205                                         REG(I2C_CON) = 0;
 206                                         return(1);
 207                                 }
 208
 209                                 tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK | I2C_STAT_ARDY);
 210
 211                                 CHECK_NACK();
 212
 213                                 if (!(tmp & I2C_STAT_ARDY)) {
 214                                         REG(I2C_CON) = 0;
 215                                         return(1);
 216                                 }
 217                 }
 218         }
 219
 220         /* Address phase is over, now read 'len' bytes and stop */
 221         tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP;
 222         REG(I2C_CNT) = len & 0xffff;
 223         REG(I2C_SA) = chip;
 224         REG(I2C_CON) = tmp;
 225
 226         for (i = 0; i < len; i++) {
 227                 tmp = poll_i2c_irq(I2C_STAT_RRDY | I2C_STAT_NACK | I2C_STAT_ROVR);
 228
 229                 CHECK_NACK();
 230
 231                 if (tmp & I2C_STAT_RRDY) {
 232                         buf[i] = REG(I2C_DRR);
 233                 } else {
 234                         REG(I2C_CON) = 0;
 235                         return(1);
 236                 }
 237         }
 238
 239         tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK);
 240
 241         CHECK_NACK();
 242
 243         if (!(tmp & I2C_STAT_SCD)) {
 244                 REG(I2C_CON) = 0;
 245                 return(1);
 246         }
 247
 248         flush_rx();
 249         REG(I2C_STAT) = 0xffff;
 250         REG(I2C_CNT) = 0;
 251         REG(I2C_CON) = 0;
 252
 253         return(0);
 254 }
 255
 256
 257 int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len)
 258 {
 259         u_int32_t       tmp;
 260         int             i;
 261
 262         if ((alen < 0) || (alen > 2)) {
 263                 printf("%s(): bogus address length %x\n", __FUNCTION__, alen);
 264                 return(1);
 265         }
 266         if (len < 0) {
 267                 printf("%s(): bogus length %x\n", __FUNCTION__, len);
 268                 return(1);
 269         }
 270
 271         if (wait_for_bus()) {return(1);}
 272
 273         /* Start address phase */
 274         tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP;
 275         REG(I2C_CNT) = (alen == 0) ? len & 0xffff : (len & 0xffff) + alen;
 276         REG(I2C_SA) = chip;
 277         REG(I2C_CON) = tmp;
 278
 279         switch (alen) {
 280                 case 2:
 281                         /* Send address MSByte */
 282                         tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
 283
 284                         CHECK_NACK();
 285
 286                         if (tmp & I2C_STAT_XRDY) {
 287                                 REG(I2C_DXR) = (addr >> 8) & 0xff;
 288                         } else {
 289                                 REG(I2C_CON) = 0;
 290                                 return(1);
 291                         }
 292                         /* No break, fall through */
 293                 case 1:
 294                         /* Send address LSByte */
 295                         tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
 296
 297                         CHECK_NACK();
 298
 299                         if (tmp & I2C_STAT_XRDY) {
 300                                 REG(I2C_DXR) = addr & 0xff;
 301                         } else {
 302                                 REG(I2C_CON) = 0;
 303                                 return(1);
 304                         }
 305         }
 306
 307         for (i = 0; i < len; i++) {
 308                 tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
 309
 310                 CHECK_NACK();
 311
 312                 if (tmp & I2C_STAT_XRDY) {
 313                         REG(I2C_DXR) = buf[i];
 314                 } else {
 315                         return(1);
 316                 }
 317         }
 318
 319         tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK);
 320
 321         CHECK_NACK();
 322
 323         if (!(tmp & I2C_STAT_SCD)) {
 324                 REG(I2C_CON) = 0;
 325                 return(1);
 326         }
 327
 328         flush_rx();
 329         REG(I2C_STAT) = 0xffff;
 330         REG(I2C_CNT) = 0;
 331         REG(I2C_CON) = 0;
 332
 333         return(0);
 334 }