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Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'
[karo-tx-uboot.git] / drivers / i2c / omap24xx_i2c.c
1 /*
2  * Basic I2C functions
3  *
4  * Copyright (c) 2004 Texas Instruments
5  *
6  * This package is free software;  you can redistribute it and/or
7  * modify it under the terms of the license found in the file
8  * named COPYING that should have accompanied this file.
9  *
10  * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
13  *
14  * Author: Jian Zhang jzhang@ti.com, Texas Instruments
15  *
16  * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
17  * Rewritten to fit into the current U-Boot framework
18  *
19  * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
20  *
21  * Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions
22  * New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
23  * (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older
24  * OMAPs and derivatives as well. The only anticipated exception would
25  * be the OMAP2420, which shall require driver modification.
26  * - Rewritten i2c_read to operate correctly with all types of chips
27  *   (old function could not read consistent data from some I2C slaves).
28  * - Optimized i2c_write.
29  * - New i2c_probe, performs write access vs read. The old probe could
30  *   hang the system under certain conditions (e.g. unconfigured pads).
31  * - The read/write/probe functions try to identify unconfigured bus.
32  * - Status functions now read irqstatus_raw as per TRM guidelines
33  *   (except for OMAP243X and OMAP34XX).
34  * - Driver now supports up to I2C5 (OMAP5).
35  */
36
37 #include <common.h>
38
39 #include <asm/arch/i2c.h>
40 #include <asm/io.h>
41
42 #include "omap24xx_i2c.h"
43
44 DECLARE_GLOBAL_DATA_PTR;
45
46 #define I2C_TIMEOUT     1000
47
48 /* Absolutely safe for status update at 100 kHz I2C: */
49 #define I2C_WAIT        200
50
51 static int wait_for_bb(void);
52 static u16 wait_for_event(void);
53 static void flush_fifo(void);
54
55 /*
56  * For SPL boot some boards need i2c before SDRAM is initialised so force
57  * variables to live in SRAM
58  */
59 static struct i2c __attribute__((section (".data"))) *i2c_base =
60                                         (struct i2c *)I2C_DEFAULT_BASE;
61 static unsigned int __attribute__((section (".data"))) bus_initialized[I2C_BUS_MAX] =
62                                         { [0 ... (I2C_BUS_MAX-1)] = 0 };
63 static unsigned int __attribute__((section (".data"))) current_bus = 0;
64
65 void i2c_init(int speed, int slaveadd)
66 {
67         int psc, fsscll, fssclh;
68         int hsscll = 0, hssclh = 0;
69         u32 scll, sclh;
70         int timeout = I2C_TIMEOUT;
71
72         /* Only handle standard, fast and high speeds */
73         if ((speed != OMAP_I2C_STANDARD) &&
74             (speed != OMAP_I2C_FAST_MODE) &&
75             (speed != OMAP_I2C_HIGH_SPEED)) {
76                 printf("Error : I2C unsupported speed %d\n", speed);
77                 return;
78         }
79
80         psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
81         psc -= 1;
82         if (psc < I2C_PSC_MIN) {
83                 printf("Error : I2C unsupported prescalar %d\n", psc);
84                 return;
85         }
86
87         if (speed == OMAP_I2C_HIGH_SPEED) {
88                 /* High speed */
89
90                 /* For first phase of HS mode */
91                 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
92                         (2 * OMAP_I2C_FAST_MODE);
93
94                 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
95                 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
96                 if (((fsscll < 0) || (fssclh < 0)) ||
97                     ((fsscll > 255) || (fssclh > 255))) {
98                         puts("Error : I2C initializing first phase clock\n");
99                         return;
100                 }
101
102                 /* For second phase of HS mode */
103                 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
104
105                 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
106                 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
107                 if (((fsscll < 0) || (fssclh < 0)) ||
108                     ((fsscll > 255) || (fssclh > 255))) {
109                         puts("Error : I2C initializing second phase clock\n");
110                         return;
111                 }
112
113                 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
114                 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
115
116         } else {
117                 /* Standard and fast speed */
118                 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
119
120                 fsscll -= I2C_FASTSPEED_SCLL_TRIM;
121                 fssclh -= I2C_FASTSPEED_SCLH_TRIM;
122                 if (((fsscll < 0) || (fssclh < 0)) ||
123                     ((fsscll > 255) || (fssclh > 255))) {
124                         puts("Error : I2C initializing clock\n");
125                         return;
126                 }
127
128                 scll = (unsigned int)fsscll;
129                 sclh = (unsigned int)fssclh;
130         }
131
132         if (readw(&i2c_base->con) & I2C_CON_EN) {
133                 writew(0, &i2c_base->con);
134                 udelay(50000);
135         }
136
137         writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
138         udelay(1000);
139
140         writew(I2C_CON_EN, &i2c_base->con);
141         while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
142                 if (timeout <= 0) {
143                         puts("ERROR: Timeout in soft-reset\n");
144                         return;
145                 }
146                 udelay(1000);
147         }
148
149         writew(0, &i2c_base->con);
150         writew(psc, &i2c_base->psc);
151         writew(scll, &i2c_base->scll);
152         writew(sclh, &i2c_base->sclh);
153
154         /* own address */
155         writew(slaveadd, &i2c_base->oa);
156         writew(I2C_CON_EN, &i2c_base->con);
157 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
158         /*
159          * Have to enable interrupts for OMAP2/3, these IPs don't have
160          * an 'irqstatus_raw' register and we shall have to poll 'stat'
161          */
162         writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
163                I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
164 #endif
165         udelay(1000);
166         flush_fifo();
167         writew(0xFFFF, &i2c_base->stat);
168         writew(0, &i2c_base->cnt);
169
170         if (gd->flags & GD_FLG_RELOC)
171                 bus_initialized[current_bus] = 1;
172 }
173
174 static void flush_fifo(void)
175 {       u16 stat;
176
177         /* note: if you try and read data when its not there or ready
178          * you get a bus error
179          */
180         while (1) {
181                 stat = readw(&i2c_base->stat);
182                 if (stat == I2C_STAT_RRDY) {
183                         readb(&i2c_base->data);
184                         writew(I2C_STAT_RRDY, &i2c_base->stat);
185                         udelay(1000);
186                 } else
187                         break;
188         }
189 }
190
191 /*
192  * i2c_probe: Use write access. Allows to identify addresses that are
193  *            write-only (like the config register of dual-port EEPROMs)
194  */
195 int i2c_probe(uchar chip)
196 {
197         u16 status;
198         int res = 1; /* default = fail */
199
200         if (chip == readw(&i2c_base->oa))
201                 return res;
202
203         /* Wait until bus is free */
204         if (wait_for_bb())
205                 return res;
206
207         /* No data transfer, slave addr only */
208         writew(0, &i2c_base->cnt);
209         /* Set slave address */
210         writew(chip, &i2c_base->sa);
211         /* Stop bit needed here */
212         writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
213                I2C_CON_STP, &i2c_base->con);
214
215         status = wait_for_event();
216
217         if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
218                 /*
219                  * With current high-level command implementation, notifying
220                  * the user shall flood the console with 127 messages. If
221                  * silent exit is desired upon unconfigured bus, remove the
222                  * following 'if' section:
223                  */
224                 if (status == I2C_STAT_XRDY)
225                         printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
226                                current_bus, status);
227
228                 goto pr_exit;
229         }
230
231         /* Check for ACK (!NAK) */
232         if (!(status & I2C_STAT_NACK)) {
233                 res = 0;                        /* Device found */
234                 udelay(I2C_WAIT);               /* Required by AM335X in SPL */
235                 /* Abort transfer (force idle state) */
236                 writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
237                 udelay(1000);
238                 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX |
239                        I2C_CON_STP, &i2c_base->con);            /* STP */
240         }
241 pr_exit:
242         flush_fifo();
243         writew(0xFFFF, &i2c_base->stat);
244         writew(0, &i2c_base->cnt);
245         return res;
246 }
247
248 /*
249  * i2c_read: Function now uses a single I2C read transaction with bulk transfer
250  *           of the requested number of bytes (note that the 'i2c md' command
251  *           limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is
252  *           defined in the board config header, this transaction shall be with
253  *           Repeated Start (Sr) between the address and data phases; otherwise
254  *           Stop-Start (P-S) shall be used (some I2C chips do require a P-S).
255  *           The address (reg offset) may be 0, 1 or 2 bytes long.
256  *           Function now reads correctly from chips that return more than one
257  *           byte of data per addressed register (like TI temperature sensors),
258  *           or that do not need a register address at all (such as some clock
259  *           distributors).
260  */
261 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
262 {
263         int i2c_error = 0;
264         u16 status;
265
266         if (alen < 0) {
267                 puts("I2C read: addr len < 0\n");
268                 return 1;
269         }
270         if (len < 0) {
271                 puts("I2C read: data len < 0\n");
272                 return 1;
273         }
274         if (buffer == NULL) {
275                 puts("I2C read: NULL pointer passed\n");
276                 return 1;
277         }
278
279         if (alen > 2) {
280                 printf("I2C read: addr len %d not supported\n", alen);
281                 return 1;
282         }
283
284         if (addr + len > (1 << 16)) {
285                 puts("I2C read: address out of range\n");
286                 return 1;
287         }
288
289         /* Wait until bus not busy */
290         if (wait_for_bb())
291                 return 1;
292
293         /* Zero, one or two bytes reg address (offset) */
294         writew(alen, &i2c_base->cnt);
295         /* Set slave address */
296         writew(chip, &i2c_base->sa);
297
298         if (alen) {
299                 /* Must write reg offset first */
300 #ifdef CONFIG_I2C_REPEATED_START
301                 /* No stop bit, use Repeated Start (Sr) */
302                 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
303                        I2C_CON_TRX, &i2c_base->con);
304 #else
305                 /* Stop - Start (P-S) */
306                 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP |
307                        I2C_CON_TRX, &i2c_base->con);
308 #endif
309                 /* Send register offset */
310                 while (1) {
311                         status = wait_for_event();
312                         /* Try to identify bus that is not padconf'd for I2C */
313                         if (status == I2C_STAT_XRDY) {
314                                 i2c_error = 2;
315                                 printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
316                                        current_bus, status);
317                                 goto rd_exit;
318                         }
319                         if (status == 0 || status & I2C_STAT_NACK) {
320                                 i2c_error = 1;
321                                 printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",
322                                        status);
323                                 goto rd_exit;
324                         }
325                         if (alen) {
326                                 if (status & I2C_STAT_XRDY) {
327                                         alen--;
328                                         /* Do we have to use byte access? */
329                                         writeb((addr >> (8 * alen)) & 0xff,
330                                                &i2c_base->data);
331                                         writew(I2C_STAT_XRDY, &i2c_base->stat);
332                                 }
333                         }
334                         if (status & I2C_STAT_ARDY) {
335                                 writew(I2C_STAT_ARDY, &i2c_base->stat);
336                                 break;
337                         }
338                 }
339         }
340         /* Set slave address */
341         writew(chip, &i2c_base->sa);
342         /* Read len bytes from slave */
343         writew(len, &i2c_base->cnt);
344         /* Need stop bit here */
345         writew(I2C_CON_EN | I2C_CON_MST |
346                I2C_CON_STT | I2C_CON_STP,
347                &i2c_base->con);
348
349         /* Receive data */
350         while (1) {
351                 status = wait_for_event();
352                 /*
353                  * Try to identify bus that is not padconf'd for I2C. This
354                  * state could be left over from previous transactions if
355                  * the address phase is skipped due to alen=0.
356                  */
357                 if (status == I2C_STAT_XRDY) {
358                         i2c_error = 2;
359                         printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
360                                current_bus, status);
361                         goto rd_exit;
362                 }
363                 if (status == 0 || status & I2C_STAT_NACK) {
364                         i2c_error = 1;
365                         goto rd_exit;
366                 }
367                 if (status & I2C_STAT_RRDY) {
368                         *buffer++ = readb(&i2c_base->data);
369                         writew(I2C_STAT_RRDY, &i2c_base->stat);
370                 }
371                 if (status & I2C_STAT_ARDY) {
372                         writew(I2C_STAT_ARDY, &i2c_base->stat);
373                         break;
374                 }
375         }
376
377 rd_exit:
378         flush_fifo();
379         writew(0xFFFF, &i2c_base->stat);
380         writew(0, &i2c_base->cnt);
381         return i2c_error;
382 }
383
384 /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
385 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
386 {
387         int i;
388         u16 status;
389         int i2c_error = 0;
390
391         if (alen < 0) {
392                 puts("I2C write: addr len < 0\n");
393                 return 1;
394         }
395
396         if (len < 0) {
397                 puts("I2C write: data len < 0\n");
398                 return 1;
399         }
400
401         if (buffer == NULL) {
402                 puts("I2C write: NULL pointer passed\n");
403                 return 1;
404         }
405
406         if (alen > 2) {
407                 printf("I2C write: addr len %d not supported\n", alen);
408                 return 1;
409         }
410
411         if (addr + len > (1 << 16)) {
412                 printf("I2C write: address 0x%x + 0x%x out of range\n",
413                        addr, len);
414                 return 1;
415         }
416
417         /* Wait until bus not busy */
418         if (wait_for_bb())
419                 return 1;
420
421         /* Start address phase - will write regoffset + len bytes data */
422         writew(alen + len, &i2c_base->cnt);
423         /* Set slave address */
424         writew(chip, &i2c_base->sa);
425         /* Stop bit needed here */
426         writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
427                I2C_CON_STP, &i2c_base->con);
428
429         while (alen) {
430                 /* Must write reg offset (one or two bytes) */
431                 status = wait_for_event();
432                 /* Try to identify bus that is not padconf'd for I2C */
433                 if (status == I2C_STAT_XRDY) {
434                         i2c_error = 2;
435                         printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
436                                current_bus, status);
437                         goto wr_exit;
438                 }
439                 if (status == 0 || status & I2C_STAT_NACK) {
440                         i2c_error = 1;
441                         printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",
442                                status);
443                         goto wr_exit;
444                 }
445                 if (status & I2C_STAT_XRDY) {
446                         alen--;
447                         writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data);
448                         writew(I2C_STAT_XRDY, &i2c_base->stat);
449                 } else {
450                         i2c_error = 1;
451                         printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n",
452                                status);
453                         goto wr_exit;
454                 }
455         }
456         /* Address phase is over, now write data */
457         for (i = 0; i < len; i++) {
458                 status = wait_for_event();
459                 if (status == 0 || status & I2C_STAT_NACK) {
460                         i2c_error = 1;
461                         printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
462                                status);
463                         goto wr_exit;
464                 }
465                 if (status & I2C_STAT_XRDY) {
466                         writeb(buffer[i], &i2c_base->data);
467                         writew(I2C_STAT_XRDY, &i2c_base->stat);
468                 } else {
469                         i2c_error = 1;
470                         printf("i2c_write: bus not ready for data Tx (i=%d)\n",
471                                i);
472                         goto wr_exit;
473                 }
474         }
475
476 wr_exit:
477         flush_fifo();
478         writew(0xFFFF, &i2c_base->stat);
479         writew(0, &i2c_base->cnt);
480         return i2c_error;
481 }
482
483 /*
484  * Wait for the bus to be free by checking the Bus Busy (BB)
485  * bit to become clear
486  */
487 static int wait_for_bb(void)
488 {
489         int timeout = I2C_TIMEOUT;
490         u16 stat;
491
492         writew(0xFFFF, &i2c_base->stat);        /* clear current interrupts...*/
493 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
494         while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
495 #else
496         /* Read RAW status */
497         while ((stat = readw(&i2c_base->irqstatus_raw) &
498                 I2C_STAT_BB) && timeout--) {
499 #endif
500                 writew(stat, &i2c_base->stat);
501                 udelay(I2C_WAIT);
502         }
503
504         if (timeout <= 0) {
505                 printf("Timed out in wait_for_bb: status=%04x\n",
506                        stat);
507                 return 1;
508         }
509         writew(0xFFFF, &i2c_base->stat);         /* clear delayed stuff*/
510         return 0;
511 }
512
513 /*
514  * Wait for the I2C controller to complete current action
515  * and update status
516  */
517 static u16 wait_for_event(void)
518 {
519         u16 status;
520         int timeout = I2C_TIMEOUT;
521
522         do {
523                 udelay(I2C_WAIT);
524 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
525                 status = readw(&i2c_base->stat);
526 #else
527                 /* Read RAW status */
528                 status = readw(&i2c_base->irqstatus_raw);
529 #endif
530         } while (!(status &
531                    (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
532                     I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
533                     I2C_STAT_AL)) && timeout--);
534
535         if (timeout <= 0) {
536                 printf("Timed out in wait_for_event: status=%04x\n",
537                        status);
538                 /*
539                  * If status is still 0 here, probably the bus pads have
540                  * not been configured for I2C, and/or pull-ups are missing.
541                  */
542                 printf("Check if pads/pull-ups of bus %d are properly configured\n",
543                        current_bus);
544                 writew(0xFFFF, &i2c_base->stat);
545                 status = 0;
546         }
547
548         return status;
549 }
550
551 int i2c_set_bus_num(unsigned int bus)
552 {
553         if (bus >= I2C_BUS_MAX) {
554                 printf("Bad bus: %x\n", bus);
555                 return -1;
556         }
557
558         switch (bus) {
559         default:
560                 bus = 0;        /* Fall through */
561         case 0:
562                 i2c_base = (struct i2c *)I2C_BASE1;
563                 break;
564         case 1:
565                 i2c_base = (struct i2c *)I2C_BASE2;
566                 break;
567 #if (I2C_BUS_MAX > 2)
568         case 2:
569                 i2c_base = (struct i2c *)I2C_BASE3;
570                 break;
571 #if (I2C_BUS_MAX > 3)
572         case 3:
573                 i2c_base = (struct i2c *)I2C_BASE4;
574                 break;
575 #if (I2C_BUS_MAX > 4)
576         case 4:
577                 i2c_base = (struct i2c *)I2C_BASE5;
578                 break;
579 #endif
580 #endif
581 #endif
582         }
583
584         current_bus = bus;
585
586         if (!bus_initialized[current_bus])
587                 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
588
589         return 0;
590 }
591
592 int i2c_get_bus_num(void)
593 {
594         return (int) current_bus;
595 }